CN113327974A - Field effect transistor and method for manufacturing the same - Google Patents

Field effect transistor and method for manufacturing the same Download PDF

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Publication number
CN113327974A
CN113327974A CN202110134611.5A CN202110134611A CN113327974A CN 113327974 A CN113327974 A CN 113327974A CN 202110134611 A CN202110134611 A CN 202110134611A CN 113327974 A CN113327974 A CN 113327974A
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gate
effect transistor
field effect
vertical plane
channel length
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CN113327974B (en
Inventor
刘佑铭
何学缅
司徒道海
刘金营
吴永玉
李敏
李天慧
李剑波
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SHANGHAI ADVANCED SEMICONDUCTO
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation

Abstract

The invention provides a field effect transistor and a manufacturing method thereof, wherein the field effect transistor comprises a buried grid, and the buried grid comprises a first end grid, a central grid and a second end grid in the horizontal direction perpendicular to the length of a channel; wherein: the cross-sectional area of the first end gate on a vertical plane parallel to the channel length is larger than the cross-sectional area of the central gate on a vertical plane parallel to the channel length; the second end gate has a larger cross-sectional area in a vertical plane parallel to the channel length than the center gate. The field effect transistor adopts a three-dimensional structure to replace a traditional plane structure, realizes three-dimensional wrapping of a channel, increases the area of the width of the channel, increases the control area of the channel under the condition of not increasing the area of an active region, improves the grid control capability, stabilizes the threshold voltage and increases the saturation current.

Description

Field effect transistor and method for manufacturing the same
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a field effect transistor and a manufacturing method thereof.
Background
For a traditional planar MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) structure, with the size reduction of an MOSFET device, a short channel Effect is more and more serious, the control capability of a gate to a channel is gradually weakened, and when the control capability is serious, a source end and a drain end are easily short-circuited, saturation current is reduced, switching characteristics are reduced, and the like.
Disclosure of Invention
The invention provides a field effect transistor and a manufacturing method thereof, aiming at overcoming the defects that the short channel effect is more and more serious, the control capability of a grid electrode to a channel is gradually weakened, and the problems that a source end and a drain end are easy to be short-circuited, the saturation current is reduced, the switching characteristic is reduced and the like are caused in serious conditions along with the reduction of the size of an MOSFET device in the prior art.
The invention solves the technical problems through the following technical scheme:
the invention provides a field effect transistor, which comprises a buried grid, wherein the buried grid comprises a first end grid, a central grid and a second end grid in the horizontal direction perpendicular to the length of a channel; wherein:
the first end gate has a larger cross-sectional area in a vertical plane parallel to the channel length than the center gate;
the second end gate has a larger cross-sectional area in a vertical plane parallel to the channel length than the center gate.
Preferably, the first end gate and the second end gate are symmetrically distributed at two ends of the central gate.
Preferably, the section of the buried gate on a vertical plane perpendicular to the channel length is in an inverted concave shape.
Preferably, the buried gate is in an inverted saddle shape.
Preferably, the buried gate comprises a gate dielectric layer and a gate electrode;
the gate dielectric layer is a high-K metal (a gate dielectric material) layer and the gate electrode is a metal gate, or the gate dielectric layer is a gate oxide layer and the gate electrode is a polysilicon gate.
Preferably, the cross-sectional area of the end of the first end gate away from the central gate on a vertical plane parallel to the channel length is equal to the cross-sectional area of the central gate on a vertical plane parallel to the channel length;
the cross-sectional area of the end of the second end gate remote from the center gate on a vertical plane parallel to the channel length is equal to the cross-sectional area of the center gate on a vertical plane parallel to the channel length.
The present invention also provides a manufacturing method of a field effect transistor, the manufacturing method being used for manufacturing the aforementioned field effect transistor, the manufacturing method including:
carrying out mask photoresist deposition on the gate channel;
etching a groove by a dry method;
and carrying out wet etching on two ends of the groove in the horizontal direction perpendicular to the length of the groove so as to enlarge the sectional areas of the two ends on a vertical surface parallel to the length of the groove.
Preferably, the step of performing wet etching on both ends of the trench in a horizontal direction perpendicular to the length of the trench specifically includes:
and etching two ends of the groove in an STI (Shallow Trench Isolation) area in a horizontal direction vertical to the length of the groove by using hydrofluoric acid soaking.
Preferably, the manufacturing method further comprises:
oxidizing the gate oxide layer;
depositing a polysilicon gate;
or the like, or, alternatively,
the manufacturing method further includes:
depositing a high-K layer;
and depositing a metal gate.
The positive progress effects of the invention are as follows: the field effect transistor adopts a three-dimensional structure to replace a traditional plane structure, realizes three-dimensional wrapping of a channel, increases the area of the width of the channel, increases the control area of the channel under the condition of not increasing the area of an active region, improves the grid control capability, stabilizes the threshold voltage and increases the saturation current.
Drawings
Fig. 1 is a schematic structural view of a field effect transistor according to embodiment 1 of the present invention.
Fig. 2 is a schematic cross-sectional view of a buried gate in a field effect transistor according to embodiment 1 of the present invention, in a vertical plane perpendicular to a channel length.
Fig. 3 is a schematic cross-sectional view of another buried gate in the field effect transistor of embodiment 1 of the present invention, in a vertical plane perpendicular to the channel length.
Fig. 4 is a partial flowchart of a method for manufacturing a field effect transistor according to embodiment 2 of the present invention.
Fig. 5 is a schematic top view of the STI region and the buried gate in the method for manufacturing the field effect transistor according to embodiment 2 of the present invention.
Fig. 6 is a flowchart of another part of the manufacturing method of the field effect transistor of embodiment 2 of the present invention.
Fig. 7 is another partial flowchart of a method for manufacturing a field effect transistor according to embodiment 2 of the present invention.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Example 1
The present embodiment provides a field effect transistor. Referring to fig. 1 and 2, the field effect transistor includes a buried gate 1, the buried gate 1 includes a first end gate 11, a central gate 12, and a second end gate 13 in a horizontal direction perpendicular to a channel length, and a dotted line within the buried gate in fig. 2 indicates a boundary line of the central gate 12 with the first end gate 11 and the second end gate 13.
Wherein:
the cross-sectional area of the first end gate 11 in a vertical plane parallel to the channel length is larger than the cross-sectional area of the center gate 12 in a vertical plane parallel to the channel length. The dashed line running through the first end gate 11 on the left in fig. 2 represents a vertical plane parallel to the channel length, the graph above the dashed line representing a cross section 111 of the first end gate 11 on the vertical plane; the dashed line in fig. 2, which runs through the center gate 12 in the middle, represents a vertical plane parallel to the channel length, and the graph above the dashed line represents a cross section 121 of the center gate 12 on the vertical plane, the area of the cross section 111 being larger than the area of the cross section 121.
The cross-sectional area of the second end gate 13 in a vertical plane parallel to the channel length is larger than the cross-sectional area of the central gate 12 in a vertical plane parallel to the channel length. The dashed line through the second end gate 13 on the right side in fig. 2 represents a vertical plane parallel to the channel length, and the graph above the dashed line represents a cross section 131 of the second end gate 13 on the vertical plane; the dashed line in fig. 2, which runs through the center gate 12 in the middle, represents a vertical plane parallel to the channel length, and the graph above the dashed line represents a cross section 121 of the center gate 12 on the vertical plane, the area of the cross section 131 being larger than the area of the cross section 121.
The field effect transistor of this embodiment has adopted three-dimensional spatial structure to replace traditional planar structure, has realized the three-dimensional parcel to the channel, has increased the area of channel width, has increased the channel control area under the condition that does not increase the active area, has improved the grid control ability, has stabilized threshold voltage, has increased saturated current.
In specific implementation, the first end gate 11 and the second end gate 13 are symmetrically distributed at two ends of the central gate 12.
In specific implementation, the section of the buried gate 1 on a vertical plane perpendicular to the channel length is in an inverted concave shape.
In a specific embodiment, the buried gate 1 has an inverted saddle shape.
In specific implementation, the buried gate 1 includes a gate dielectric layer and a gate electrode. In this embodiment, the gate dielectric layer is preferably a high-K metal layer, and the gate electrode is preferably a metal gate, so as to reduce the thickness of the equivalent oxide layer and improve the gate capacitance. In other embodiments, the gate dielectric layer may be a gate oxide layer, and the gate electrode may be a polysilicon gate.
In this embodiment, the material of the gate electrode is not limited to a metal material, and may include other electrode materials such as Poly (polysilicon); the base material may be a semiconductor material such as single crystal silicon or silicon carbide.
Figure 3 shows a schematic cross-sectional view of another example of a buried gate in a vertical plane perpendicular to the channel length. The shape of the cross section of the first end gate 11, the center gate 12, and the second end gate 13 on the vertical plane perpendicular to the channel length is not limited here. The dotted line in the figure indicates the boundary between the central gate 12 and the first and second end gates 11 and 13.
Specifically, the sectional area of the end of the first end gate 11 remote from the center gate 12 on the vertical plane parallel to the channel length is equal to the sectional area of the center gate 12 on the vertical plane parallel to the channel length.
The cross-sectional area of the end of the second end gate 13 remote from the central gate 12 in a vertical plane parallel to the channel length is equal to the cross-sectional area of the central gate 12 in a vertical plane parallel to the channel length.
The field effect transistor of this embodiment has adopted three-dimensional spatial structure to replace traditional planar structure, has realized the three-dimensional parcel to the channel, has increased the area of channel width, has increased the channel control area under the condition that does not increase the active area, has improved the grid control ability, has stabilized threshold voltage, has increased saturated current.
Example 2
This embodiment provides a manufacturing method of a field effect transistor, which is used to manufacture the field effect transistor in embodiment 1. Referring to fig. 4, the manufacturing method includes:
and S11, performing mask photoresist deposition on the gate channel.
And S12, dry etching the groove.
And S13, performing wet etching on two ends of the groove in the horizontal direction perpendicular to the length of the groove to enlarge the sectional areas of the two ends on the vertical plane parallel to the length of the groove.
After step S13 is completed, the profile structure of the buried gate shown in fig. 2 or fig. 3 in embodiment 1 can be obtained, where wet etching is performed on both ends of the trench to obtain the profile structures of the first end gate and the second end gate, and the portion not subjected to wet etching in the middle is the profile structure of the central gate.
In specific implementation, step S13 specifically includes:
s131, etching two ends of the groove in the STI region in the horizontal direction perpendicular to the length of the channel by using hydrofluoric acid soaking so as to enlarge the sectional areas of the two ends on the vertical surface parallel to the length of the channel. Fig. 5 shows a schematic top view of the STI region 2 and the buried gate 1.
The manufacturing method of the present embodiment may further include a step of manufacturing a gate dielectric layer and a gate electrode of the buried gate after step S13.
Fig. 6 provides an implementation manner, and the manufacturing method further includes, after step S13:
s14, oxidizing the gate oxide layer.
And S15, depositing a polysilicon gate.
Fig. 7 provides another implementation, and the manufacturing method further includes, after step S13:
and S16, depositing a high-K layer.
And S17, depositing a metal gate.
In this embodiment, the possibility of three-dimensional wrapping of the channel by the gate is realized through an Oxide Pull-back (oxidation call back) process after etching. The field effect transistor manufacturing method of the field effect transistor comprises the embedded grid, the embedded grid adopts a three-dimensional structure to replace a traditional planar structure, three-dimensional wrapping of a channel is achieved, the area of the channel width is increased, the channel control area is increased under the condition that the area of an active region is not increased, the grid control capacity is improved, the threshold voltage is stabilized, and the saturation current is increased.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.

Claims (9)

1. A field effect transistor comprising a buried gate comprising, in a horizontal direction perpendicular to a channel length, a first end gate, a center gate, and a second end gate; wherein:
the first end gate has a larger cross-sectional area in a vertical plane parallel to the channel length than the center gate;
the second end gate has a larger cross-sectional area in a vertical plane parallel to the channel length than the center gate.
2. The field effect transistor of claim 1, wherein the first end gate and the second end gate are symmetrically distributed across the center gate.
3. The field effect transistor of claim 2 wherein the buried gate has an inverted concave shape in cross section in a vertical plane perpendicular to the channel length.
4. The field effect transistor of claim 3 wherein said buried gate is in the shape of an inverted saddle.
5. The field effect transistor of claim 1, wherein said buried gate comprises a gate dielectric layer and a gate electrode;
the gate dielectric layer is a high-K metal layer and the gate electrode is a metal gate, or the gate dielectric layer is a gate oxide layer and the gate electrode is a polysilicon gate.
6. The field effect transistor of claim 2,
the cross-sectional area of one end of the first end gate, which is far away from the central gate, on a vertical plane parallel to the channel length is equal to the cross-sectional area of the central gate on the vertical plane parallel to the channel length;
the cross-sectional area of the end of the second end gate remote from the center gate on a vertical plane parallel to the channel length is equal to the cross-sectional area of the center gate on a vertical plane parallel to the channel length.
7. A manufacturing method of a field effect transistor, characterized in that the manufacturing method is used for manufacturing the field effect transistor according to any one of claims 1 to 6, the manufacturing method comprising:
carrying out mask photoresist deposition on the gate channel;
etching a groove by a dry method;
and carrying out wet etching on two ends of the groove in the horizontal direction perpendicular to the length of the groove so as to enlarge the sectional areas of the two ends on a vertical surface parallel to the length of the groove.
8. The method for manufacturing a field effect transistor according to claim 7, wherein the step of wet etching both ends of the trench in a horizontal direction perpendicular to a channel length specifically includes:
and etching two ends of the groove in the STI region in the horizontal direction perpendicular to the length of the groove by using hydrofluoric acid soaking.
9. The method of manufacturing a field effect transistor according to claim 7, further comprising:
oxidizing the gate oxide layer;
depositing a polysilicon gate;
or the like, or, alternatively,
the manufacturing method further includes:
depositing a high-K layer;
and depositing a metal gate.
CN202110134611.5A 2021-01-29 2021-01-29 Field effect transistor and method of manufacturing the same Active CN113327974B (en)

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KR940003075A (en) * 1992-07-01 1994-02-19 김주용 TFT (Thin Film Transistor) Manufacturing Method With Trench Surrounding Gate Structure
JPH0974199A (en) * 1995-01-12 1997-03-18 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacture
US20090166731A1 (en) * 2007-12-26 2009-07-02 Nec Electronics Corporation Vertical-type field-effect transistor and manufacturing method thereof
US20120273859A1 (en) * 2011-04-28 2012-11-01 Elpida Memory, Inc. Semiconductor device and method of forming the same
US20130130455A1 (en) * 2011-11-21 2013-05-23 SK Hynix Inc. Method of manufacturing semiconductor device
US20160172482A1 (en) * 2014-12-10 2016-06-16 Alpha And Omega Semiconductor Incorporated Integrating enhancement mode depleted accumulation/inversion channel devices with mosfets
CN105244319A (en) * 2015-08-28 2016-01-13 西安电子科技大学 Inverted trapezoidal grid CMOS integrated device with strain SiGe channel and preparation method of integrated device
CN106298941A (en) * 2016-09-13 2017-01-04 上海华虹宏力半导体制造有限公司 Shield grid groove power device and manufacture method thereof
WO2018154402A1 (en) * 2017-02-22 2018-08-30 International Business Machines Corporation Fabrication of vertical field effect transistor device with modified vertical fin geometry
CN107871780A (en) * 2017-11-20 2018-04-03 中国科学院上海微系统与信息技术研究所 Field-effect transistor structure and preparation method thereof
CN209045563U (en) * 2018-11-09 2019-06-28 长鑫存储技术有限公司 A kind of buried gate structure
US20200243375A1 (en) * 2019-01-25 2020-07-30 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device having buried gate electrodes
US20200279932A1 (en) * 2019-03-01 2020-09-03 Intel Corporation Planar transistors with wrap-around gates and wrap-around source and drain contacts
CN112071909A (en) * 2019-06-11 2020-12-11 芯恩（青岛）集成电路有限公司 Three-dimensional metal-oxide field effect transistor and preparation method thereof

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