CN113327974B - Field effect transistor and method of manufacturing the same - Google Patents

Field effect transistor and method of manufacturing the same Download PDF

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Publication number
CN113327974B
CN113327974B CN202110134611.5A CN202110134611A CN113327974B CN 113327974 B CN113327974 B CN 113327974B CN 202110134611 A CN202110134611 A CN 202110134611A CN 113327974 B CN113327974 B CN 113327974B
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gate
channel length
vertical plane
effect transistor
cross
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CN113327974A (en
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刘佑铭
何学缅
司徒道海
刘金营
吴永玉
李敏
李天慧
李剑波
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SHANGHAI ADVANCED SEMICONDUCTO
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a field effect transistor and a manufacturing method thereof, wherein the field effect transistor comprises a buried grid, and the buried grid comprises a first end grid, a central grid and a second end grid in the horizontal direction perpendicular to the length of a channel; wherein: the cross-sectional area of the first end gate on a vertical plane parallel to the channel length is greater than the cross-sectional area of the center gate on a vertical plane parallel to the channel length; the second end gate has a cross-sectional area on a vertical plane parallel to the channel length that is greater than a cross-sectional area of the center gate on a vertical plane parallel to the channel length. The field effect transistor adopts a three-dimensional structure to replace a traditional plane structure, realizes three-way wrapping of a channel, increases the area of the width of the channel, increases the control area of the channel under the condition of not increasing the area of an active region, improves the gate control capability, stabilizes the threshold voltage and increases the saturation current.

Description

Field effect transistor and method of manufacturing the same
Technical Field
The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a field effect transistor and a manufacturing method thereof.
Background
For the conventional planar MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) structure, as the size of the MOSFET device is reduced, the short channel effect is more and more serious, and the control capability of the gate to the channel is gradually weakened, so that the source terminal and the drain terminal are easily shorted, the saturation current is reduced, and the switching characteristics are reduced.
Disclosure of Invention
The invention aims to overcome the defects that the short-channel effect is more and more serious along with the reduction of the size of a MOSFET device in the prior art, the control capability of a grid electrode to a channel is gradually weakened, the source end and the drain end are extremely easy to be short-circuited, the saturated current is reduced, the switching characteristic is reduced and the like in severe cases, and provides a field effect transistor and a manufacturing method thereof.
The invention solves the technical problems by the following technical scheme:
the invention provides a field effect transistor, which comprises a buried gate, wherein the buried gate comprises a first end gate, a central gate and a second end gate in the horizontal direction perpendicular to the length of a channel; wherein:
the cross-sectional area of the first end gate on a vertical plane parallel to the channel length is greater than the cross-sectional area of the center gate on a vertical plane parallel to the channel length;
the second end gate has a cross-sectional area on a vertical plane parallel to the channel length that is greater than a cross-sectional area of the center gate on a vertical plane parallel to the channel length.
Preferably, the first end gate and the second end gate are symmetrically distributed at two ends of the central gate.
Preferably, the cross section of the buried gate on a vertical plane perpendicular to the channel length is inverted concave.
Preferably, the buried gate is in the shape of an inverted saddle.
Preferably, the buried gate comprises a gate dielectric layer and a gate electrode;
the gate dielectric layer is a high-K metal (a gate dielectric material) layer and the gate electrode is a metal gate, or the gate dielectric layer is a gate oxide layer and the gate electrode is a polysilicon gate.
Preferably, a cross-sectional area of an end of the first end gate away from the center gate on a vertical plane parallel to the channel length is equal to a cross-sectional area of the center gate on a vertical plane parallel to the channel length;
the cross-sectional area of the end of the second end gate away from the center gate on a vertical plane parallel to the channel length is equal to the cross-sectional area of the center gate on a vertical plane parallel to the channel length.
The invention also provides a manufacturing method of the field effect transistor, which is used for manufacturing the field effect transistor, and comprises the following steps:
mask photoresistance deposition is carried out on the grid channel;
etching a groove by a dry method;
wet etching is performed on two ends of the groove in the horizontal direction perpendicular to the channel length so as to enlarge the sectional area of the two ends on the vertical plane parallel to the channel length.
Preferably, the step of wet etching two ends of the trench in the horizontal direction perpendicular to the channel length specifically includes:
both ends of the trench in the STI (Shallow Trench Isolation ) region in the horizontal direction perpendicular to the channel length are etched using a hydrofluoric acid dip.
Preferably, the manufacturing method further includes:
oxidizing a gate oxide layer;
depositing a polysilicon gate;
or alternatively, the first and second heat exchangers may be,
the manufacturing method further comprises the steps of:
depositing a high-K layer;
and (5) depositing a metal gate.
The invention has the positive progress effects that: the field effect transistor adopts a three-dimensional structure to replace a traditional plane structure, realizes three-way wrapping of a channel, increases the area of the width of the channel, increases the control area of the channel under the condition of not increasing the area of an active region, improves the gate control capability, stabilizes the threshold voltage and increases the saturation current.
Drawings
Fig. 1 is a schematic structural diagram of a field effect transistor according to embodiment 1 of the present invention.
Fig. 2 is a schematic cross-sectional view of a buried gate in a field effect transistor according to embodiment 1 of the present invention in a vertical plane perpendicular to a channel length.
Fig. 3 is a schematic cross-sectional view of another buried gate in a field effect transistor according to embodiment 1 of the present invention in a vertical plane perpendicular to a channel length.
Fig. 4 is a partial flow chart of a manufacturing method of a field effect transistor according to embodiment 2 of the present invention.
Fig. 5 is a schematic top view of STI regions and buried gates in the method of manufacturing a field effect transistor according to embodiment 2 of the present invention.
Fig. 6 is a flowchart of another part of the manufacturing method of the field effect transistor of embodiment 2 of the present invention.
Fig. 7 is a flow chart showing another part of the method for manufacturing a field effect transistor according to embodiment 2 of the present invention.
Detailed Description
The invention is further illustrated by means of the following examples, which are not intended to limit the scope of the invention.
Example 1
The present embodiment provides a field effect transistor. Referring to fig. 1 and 2, the field effect transistor includes a buried gate 1, the buried gate 1 including a first end gate 11, a center gate 12, and a second end gate 13 in a horizontal direction perpendicular to a channel length, and a broken line within the buried gate in fig. 2 indicates a boundary between the center gate 12 and the first and second end gates 11 and 13.
Wherein:
the cross-sectional area of the first end gate 11 on a vertical plane parallel to the channel length is larger than the cross-sectional area of the center gate 12 on a vertical plane parallel to the channel length. The dashed line extending through the first end gate 11 on the left side in fig. 2 represents a vertical plane parallel to the channel length, and the graph above this dashed line represents a cross section 111 of the first end gate 11 on this vertical plane; the dashed line through the central gate 12 in the middle of fig. 2 represents a vertical plane parallel to the channel length, and the graph above this dashed line represents a cross section 121 of the central gate 12 on this vertical plane, the area of the cross section 111 being larger than the area of the cross section 121.
The cross-sectional area of the second end gate 13 on a vertical plane parallel to the channel length is larger than the cross-sectional area of the center gate 12 on a vertical plane parallel to the channel length. The dashed line on the right through the second end gate 13 in fig. 2 represents a vertical plane parallel to the channel length, and the graph above this dashed line represents a cross section 131 of the second end gate 13 on this vertical plane; the dashed line through the central gate 12 in the middle of fig. 2 represents a vertical plane parallel to the channel length, and the graph above this dashed line represents a cross section 121 of the central gate 12 on this vertical plane, the area of the cross section 131 being larger than the area of the cross section 121.
The field effect transistor of the embodiment adopts a three-dimensional structure to replace a traditional plane structure, realizes three-way wrapping of a channel, increases the area of the width of the channel, increases the control area of the channel under the condition of not increasing the area of an active region, improves the gate control capability, stabilizes the threshold voltage and increases the saturation current.
In particular, the first end gate 11 and the second end gate 13 are symmetrically distributed at two ends of the central gate 12.
In particular, the buried gate 1 has an inverted concave shape in cross section on a vertical plane perpendicular to the channel length.
In particular, the buried gate 1 has an inverted saddle shape.
In particular, the buried gate 1 includes a gate dielectric layer and a gate electrode. In this embodiment, the gate dielectric layer is preferably a high-K metal layer, and the gate electrode is preferably a metal gate, so as to facilitate reducing the equivalent oxide thickness and improving the gate capacitance. In other embodiments, the gate dielectric layer may be a gate oxide layer and the gate electrode may be a polysilicon gate.
In the present embodiment, the material of the gate electrode is not limited to a metal material, and may include other electrode materials such as Poly (polysilicon); the substrate material may be a semiconductor material such as monocrystalline silicon or silicon carbide.
Fig. 3 shows a schematic cross-sectional view of another example of a buried gate in a vertical plane perpendicular to the channel length. The shapes of the cross sections of the first end gate 11, the center gate 12, and the second end gate 13 on the vertical plane perpendicular to the channel length are not limited here. The dashed line in the figure shows the boundary between the center gate 12 and the first and second end gates 11 and 13.
Specifically, the cross-sectional area of the end of the first end gate 11 remote from the center gate 12 on a vertical plane parallel to the channel length is equal to the cross-sectional area of the center gate 12 on a vertical plane parallel to the channel length.
The cross-sectional area of the end of the second end gate 13 remote from the center gate 12 on a vertical plane parallel to the channel length is equal to the cross-sectional area of the center gate 12 on a vertical plane parallel to the channel length.
The field effect transistor of the embodiment adopts a three-dimensional structure to replace a traditional plane structure, realizes three-way wrapping of a channel, increases the area of the width of the channel, increases the control area of the channel under the condition of not increasing the area of an active region, improves the gate control capability, stabilizes the threshold voltage and increases the saturation current.
Example 2
The present embodiment provides a manufacturing method of a field effect transistor, which is used for manufacturing the field effect transistor in embodiment 1. Referring to fig. 4, the manufacturing method includes:
s11, carrying out mask photoresist deposition on the gate channel.
S12, etching the groove by a dry method.
And S13, carrying out wet etching on two ends of the groove in the horizontal direction perpendicular to the length of the channel so as to enlarge the sectional area of the two ends on a vertical plane parallel to the length of the channel.
Step S13 is completed, so as to obtain the profile structure of the buried gate shown in fig. 2 or fig. 3 in embodiment 1, where wet etching is performed on both ends of the trench, that is, the profile structure of the first end gate and the second end gate is obtained by etching, and the part where wet etching is not performed in the middle is the profile structure of the central gate.
In specific implementation, step S13 specifically includes:
s131, etching two ends of the groove in the STI region in the horizontal direction perpendicular to the length of the channel by using hydrofluoric acid to soak so as to enlarge the sectional area of the two ends on the vertical plane parallel to the length of the channel. Fig. 5 shows a schematic top view of the STI region 2 and buried gate 1.
The manufacturing method of the present embodiment may further include a step of manufacturing the gate dielectric layer and the gate electrode of the buried gate after step S13.
Fig. 6 provides an implementation, and the manufacturing method further includes, after step S13:
s14, oxidizing the gate oxide layer.
S15, polysilicon gate deposition.
Fig. 7 provides another implementation, where the manufacturing method further includes, after step S13:
s16, depositing a high-K layer.
S17, depositing a metal gate.
In the embodiment, the possibility of three-dimensional wrapping of the grid to the channel is realized through an Oxide Pull-back (oxidation callback) process after etching. The manufacturing method of the field effect transistor of the embodiment manufactures the field effect transistor comprising the buried grid, the buried grid adopts a three-dimensional structure to replace a traditional plane structure, three-way wrapping of a channel is realized, the area of the width of the channel is increased, the control area of the channel is increased under the condition that the area of an active area is not increased, the grid control capability is improved, the threshold voltage is stabilized, and the saturated current is increased.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the invention, but such changes and modifications fall within the scope of the invention.

Claims (8)

1. A field effect transistor comprising a buried gate comprising a first end gate, a center gate, and a second end gate in a horizontal direction perpendicular to a channel length; wherein:
the cross-sectional area of the first end gate on a vertical plane parallel to the channel length is greater than the cross-sectional area of the center gate on a vertical plane parallel to the channel length;
the cross-sectional area of the second end gate on a vertical plane parallel to the channel length is greater than the cross-sectional area of the center gate on a vertical plane parallel to the channel length;
the buried grid is in an inverted saddle shape;
wherein the channel length of the first end gate and the channel length of the second end gate are both greater than the channel length of the center gate;
the first end gate and the second end gate are in direct contact with a source drain.
2. The field effect transistor of claim 1, wherein the first end gate and the second end gate are symmetrically distributed across the center gate.
3. The field effect transistor of claim 2 wherein the buried gate has an inverted recess shape in cross-section in a vertical plane perpendicular to the channel length.
4. The field effect transistor of claim 1 wherein said buried gate comprises a gate dielectric layer and a gate electrode;
the gate dielectric layer is a high-K metal layer and the gate electrode is a metal gate, or the gate dielectric layer is a gate oxide layer and the gate electrode is a polysilicon gate.
5. The field effect transistor of claim 2, wherein,
a cross-sectional area of an end of the first end gate remote from the center gate on a vertical plane parallel to the channel length is equal to a cross-sectional area of the center gate on a vertical plane parallel to the channel length;
the cross-sectional area of the end of the second end gate away from the center gate on a vertical plane parallel to the channel length is equal to the cross-sectional area of the center gate on a vertical plane parallel to the channel length.
6. A method of manufacturing a field effect transistor, characterized in that the method of manufacturing is used for manufacturing a field effect transistor according to any of claims 1-5, the method of manufacturing comprising:
mask photoresistance deposition is carried out on the grid channel;
etching a groove by a dry method;
wet etching is performed on two ends of the groove in the horizontal direction perpendicular to the channel length so as to enlarge the sectional area of the two ends on the vertical plane parallel to the channel length.
7. The method of manufacturing a field effect transistor according to claim 6, wherein the step of wet etching both ends of the trench in a horizontal direction perpendicular to a channel length comprises:
and etching two ends of the groove in the STI region in the horizontal direction perpendicular to the length of the groove by using hydrofluoric acid soaking.
8. The method of manufacturing a field effect transistor according to claim 6, wherein the method of manufacturing further comprises:
oxidizing a gate oxide layer;
depositing a polysilicon gate;
or alternatively, the first and second heat exchangers may be,
the manufacturing method further comprises the steps of:
depositing a high-K layer;
and (5) depositing a metal gate.
CN202110134611.5A 2021-01-29 2021-01-29 Field effect transistor and method of manufacturing the same Active CN113327974B (en)

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KR940003075A (en) * 1992-07-01 1994-02-19 김주용 TFT (Thin Film Transistor) Manufacturing Method With Trench Surrounding Gate Structure
JPH0974199A (en) * 1995-01-12 1997-03-18 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacture
CN105244319A (en) * 2015-08-28 2016-01-13 西安电子科技大学 Inverted trapezoidal grid CMOS integrated device with strain SiGe channel and preparation method of integrated device
CN106298941A (en) * 2016-09-13 2017-01-04 上海华虹宏力半导体制造有限公司 Shield grid groove power device and manufacture method thereof
WO2018154402A1 (en) * 2017-02-22 2018-08-30 International Business Machines Corporation Fabrication of vertical field effect transistor device with modified vertical fin geometry
CN107871780A (en) * 2017-11-20 2018-04-03 中国科学院上海微系统与信息技术研究所 Field-effect transistor structure and preparation method thereof
CN209045563U (en) * 2018-11-09 2019-06-28 长鑫存储技术有限公司 A kind of buried gate structure
CN112071909A (en) * 2019-06-11 2020-12-11 芯恩（青岛）集成电路有限公司 Three-dimensional metal-oxide field effect transistor and preparation method thereof

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