CN113327895A - FinFET器件及其成型方法 - Google Patents

FinFET器件及其成型方法 Download PDF

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CN113327895A
CN113327895A CN202010130000.9A CN202010130000A CN113327895A CN 113327895 A CN113327895 A CN 113327895A CN 202010130000 A CN202010130000 A CN 202010130000A CN 113327895 A CN113327895 A CN 113327895A
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林昱佑
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Guangdong Hanqi Industrial Technology Research And Development Co ltd
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Abstract

本发明提出了一种FinFET器件及其成型方法。FinFET器件的成型方法包括以下步骤：步骤S1、采用半导体材料形成衬底(100)；步骤S2、通过蚀刻衬底(100)，形成多个鳍片(200)；其中，鳍片(200)具有多种形状；步骤S3、形成多个栅极结构(300)，使得所述鳍片(200)与多个栅极结构(300)中的一个栅极结构(300)对应，所述鳍片(200)插设在对应的栅极结构(300)中；其中，鳍片(200)的与栅极结构(300)接触的表面构成鳍片通道；不同形状的鳍片(200)的鳍片通道具有不同的宽度。本发明的FinFET器件及其成型方法设计新颖，实用性强。

Description

FinFET器件及其成型方法
技术领域
本发明涉及半导体生产技术领域，尤其涉及一种FinFET器件及其成型方法。
背景技术
一个典型的SRAM单元通常包括六个MOS管，具体包括上拉晶体管(PU)、用于读写位线(Bit Line)的控制开关(PG)、下拉晶体管(PD)；PU和PD构成CMOS反相器，如图1所示。SRAM单元的α(PU/PD)比值、β(PD/PG)比值和γ(PG/PU)比值的提高能够改善优化SRAM单元的读写性能。α(PU/PD)比值、β(PD/PG)比值和γ(PG/PU)比值和鳍片通道宽度有关，如图2-4所示。而在现有FinFET制程中，鳍片通道宽度是鳍片总数的倍数，这限制了FinFET的优化。因此，需要提出一种不受鳍片总数影响、用于调整鳍片通道宽度的技术。
发明内容
本发明针对以上技术问题，提供一种FinFET器件及其成型方法。
本发明所提出的技术方案如下：
本发明提出了一种FinFET器件的成型方法，包括以下步骤：
步骤S1、采用半导体材料形成衬底；
步骤S2、通过蚀刻衬底，形成多个鳍片；其中，鳍片具有多种形状；
步骤S3、形成多个栅极结构，使得所述鳍片与多个栅极结构中的一个栅极结构对应，所述鳍片插设在对应的栅极结构中；其中，鳍片的与栅极结构接触的表面构成鳍片通道；不同形状的鳍片的鳍片通道具有不同的宽度。
本发明上述的FinFET器件的成型方法中，在步骤S2中，利用硬掩模蚀刻衬底，并通过预先调整所选硬掩模上蚀刻图案的方式调整由蚀刻衬底所形成鳍片的形状，以使鳍片具有多种形状。
本发明上述的FinFET器件的成型方法中，在步骤S3中，形成多个栅极结构的步骤包括以下步骤：
在衬底上形成氧化物层，并使该氧化物层达到鳍片一定高度；然后在氧化物层上沉积形成栅极材料层，并使该栅极材料层覆盖鳍片；蚀刻栅极材料层，从而将栅极材料层分割为多个栅极结构。
本发明上述的FinFET器件的成型方法中，步骤S1还包括：在衬底上形成带有多个氮化硅层的硬掩模；
步骤S2包括：
通过蚀刻带有硬掩模的衬底，形成多个鳍片。
本发明上述的FinFET器件的成型方法中，氮化硅层包括芯棒以及包裹芯棒的包裹物；
在多个氮化硅层中，邻近两个氮化硅层之间的间距不完全一致。
本发明上述的FinFET器件的成型方法中，氮化硅层包括芯棒以及包裹芯棒的包裹物；
多个氮化硅层采用不完全一致的宽度。
本发明上述的FinFET器件的成型方法中，芯棒采用A-Si制成，包裹物采用SiN制成。
本发明还提出了一种FinFET器件，包括由半导体材料制成的衬底、由半导体材料在衬底上形成的多个鳍片、多个栅极结构；所述鳍片与多个栅极结构中的一个栅极结构对应，所述鳍片插设在对应的栅极结构中；鳍片的与栅极结构接触的表面构成鳍片通道；鳍片有多种形状，不同形状的鳍片的鳍片通道具有不同的宽度。
本发明上述的FinFET器件中，FinFET器件还包括形成于衬底上并达到鳍片一定高度的氧化物层。
本发明的FinFET器件及其成型方法通过采用不同形状的鳍片，使得鳍片通道宽度不受鳍片总数的影响，通过线性调整鳍片通道宽度替代离散调整鳍片总数的方式，实现α(PU/PD)比值、β(PD/PG)比值和γ(PG/PU)比值的调整。本发明的FinFET器件及其成型方法设计新颖，实用性强。
附图说明
图1示出了一种现有SRAM单元的结构示意图；
图2示出了图1所示的SRAM单元的FinFET器件的成型方法的第一步骤示意图；
图3示出了图1所示的SRAM单元的FinFET器件的成型方法的第二步骤示意图；
图4示出了图1所示的SRAM单元的FinFET器件的成型方法的第三步骤示意图；
图5示出了本发明优选实施例的FinFET器件的成型方法的第一步骤示意图；
图6示出了本发明优选实施例的FinFET器件的成型方法的第二步骤示意图；
图7示出了本发明优选实施例的FinFET器件的成型方法的第三步骤示意图；
图8示出了采用图7所示的FinFET器件的SRAM单元的一种结构示意图；
图9示出了一种现有带有氮化硅层的硬掩模的结构示意图；
图10示出了本发明带有氮化硅层的硬掩模的一种优选实施例的结构示意图；
图11示出了本发明带有氮化硅层的硬掩模的另一种优选实施例的结构示意图。
具体实施方式
为了便于本领域技术人员理解和实施本发明，下面将结合附图及具体实施例对本发明的技术目的、技术方案以及技术效果进行进一步详细的阐述。
如图5-图7所示，图5示出了本发明优选实施例的FinFET器件的成型方法的第一步骤示意图；图6示出了本发明优选实施例的FinFET器件的成型方法的第二步骤示意图；图7示出了本发明优选实施例的FinFET器件的成型方法的第三步骤示意图。具体地，FinFET器件的成型方法包括以下步骤：
步骤S1、采用半导体材料形成衬底100；
步骤S2、通过蚀刻衬底100，形成多个鳍片200；其中，鳍片200具有多种形状；
在本步骤中，利用硬掩模(HM，Hard Mask)500蚀刻衬底100，并通过预先调整所选硬掩模500上蚀刻图案的方式调整由蚀刻衬底100所形成鳍片200的形状，以使鳍片200具有多种形状；
硬掩模是一种通过CVD(Chemical Vapor Deposition，CVD)生成的无机薄膜材料。其主要成分通常有TiN、SiN、SiO2等。硬掩模主要运用于多重光刻工艺中，首先把多重光刻胶图像转移到硬掩模上，然后通过硬掩模将最终图形刻蚀转移到衬底上。
在本步骤中，还通过预先调整所选硬掩模500上蚀刻图案的方式，以此实现FinFET器件的目标值的保持、读取和写入边限。
步骤S3、形成多个栅极结构300，使得所述鳍片200与多个栅极结构300中的一个栅极结构300对应，所述鳍片200插设在对应的栅极结构300中；其中，鳍片200的与栅极结构300接触的表面构成鳍片通道；不同形状的鳍片200的鳍片通道具有不同的宽度。
在本步骤中，形成多个栅极结构300的步骤包括以下步骤：
在衬底100上形成氧化物层400，并使该氧化物层400达到鳍片200一定高度；然后在氧化物层400上沉积形成栅极材料层，并使该栅极材料层覆盖鳍片200；蚀刻栅极材料层，从而将栅极材料层分割为多个栅极结构300。
进一步地，步骤S1还包括：
在衬底100上形成带有多个氮化硅层600的硬掩模500；硬掩模500的厚度根据FinFET器件的保持、读取和写入边限的不同要求进行调整；通过氮化硅层600的覆盖，使得硬掩模500的被氮化硅层600覆盖的部分得到保护，不会被蚀刻。而多个氮化硅层600之间的间隙可供蚀刻硬掩模500之用。
步骤S2包括：
通过蚀刻带有硬掩模500的衬底100，形成多个鳍片200。
本实施例的FinFET器件的成型方法通过采用不同形状的鳍片200，使得鳍片通道宽度不受鳍片总数的影响，如图8所示，通过线性调整鳍片通道宽度替代离散调整鳍片总数的方式，实现α(PU/PD)比值、β(PD/PG)比值和γ(PG/PU)比值的调整。
进一步地，氮化硅层600包括芯棒610以及包裹芯棒610的包裹物620；芯棒610采用A-Si制成，包裹物620采用SiN制成。
如图9所示，图9示出了现有带有氮化硅层的硬掩模的结构示意图。在现有带有氮化硅层的硬掩模中，由于芯棒610的宽度和邻近两芯棒610之间的间距差不多，导致多个鳍片200具有一致的形状。
图10示出了本发明带有氮化硅层的硬掩模的一种优选实施例的结构示意图；图11示出了本发明带有氮化硅层的硬掩模的另一种优选实施例的结构示意图；
为了使得鳍片200具有多种形状，在本实施例中，在多个氮化硅层600中，邻近两个氮化硅层600之间的间距可以不完全一致，如图10所示，该特征通过调整其中几个芯棒610之间的间距实现；或者，多个氮化硅层600可采用不完全一致的宽度，如图11所示，该特征通过调整其中几个芯棒610的宽度实现。
如图7所示，本发明提出了一种FinFET器件，该FinFET器件包括由半导体材料制成的衬底100、由半导体材料在衬底100上形成的多个鳍片200、多个栅极结构300；所述鳍片200与多个栅极结构300中的一个栅极结构300对应，所述鳍片200插设在对应的栅极结构300中；鳍片200的与栅极结构300接触的表面构成鳍片通道；鳍片200有多种形状，不同形状的鳍片200的鳍片通道具有不同的宽度。
上述技术方案为基础技术方案，鳍片通道的宽度根据一定要求预先确定。同时，多个鳍片200的宽度也是预先确定的，以此实现FinFET器件的目标值的保持、读取和写入边限。
进一步地，FinFET器件还包括形成于衬底100上并达到鳍片200一定高度的氧化物层400。
对比如图4所示的现有技术和如图7所示的本实施例的FinFET器件的结构参数，可以看到本实施例的FinFET器件的α(PU/PD)比值、β(PD/PG)比值和γ(PG/PU)比值得到了提高。
项目 现有技术 本实施例
芯棒610间距 66nm 18～33nm,66nm
鳍片宽度 7nm 7nm～22nm
鳍片高度 42nm 42nm
鳍片通道宽度 42+7+42＝91nm 91nm～106nm
α/β/γ比例 1,2,3,4… 1,1.16,2,2.16,2.32,…
上面结合附图对本发明的实施例进行了描述，但是本发明并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本发明的启示下，在不脱离本发明宗旨和权利要求所保护的范围情况下，还可做出很多形式，这些均属于本发明的保护之内。

Claims (9)

1.一种FinFET器件的成型方法，其特征在于，包括以下步骤：
步骤S1、采用半导体材料形成衬底(100)；
步骤S2、通过蚀刻衬底(100)，形成多个鳍片(200)；其中，鳍片(200)具有多种形状；
步骤S3、形成多个栅极结构(300)，使得所述鳍片(200)与多个栅极结构(300)中的一个栅极结构(300)对应，所述鳍片(200)插设在对应的栅极结构(300)中；其中，鳍片(200)的与栅极结构(300)接触的表面构成鳍片通道；不同形状的鳍片(200)的鳍片通道具有不同的宽度。
2.根据权利要求1所述的FinFET器件的成型方法，其特征在于，在步骤S2中，利用硬掩模(500)蚀刻衬底(100)，并通过预先调整所选硬掩模(500)上蚀刻图案的方式调整由蚀刻衬底(100)所形成鳍片(200)的形状，以使鳍片(200)具有多种形状。
3.根据权利要求1所述的FinFET器件的成型方法，其特征在于，在步骤S3中，形成多个栅极结构(300)的步骤包括以下步骤：
在衬底(100)上形成氧化物层(400)，并使该氧化物层(400)达到鳍片(200)一定高度；然后在氧化物层(400)上沉积形成栅极材料层，并使该栅极材料层覆盖鳍片(200)；蚀刻栅极材料层，从而将栅极材料层分割为多个栅极结构(300)。
4.根据权利要求1所述的FinFET器件的成型方法，其特征在于，步骤S1还包括：在衬底(100)上形成带有多个氮化硅层(600)的硬掩模(500)；
步骤S2包括：
通过蚀刻带有硬掩模(500)的衬底(100)，形成多个鳍片(200)。
5.根据权利要求4所述的FinFET器件的成型方法，其特征在于，氮化硅层(600)包括芯棒(610)以及包裹芯棒(610)的包裹物(620)；
在多个氮化硅层(600)中，邻近两个氮化硅层(600)之间的间距不完全一致。
6.根据权利要求4所述的FinFET器件的成型方法，其特征在于，氮化硅层(600)包括芯棒(610)以及包裹芯棒(610)的包裹物(620)；
多个氮化硅层(600)采用不完全一致的宽度。
7.根据权利要求4所述的FinFET器件的成型方法，其特征在于，芯棒(610)采用A-Si制成，包裹物(620)采用SiN制成。
8.一种FinFET器件，其特征在于，包括由半导体材料制成的衬底(100)、由半导体材料在衬底(100)上形成的多个鳍片(200)、多个栅极结构(300)；所述鳍片(200)与多个栅极结构(300)中的一个栅极结构(300)对应，所述鳍片(200)插设在对应的栅极结构(300)中；鳍片(200)的与栅极结构(300)接触的表面构成鳍片通道；鳍片(200)有多种形状，不同形状的鳍片(200)的鳍片通道具有不同的宽度。
9.根据权利要求8所述的FinFET器件，其特征在于，FinFET器件还包括形成于衬底(100)上并达到鳍片(200)一定高度的氧化物层(400)。
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CN103227152A (zh) * 2012-01-26 2013-07-31 格罗方德半导体公司 利用侧壁图像转移技术形成sram装置的方法
US20140077303A1 (en) * 2012-09-14 2014-03-20 Samsung Electronics Co., Ltd. Fin transistor and semiconductor integrated circuit including the same
CN105097516A (zh) * 2014-04-25 2015-11-25 中芯国际集成电路制造(上海)有限公司 一种FinFET器件及其制造方法、电子装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103227152A (zh) * 2012-01-26 2013-07-31 格罗方德半导体公司 利用侧壁图像转移技术形成sram装置的方法
US20140077303A1 (en) * 2012-09-14 2014-03-20 Samsung Electronics Co., Ltd. Fin transistor and semiconductor integrated circuit including the same
CN105097516A (zh) * 2014-04-25 2015-11-25 中芯国际集成电路制造(上海)有限公司 一种FinFET器件及其制造方法、电子装置

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