CN113312023B - Photoelectric mixed multiplier - Google Patents
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- CN113312023B CN113312023B CN202110728989.8A CN202110728989A CN113312023B CN 113312023 B CN113312023 B CN 113312023B CN 202110728989 A CN202110728989 A CN 202110728989A CN 113312023 B CN113312023 B CN 113312023B
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Abstract
The invention provides a photoelectric hybrid multiplier, comprising: the partial product generating module performs product operation on the input multiplier and outputs a product operation result; the optical pulse generating module generates optical pulses; the column accumulation module receives the product operation result as a control signal, receives the optical pulse at the same time, determines whether to delay the optical pulse according to the control signal and outputs the optical pulse; the carry accumulation module receives the optical pulse output by the column accumulation module, determines whether to delay the optical pulse and determines delay time according to a carry signal, and outputs the optical pulse; the photoelectric conversion module receives the optical pulse output by the carry accumulation module and converts the optical pulse into a corresponding electric pulse signal; the carry generation module receives the electric pulse signals, judges the number of the time delays of the electric pulse signals according to the arrival time of the electric pulse signals to obtain the result of the accumulation operation, and generates carry signals. The invention adopts the optical device and the electric device to carry out multiplication, thereby improving the performance of the multiplier and reducing the power consumption.
Description
Technical Field
The invention relates to the technical field of photoelectricity, in particular to a photoelectric hybrid multiplier.
Background
The multiplier is used as an important operation unit in a CPU, a DSP and a neural network processor, is widely applied to operations such as frequency multiplication, multiply-accumulate, fast Fourier transform and the like, and has larger influence on the whole circuit by the calculation performance and the power consumption overhead. Therefore, a high performance, low power multiplier design is critical to these applications.
Operationally, the multiplication can be divided into two steps. The partial products are first calculated in bits and then accumulated. Most of the existing multiplier designs are based on electric devices, from the perspective of device cost, the number of the electric devices and the bit width of the multiplier form a square relation, from the perspective of performance, the frequency of the multiplier is limited by delay of propagation of a carry chain in partial product accumulation, and from the perspective of power consumption, burrs caused by different arrival times of signals in the electric multiplier and unnecessary overturning caused by an operand self-input mode bring extra power consumption cost.
In order to reduce device overhead, some efforts have been made to perform partial product accumulation in the time domain. The advantage of accumulating in the time domain is that only one link is needed to complete the accumulation operation of partial products no matter how the bit width of the multiplier is expanded, thereby reducing the number of used electric devices. However, accumulating in the time domain lengthens the critical path length of the multiplier because of the limited propagation speed of the signal in the electrical device and the linear relationship of the accumulation operation time in the time domain to the size of the operands.
Compared with an electric device, the optical device has the advantages of low delay, high bandwidth, low power consumption and the like. Some existing work uses devices such as Semiconductor Optical Amplifiers (SOAs), mach-zehnder interferometers (MZ I), etc. to implement two-bit or four-bit all-optical multipliers. However, as the number of bits increases, the number of optical devices used in the all-optical multiplier increases rapidly, and the delay and power consumption also increase, which seriously deteriorates the performance and power consumption benefits brought by the optical devices. In addition, the existing all-optical multipliers all require a large amount of photoelectric conversion to realize logic operation, which brings extra device overhead.
Disclosure of Invention
The invention aims to provide a photoelectric hybrid multiplier, which can use an electric device to perform partial product operation, use an optical device to perform accumulation calculation, and achieve the effect of reducing power consumption by combining the electric device and the optical device.
In order to achieve the above object, the present invention provides an optoelectronic hybrid multiplier, comprising:
the partial product generating module is used for carrying out product operation on the input multiplier and outputting a product operation result;
the optical pulse generating module is used for generating optical pulses;
the column accumulation module is used for receiving the multiplication result which serves as a control signal and receiving the optical pulse of the optical pulse generation module, determining whether to delay the optical pulse according to the control signal and outputting the optical pulse finally;
the carry accumulation module is used for receiving the optical pulse output by the column accumulation module, determining whether to delay the optical pulse according to a carry signal, determining delay time according to the carry signal and finally outputting the optical pulse;
the photoelectric conversion module is used for receiving the optical pulse output by the carry accumulation module and converting the optical pulse into a corresponding electric pulse signal; and
the carry generation module is used for receiving the electric pulse signals, judging the number of the delayed light pulses according to the arrival time of the electric pulse signals so as to obtain the result of accumulation operation and generating carry signals;
the optical pulse generation module, the column accumulation module and the carry accumulation module are optical devices, and the partial product generation module and the carry generation module are electric devices.
Optionally, in the optoelectronic hybrid multiplier, the partial product generation module includes an and gate device.
Optionally, in the optoelectronic hybrid multiplier, the optical pulse generation module includes:
a laser for emitting continuous light;
an optical switch for receiving the continuous light and generating the light pulse.
Optionally, in the optoelectronic hybrid multiplier, the column accumulation module includes a plurality of fixed optical delay devices connected in series, and the plurality of optical delay devices determine whether to delay the optical pulse in sequence according to the control signal.
Optionally, in the optoelectronic hybrid multiplier, the fixed delay device delays the optical pulse by a fixed time or not.
Optionally, in the optoelectronic hybrid multiplier, the column accumulation module includes 8 fixed optical delay devices connected in series, and the 8 fixed optical delay devices determine whether to delay the optical pulse in sequence according to the control signal.
Optionally, in the optoelectronic hybrid multiplier, the fixed optical delay device is controlled by an 8-bit control signal generated by the partial product generation module.
Optionally, in the optoelectronic hybrid multiplier, if the control signal is at a high level, the optical pulse input to the fixed optical delay unit is delayed for a fixed time, and if the control signal is at a low level, the optical pulse input to the fixed optical delay unit is not delayed.
Optionally, in the optoelectronic hybrid multiplier, the carry accumulation module includes a controllable optical delay device, the controllable optical delay device delays or does not delay the optical pulse, and the delay time can be controlled.
Optionally, in the photoelectric hybrid multiplier, the photoelectric conversion module receives the optical pulse output by the carry accumulation module, and converts the optical pulse into an electrical pulse signal corresponding to a bit by using a photoelectric conversion device and an amplification circuit to control the counter.
Optionally, in the optoelectronic hybrid multiplier, the carry generation module includes:
the counter starts counting while the optical pulse is generated, and stops counting after receiving the electric pulse signal, wherein the value in the counter is the result of accumulation operation;
the decoder is used for receiving the result of the accumulation operation and generating a bit product and a carry signal of the multiplication operation, wherein the bit product is used as the operation result of the multiplication operation, and the carry signal is sent to the carry accumulation module to be used as the carry signal of the next multiplication operation.
In the photoelectric hybrid multiplier provided by the invention, the electric device is adopted for carrying out partial product operation, and the optical device is adopted for carrying out accumulation operation. Compared with a multiplier which is all electric devices, the multiplier eliminates burrs caused by different arrival times of internal signals and unnecessary overturn caused by the input mode of an operand, and further reduces power consumption. Delay and power consumption are reduced relative to multipliers that are all optical devices. In short, the performance of the multiplier can be improved and the power consumption can be reduced by adopting the optical device and the electric device to mix for multiplication calculation.
Drawings
Fig. 1 is a schematic structural diagram of an opto-electric hybrid multiplier according to an embodiment of the present invention;
FIG. 2 is a computational model of an opto-electric hybrid multiplier according to an embodiment of the present invention;
FIG. 3 is a diagram of the calculation details of the opto-electronic hybrid multiplier of an embodiment of the present invention;
fig. 4 is a waveform diagram of the input and output of the opto-electronic hybrid multiplier according to an embodiment of the present invention;
in the figure: 100-partial product generation module, 200-optical pulse generation module, 210-laser, 220-optical switch, 300-column accumulation module, 310-fixed optical delay device, 400-carry accumulation module, 410-controllable optical delay device, 500-photoelectric conversion module, 510-optical receiver, 600-carry generation module, 610-counter and 620-decoder.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the following, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
With the continuous development of silicon photonics, the existing technology can integrate photonic devices and electronic devices on the same chip. The silicon optical process can simultaneously utilize the advantages of the electric device and the optical device, and has the characteristics of high bandwidth, low cost and the like. This makes it possible to design a high-performance, low-power-consumption opto-electronic hybrid multiplier using silicon photonics. On the basis, the photoelectric conversion can be reduced to one path by utilizing time domain calculation, and the expenditure of the photoelectric conversion can be effectively reduced.
Therefore, referring to fig. 1, the present invention provides an optoelectronic hybrid multiplier, which performs multiplication of multi-bit operands through partial product operations of multiple rounds, comprising:
a partial product generating module 100, configured to perform product operation on an input multiplier and output a product operation result;
an optical pulse generation module 200 for generating an optical pulse;
the column accumulation module 300 receives a multiplication result as a control signal, receives the optical pulse of the optical pulse generation module 200, determines whether to delay the optical pulse according to the control signal, and finally outputs the optical pulse;
a carry accumulation module 400, configured to receive the optical pulse output by the column accumulation module 300, determine whether to delay the optical pulse according to a carry signal of a previous round, determine a delay time according to the carry signal, and finally output the optical pulse;
the photoelectric conversion module 500 is configured to receive the optical pulse output by the carry accumulation module 400 and convert the optical pulse into a corresponding electrical pulse signal; and
a carry generation module 600, which receives the electrical pulse signals, determines the number of the delayed optical pulses according to the arrival time of the electrical pulse signals to obtain the result of the accumulation operation, and generates carry signals, wherein the carry signals are used as the reference of the delay time of the carry accumulation module 400 in the next round;
the optical pulse generating module 200, the column accumulation module 300, and the carry accumulation module 400 are optical devices, and the partial product generating module 100 and the carry generating module 600 are electrical devices.
Further, the partial product generation module 100 includes an and gate device. The partial product operation can be completed by a single AND gate, and the optical device overhead is saved compared with the partial product operation of an all-optical multiplier. The partial product generation module 100 inputs a one-bit multiplicand and multiplier per round and generates 8-bit control signals per round to control the 8 fixed optical delay devices 310 in the column accumulation module 300. The partial product generation module 100 inputs a one-bit multiplicand and multiplier per round and generates 8-bit control signals per round to control the 8 fixed optical delay devices 310 in the column accumulation module 300. The 8-bit control signal is the same as the partial product operation result in FIG. 3, because the control signal is fixed at 8 bits, if the partial product quantity in FIG. 3 is less than 8 bits, the control signal is filled with 0. The operation is divided into several rounds. In each round of operation, a bit partial product is generated by electric calculation, and the accumulation of the partial products in the operation is generated in a time domain by using an optical path. The least significant bit of the result of each round of operation is stored as the result output and the remaining significant bits are used as carry bits for the next round of accumulation.
Further, the optical pulse generation module 200 includes: a laser 210 for emitting continuous light; an optical switch 220 for receiving the continuous light and generating a light pulse. The optical switch 220 of the embodiment of the present invention generates the optical pulse signal with the same width as the high level of the round clock by the round clock control optical switch 220 and sends the optical pulse signal to the column accumulation module 300.
Further, the column accumulation module 300 includes a plurality of serially connected fixed optical delay devices 310, and the plurality of optical delay devices determine whether to delay the optical pulse according to the control signal in sequence, where the number of the fixed optical delay devices 310 is equal to the bit width of the multiplier and the multiplicand. The fixed delay device delays the light pulse for a fixed time or not. Specifically, in the embodiment of the present invention, 8 fixed optical delay devices are used as an example, and the 8 fixed optical delay devices 310 sequentially determine whether to delay the optical pulse according to the control signal. The fixed optical delay device 310 is controlled by an 8-bit control signal generated by the partial product generation module 100, and the control signal is a product result calculated by the partial product generation module 100. When the control signal is at a high level, the optical pulse input to the fixed optical delay is delayed for a fixed time, and when the control signal is at a low level, the optical pulse input to the fixed optical delay is not delayed. The column accumulation module 300 receives the optical pulse of the optical pulse generation module 200, and outputs the delayed optical pulse, thereby completing the carryless part of the accumulation operation in fig. 1. Because the accumulation of partial products in the electric multiplier is a critical path, the delay of the critical path can be reduced by adopting an optical device for accumulation. Compared with accumulation operation in a non-time domain, accumulation in the time domain can combine multiple paths of operation into one path, and the overhead of the optical device is effectively reduced. Compared with the accumulation operation based on the time domain of the electric device, the optical device has smaller time delay, and the time delay of the signal transmitted on the electric device is greatly reduced. The electric calculation is used for partial product operation and the time domain light calculation is used for accumulation operation. Compared with an electric multiplier, the method eliminates burrs caused by different arrival times of internal signals and unnecessary overturn caused by the input mode of the operation number, and further reduces power consumption.
Further, the carry accumulation module 400 includes a controllable optical delay device 410, and the controllable optical delay device 410 delays or does not delay the optical pulse, and the delay time can be controlled. The delay device has a function of delaying one to seven fixed time units or not, is controlled by a carry signal generated in the previous round by the carry generation module 600, and the delay time corresponds to the magnitude of the carry signal one to one. The carry part of the accumulate operation in fig. 3 is completed. The carry accumulation module 400 includes a controllable optical delay device 410, which has a function of delaying one to seven fixed time units or no delay, and is controlled by the carry signal generated by the carry generation module 600 in the previous round, and the delay time corresponds to the magnitude of the carry signal.
Further, the photoelectric conversion module 500 receives the optical pulse output by the carry accumulation module 400, and uses the photoelectric conversion device and the amplifying circuit to convert the optical pulse into an electrical pulse signal corresponding to the bit to control the counter 610.
Further, the carry generation module 600 includes: the counter 610 starts counting while the optical pulse is generated, and stops counting after receiving the electric pulse signal, and the value in the counter 610 is the result of the accumulation operation; decoder 620 is configured to receive the result of the accumulation operation and generate a bit product of the multiplication and a carry signal, where the bit product is the result of the multiplication and the carry signal is sent to bit accumulation module 400 as the carry signal of the next multiplication. Specifically, the counter 610 starts counting while the optical pulse is generated, and stops counting after receiving the electrical pulse signal sent by the optical receiver 510, where the value in the counter 610 is the result of the accumulation operation. The counter 610 transmits the result of this time to the decoder 620, and the decoder 620 generates a bit product of this round and a carry signal according to the value of the counter 610, the bit product is stored as the operation result of this round, and the carry signal is transmitted to the carry accumulation module 400 to realize carry accumulation of the next round.
Referring to fig. 2 and 3, although only 8-bit multipliers are used as an illustration, other embodiments of the present invention can be extended to any bit width, and are not limited to 8 bits. Fig. 2 shows a calculation model of the opto-electric hybrid multiplier according to the embodiment of the present invention in rounds, according to which 16 rounds are required in total for calculating 8-bit multiplication. Each round requires the computation of several partial products and their accumulated sum with the carry of the previous round, while generating a new carry. FIG. 3 shows in detail the splitting of each round of computation over electrical and time domain optical computations, and the corresponding store and carry operations. The partial product operation is realized through electrical calculation, the first column in fig. 2 represents the number of rounds, the second column is the result of the partial product operation, and it can be seen that round 1 generates a0b0, round 2 generates a1b0 and a0b1, round 3 generates a2b0, a1b1 and a0b2, round 8 generates a7b0, a6b1, a5b2, a4b3, a3b4, a2b5, a1b6 and a0b7, and the generated partial products correspond to the items of each column in the calculation model in fig. 1. After the partial product operations are completed, their accumulation is performed by time domain optical computation, column 3 is the value of the accumulation operation, round 1 does not need accumulation, round 2 computes a1b0+ a0b1, round 3 computes a2b0+ a1b1+ a0b2+ carry, carry is the carry information of the previous round, i.e., the carry information of the second round (from round #2), and round 8 computes a7b0+ a6b1+ a5b2+ a4b3+ a3b4+ a2b5+ a1b6+ a0b7+ carry (from # 7). The values of the partial product operation and the accumulation operation in the remaining rounds, such as the 4 th round and the 15 th round, can be known by referring to the diagram of fig. 2, and are not described herein again. After the partial product accumulation operation is completed, the least significant bits of the result are saved and a carry is calculated for the next round of accumulation. As in column 4, the result of the accumulate operation is stored in the lowest order bits while the carry for the next round is computed.
For a specific multiplication of two 8-bit binary numbers, the input and output signal waveforms are shown in fig. 4. The multiplication of two 8-bit binary numbers can be divided into four stages, respectively: reset phase, rounds 0 to 7, 8 to 15 and 16. In the reset phase, the reset signal is active low, the multiplicand and the least significant bit of the multiplier are ready at the corresponding input port, the count clock is running all the time but the round clock is not started, and a bit product output is invalid data. From round 0 to round 7, each round generates a round clock that is used to generate the optical pulses to complete the accumulation operation in the time domain. In addition, during this phase, a one-bit multiplicand and a one-bit multiplier are updated synchronously each round, in order from low to high. Starting from the second round, a valid one-bit product is output, the least significant bit of the 16-bit product is output and the order of output is from low to high. From round 8 to round 15, as in the above stage, one round clock is generated for each round to complete the accumulation operation in the time domain. But at this stage the one-bit multiplicand and one-bit multiplier inputs are not valid because all 8 bits have been completed at the previous stage inputs. At this point, a valid one-bit product is still output for each round, and the order of output is from low to high. In the fourth stage, the enable signal is pulled low, the last valid bit product is output, and the whole multiplication operation is completed. Referring to fig. 1, a reset signal is connected to the partial product generation module 100 and the decoder 620, an enable signal is connected to the counter 610, a count clock is connected to the counter 610, a round clock is connected to the optical switch 220, the counter 610 and the decoder 620, and a multiplier and a multiplicand refer to operands to be multiplied by the partial product generation module 100.
In summary, in the optoelectronic hybrid multiplier provided in the embodiment of the present invention, the electrical device is used to perform the partial product operation, and the optical device is used to perform the accumulation operation. Compared with a multiplier which is all electric devices, the multiplier eliminates burrs caused by different arrival times of internal signals and unnecessary overturn caused by the input mode of an operand, and further reduces power consumption. Delay and power consumption are reduced relative to multipliers that are all optical devices. In short, the performance of the multiplier can be improved and the power consumption can be reduced by adopting the optical device and the electric device to mix for multiplication calculation.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (11)
1. An opto-electric hybrid multiplier, comprising:
the partial product generating module is used for carrying out product operation on the input multiplier and outputting a product operation result;
the optical pulse generating module is used for generating optical pulses;
the column accumulation module is used for receiving the multiplication result which serves as a control signal and receiving the optical pulse of the optical pulse generation module, determining whether to delay the optical pulse according to the control signal and outputting the optical pulse finally;
the carry accumulation module is used for receiving the optical pulse output by the column accumulation module, determining whether to delay the optical pulse according to a carry signal, determining delay time according to the carry signal and finally outputting the optical pulse;
the photoelectric conversion module is used for receiving the optical pulse output by the carry accumulation module and converting the optical pulse into a corresponding electric pulse signal; and
the carry generation module is used for receiving the electric pulse signals, judging the number of the delayed light pulses according to the arrival time of the electric pulse signals so as to obtain the result of accumulation operation and generating carry signals;
the optical pulse generation module, the column accumulation module and the carry accumulation module are optical devices, and the partial product generation module and the carry generation module are electric devices.
2. The optoelectronic hybrid multiplier of claim 1, wherein said partial product generation block comprises an and gate arrangement.
3. The optoelectronic hybrid multiplier of claim 1, wherein said optical pulse generating module comprises:
a laser for emitting continuous light;
an optical switch for receiving the continuous light and generating the light pulse.
4. The optoelectronic hybrid multiplier of claim 1, wherein said column accumulation module comprises a plurality of serially connected fixed optical delay devices, said plurality of optical delay devices determining whether to delay said optical pulses in turn based on said control signal.
5. The optoelectronic hybrid multiplier of claim 4, wherein said fixed optical delay device delays said optical pulse by a fixed time or no delay.
6. The optoelectronic hybrid multiplier of claim 4, wherein said column accumulation module comprises 8 serially connected fixed optical delay devices, 8 of said fixed optical delay devices determining whether to delay said optical pulse in turn according to said control signal.
7. The optoelectronic hybrid multiplier of claim 6, wherein said fixed optical delay device is controlled by an 8-bit control signal generated by said partial product generation module.
8. The opto-electric hybrid multiplier of claim 7, wherein when the control signal is high, the optical pulse input to the fixed optical delay is delayed for a fixed time, and when the control signal is low, the optical pulse input to the fixed optical delay is not delayed.
9. The optoelectronic hybrid multiplier of claim 1, wherein said carry-accumulation module comprises a controllable optical delay device, said controllable optical delay device being capable of delaying or not delaying said optical pulses, and wherein the delay time is controllable.
10. The optoelectronic hybrid multiplier of claim 1, wherein the optoelectronic conversion module receives the optical pulse output from the carry accumulation module and converts it into an electrical pulse signal using an optoelectronic conversion device and an amplification circuit.
11. The optoelectronic hybrid multiplier of claim 10, wherein said carry generation module comprises:
the counter starts counting while the optical pulse is generated, stops counting after receiving the electric pulse signal, and the value in the counter is the result of accumulation operation;
the decoder is used for receiving the result of the accumulation operation and generating a bit product and a carry signal of the multiplication operation, wherein the bit product is used as the operation result of the multiplication operation, and the carry signal is sent to the carry accumulation module to be used as the carry signal of the next multiplication operation.
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