CN113308683B - Pe-cvd设备及方法 - Google Patents

Pe-cvd设备及方法 Download PDF

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CN113308683B
CN113308683B CN202110017476.6A CN202110017476A CN113308683B CN 113308683 B CN113308683 B CN 113308683B CN 202110017476 A CN202110017476 A CN 202110017476A CN 113308683 B CN113308683 B CN 113308683B
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S·伯吉斯
K·克鲁克
D·阿查德
W·罗伊尔
E·A·莫里森
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Abstract

本申请的实施例涉及一种PE‑CVD设备和方法。根据本发明,提供一种电容耦合的等离子体增强化学气相沉积PE‑CVD设备,其包括:腔室;第一电极,其包括位于所述腔室中的衬底支架;第二电极,其包括位于所述腔室中的进气口结构,所述进气口结构包括边缘区域、相对于所述边缘区域向下悬垂的中心区域,及用于将PE‑CVD前驱气体混合物引入到所述腔室的一或多个前驱气体入口,所述边缘区域及所述中心区域两者构成所述第二电极的一部分,其中所述前驱气体入口安置于所述边缘区域中,且所述中心区域与所述衬底支架间隔开以限定等离子体暗区通道;及RF电源,其连接到所述进气口结构以向其供应RF功率。

Description

PE-CVD设备及方法
技术领域
本发明涉及一种电容耦合的等离子体增强化学气相沉积(PE-CVD)设备。本发明还涉及一种通过电容耦合的PE-CVD将材料沉积在衬底的外围区域上的方法。
背景技术
蚀刻是半导体装置制造中的众所周知的工艺,其中除去半导体衬底的选定部分,作为沉积其它层的前驱或用于由蚀刻本身产生的改变的几何形状。通常,半导体衬底是晶片。在执行晶片蚀刻工艺时,必须屏蔽预期保持未蚀刻的晶片表面。需要保护的晶片表面通常包含围绕晶片边缘的晶片的外围区域。常规上,这可通过在要保护的表面上施加光致抗蚀剂聚合物来完成。然而,光致抗蚀剂中的化学物质可能会干扰蚀刻工艺,尤其是在执行体硅蚀刻时。因此,需要一种保护晶片的外围区域的替代方法,所述方法不需要使用光致抗蚀剂并且不会以任何不希望的程度干扰蚀刻工艺。然而,任何此种替代方案应便于实施及优选地与现有的半导体处理技术兼容。而且,任何替代方法都应是可充分控制的,使得在晶片的所需外围区域中,而不是在晶片中预期保持暴露和不受保护的区域中提供保护。
发明内容
在本发明的实施例中的至少一些中,本发明涉及上文所公开的问题、期望及需求中的一或多个。此外,本发明人已经意识到其发明比这更普遍地适用。具体来说,本发明可提供一系列材料在一系列衬底的外围区域上的位置特定的沉积。
根据本发明的第一方面,提供一种电容耦合的等离子体增强化学气相沉积(PE-CVD)设备,其包括:
腔室;
第一电极,其包括位于腔室中的衬底支架;
第二电极,其包括位于腔室中的进气口结构,所述进气口结构包括边缘区域、相对于边缘区域向下悬垂的中心区域,及用于将PE-CVD前驱气体混合物引入到腔室的一或多个前驱气体入口,边缘区域及中心区域两者构成第二电极的一部分,其中前驱气体入口安置于边缘区域中,及中心区域与衬底支架间隔开以限定等离子体暗区通道;及
RF电源,其连接到进气口结构以向其供应RF功率。
根据本发明的第二方面,提供一种通过电容耦合的等离子体增强化学气相沉积(PE-CVD)将材料沉积在衬底的外围区域上的方法,所述方法包括以下步骤:
提供一种设备,所述设备包括:腔室;第一电极,其包括位于腔室中的衬底支架;第二电极,其包括位于腔室中的进气口结构,所述进气口结构包括边缘区域、相对于边缘区域向下悬垂的中心区域,以及用于将PE-CVD前驱气体混合物引入到腔室的一或多个前驱气体入口,边缘区域及中心区域两者构成第二电极的一部分,其中前驱气体入口安置于边缘区域中,及中心区域与衬底支架间隔开以限定等离子体暗区通道;及RF电源,其连接到进气口结构以向其供应RF功率;
将衬底定位在衬底支架上;及
执行电容耦合的PE-CVD工艺,其中将RF功率提供给进气口结构,以生成在等离子体暗区通道中具有暗区的等离子体,从而使材料仅沉积在衬底的外围区域上。
以此方式,可通过PE-CVD以位置特定的方式将材料沉积在衬底的外周处。沉积的位置及其它沉积特性,例如沉积厚度及厚度分布可通过控制腔室中的元件(例如,进气口结构)的结构特性,及还通过控制工艺条件来控制。
衬底支架可包括边缘区域及用于接收衬底的中心区域,所述中心区域相对于边缘区域升高,其中进气口结构的中心区域与衬底支架的中心区域间隔开以限定等离子体暗区通道。衬底可比衬底支架的中心区域宽,及具有前表面、后表面及边缘表面,所述边缘表面连接前表面及后表面,使得当衬底位于衬底支架上时,前表面面向进气口结构,后表面背对进气口结构,及衬底的外围区域延伸超出衬底支架的中心区域,由此将外围区域的后表面暴露于等离子体。随后,执行电容耦合的PE-CVD工艺的步骤可使材料沉积在衬底的外围区域中的后表面上。执行电容耦合的PE-CVD工艺的步骤还可使材料沉积在衬底的边缘区域及外围区域中的前表面上。
进气口结构的中心区域通常可与衬底支架的中心区域相对。
进气口结构的中心区域与衬底支架之间的间隔可被视为等离子体暗区通道的深度。应注意,我们关于进气口结构的中心区域与衬底支架之间的间隔定义等离子体暗区通道。应认识到,在处理期间,衬底在衬底支架上的适当位置,及因此等离子体暗区可形成的有效间隙是等离子体暗区深度减去衬底的厚度。进气口结构的中心区域与衬底支架之间的间隔可在2mm至20mm的范围内。此间隔可尤其适用于标准SiO2工艺条件(RF功率、压力、气流等)。
一般来说,第一及第二电极各自由导电材料形成。进气口结构及衬底支架中的至少一个可由金属材料,任选地铝形成。使用的铝可具有阳极化表面,例如Al2O3
进气口结构的中心区域及边缘区域均可由金属材料形成且彼此电接触。
进气口结构的中心区域可相对于进气口结构的边缘区域向下悬垂至少5mm的深度。此深度可在5mm至45mm的范围内。此深度可在5mm至25mm的范围内。
衬底支架的中心区域可相对于衬底支架的边缘区域升高在1mm至25mm的范围内的高度。衬底支架的中心区域可相对于衬底支架的边缘区域升高在1mm至10mm的范围内的高度。
通过电容耦合的PE-CVD工艺沉积的材料可为在后续蚀刻工艺期间保护衬底的保护材料。以此方式,保护轴环可围绕衬底的边缘形成。保护材料可为例如氧化物介电材料的介电材料,或半导体材料。保护材料可为氧化硅。我们使用术语“氧化硅”,因为这已被广泛认可并在半导体行业中广泛使用。然而,技术人员将理解,沉积的氧化硅膜的化学计量为SiO2或接近SiO2。任何合适的PE-CVD前驱气体混合物可用于沉积氧化硅。举例来说,PE-CVD前驱气体混合物可包括SiH4或原硅酸四乙酯(TEOS)。PE-CVD前驱气体混合物可包括SiH4及N2O、SiH4及O2,或TEOS及O2及/或O3。或者,保护材料可为SiN、SiON、SiOC或SiC。
进气口结构的中心区域可具有特性水平维度D1。衬底可具有对应的特性水平维度D。比率D1/D可在1.1至0.9,优选地1.05至0.95的范围内。特性水平维度可为直径,例如其中衬底是圆形晶片及进气口结构的中心区域具有圆形下表面。
衬底支架的中心区域可具有特性水平维度D2。衬底可具有对应的特性水平维度D。比率D2/D可在0.7至0.98,优选地0.7至0.95的范围内。特性水平维度可为直径,例如其中衬底是圆形晶片及进气口结构的中心区域具有圆形下表面。
进气口结构的中心区域可为由进气口结构的边缘区域环绕的台阶式突起。当衬底为圆形,例如圆形半导体晶片时,进气口结构的中心区域可包括圆柱形突起。在这些实施例中,进气口结构的边缘区域可为环形结构。或者,进气口结构的中心区域可具有不垂直于进气口结构的边缘区域的一或多个侧面,例如,倾斜或斜切侧面。
可配置设备,使得进气口结构的中心区域与衬底支架之间的间隔可在设备中执行的电容耦合的PE-CVD工艺过程期间变化。因此,进气口结构的中心区域与衬底支架之间的间隔可在电容耦合的PE-CVD工艺过程期间变化。设备可包括用于升高及降低衬底支架的布置,使得进气口结构的中心区域与衬底支架之间的间隔可在设备中执行的电容耦合的PE-CVD工艺过程期间变化。
衬底可为晶片。
衬底可为半导体衬底,例如硅晶片。
尽管上文已经描述了本发明,但是本发明将扩展到在上文或下文描述中提出的任何发明性组合。举例来说,相对于本发明的一个方面描述的特征相对于本发明的另一个方面公开。尽管本文中参考附图详细地描述本发明的说明性实施例,但应理解本发明不限于这些精确实施例。此外,预期单独描述或作为实施例的一部分描述的特定特征可与其它单独描述的特征或其它实施例的部分组合,即使其它特征及实施例没有提及特定特征。因此,本发明扩展到尚未描述的此类特定组合。
附图说明
现在将仅借助于实例参考附图描述本发明,其中:
图1是现有技术PE-CVD设备的喷淋头及衬底支架的侧视图;
图2是本发明的PE-CVD设备的剖视侧视图;
图3是图2的PE-CVD设备的进气口结构及衬底支架的半侧视示意图;
图4是在使用图2及3中所示的设备沉积材料之后通过晶片衬底的垂直截面;
图5展示随用于进气口结构的中心区域的不同配置及尺寸的晶片直径而变的前表面沉积厚度轮廓;
图6展示随用于进气口结构的中心区域的不同配置及尺寸的晶片直径而变的后表面沉积厚度轮廓;及
图7展示随用于将氧化硅沉积在200mm直径硅晶片上的晶片直径而变的(a)前表面及(b)后表面沉积厚度轮廓。
具体实施方式
图1展示常规的现有技术电容耦合的PE-CVD反应器的部分,其包括“喷淋头”类型10的进气口结构及衬底支架12。图1中所示的常规喷淋头结构采用包括平坦下表面的圆盘形式。喷淋头10具有分布在下表面的大部分上的多个前驱气体入口14,以便将相对均质的前驱气体的空间分布提供到腔室中。衬底支架12也具有常规设计,具有例如晶片16的衬底定位在其上的平坦上表面。晶片的宽度总是小于衬底支架的宽度。进气口结构10及衬底支架12用作电容耦合的等离子体生成反应器中的平行板电极,以产生等离子体18。等离子体18辅助将所需材料沉积在晶片16的前表面上的PE-CVD工艺。应注意,此现有技术配置引起材料沉积在晶片16的整个前表面上。尽管沉积可能发生在晶片的边缘上,但是沉积无法发生在晶片的后表面上,因为后表面与衬底支架的上表面接触及没有暴露于等离子体及工艺气体。
本发明提供一种用于PE-CVD设备的配置,其实现到衬底上的位置特定的沉积。具体来说,本发明实现沉积在衬底的所需外围区域上,而不会在衬底的更中心区域上发生沉积。这可使用与图1中所示的常规设计不同类型的进气口结构实现。更具体来说,可使用包括边缘区域及中心区域的进气口结构。前驱气体入口安置于边缘区域中。在前驱气体入口面向上的定向中,中心区域相对于边缘区域升高。当进气口结构位于PE-CVD设备的顶部附近时,前驱气体入口朝向衬底支架面向下及中心区域相对于边缘区域向下悬垂。
图2及3展示一般在20处描绘的本发明的PE-CVD设备,其包括具有位于其中的衬底支架24的腔室22。衬底支架24可为半导体晶片26可定位在其上的压板。衬底支架可进一步包括压板支架及内部加热/冷却系统,如本领域中众所周知。压板可在用于接收晶片的降低位置与用于通过PE-CVD处理晶片的升高的使用中位置之间移动,及/或修改晶片表面与第二电极之间的间隙。设备20进一步包括位于腔室22的顶部处的进气口结构28。通过管道30将所需的前驱气体或前驱气态混合物从气体供应系统(未展示)引入到进气口结构28中。进气口结构28包括安置于进气口结构28的边缘区域34中的多个前驱气体入口32,且因此从管道30引入的气体随后通过多个前驱气体入口32进入腔室22的内部。通常,将包括一或多种工艺气体的前驱气态混合物任选地结合一或多种载气供应到腔室22。进气口结构28进一步包括相对于边缘区域34向下悬垂的中心区域36。
衬底支架24充当第一电极且进气口结构28充当电容耦合的等离子体生产装置的第二电极。衬底支架及进气口结构可由铝或另一合适的导电材料形成。衬底支架24保持处于接地。进气口结构28是借助于其经由RF匹配网络40与RF电源38的连接而受驱动的电极。以此方式,在腔室22中产生等离子体42,所述等离子体引起通过所需PE-CVD工艺将材料沉积在半导体晶片26上。经由排气口44将气体从腔室22清除。可使用可连接到进气口结构或衬底支架的次级RF电源来提供混合频率RF。进气口结构28的中心区域36与衬底支架24间隔开以限定本文中称为等离子体暗区通道的通道。中心区域36在边缘区域34的下表面下方向下悬垂的深度在图3中示为x1,且中心区域36的宽度示为d1。产生具有相关联的等离子体暗区通道深度的所需等离子体暗区通道46。这通过适当地选择x1及针对所采用的工艺条件将衬底支架24与进气口结构28间隔开而实现沿着通道46的至少一部分形成等离子体暗区。应注意,在处理期间,可不沿着等离子体暗区通道46的整个宽度形成等离子体暗区。替代地,等离子体可延伸到等离子体暗区通道46中。如下文更详细地解释,可改变各种结构及工艺参数,以控制等离子体延伸到等离子体暗区通道的程度,进而控制材料朝向衬底的中心沉积的程度。然而,在等离子体暗区通道中存在等离子体暗区具有以下结果:材料沉积在衬底的外围区域上,而不沉积在衬底的更中心区域上。
在图2及3中所示的实施例中,衬底支架24也具有常规设计。更具体来说,衬底支架24包括边缘区域48及用于接收衬底26的中心区域50。衬底支架24的中心区域50具有宽度d2且相对于边缘区域48升高距离x2。如果衬底26是具有环形横截面的晶片,则衬底支架24的中心区域50通常是环形横截面的阶梯式部分,且d2是直径。将d2选择为小于衬底26的对应宽度,使得当衬底26位于衬底支架24上时,衬底26延伸出中心区域50以悬垂在边缘区域48上。以此方式,衬底26的后表面的外围区域未受衬底支架24保护。相反,衬底26的后表面的外围区域暴露于等离子体42或至少暴露于活性前驱物质的扩散,这使得材料能够沉积在上面。
图4展示在使用图2及3中所示的设备沉积材料142之后晶片衬底140的垂直截面。在晶片衬底140的外围区域中,材料142沉积在前表面140b及后表面140c上,及连接前表面140a及后表面140b的边缘表面140d上。沉积材料142在衬底140的外周处形成连续轴环结构,所述衬底在垂直截面中具有(如图4中所示)细管形状。应了解,可沉积材料142以形成保护结构来屏蔽衬底的边缘区域。因此,沉积材料可为执行有用保护功能以在其最终终端使用期间保护衬底,或在后续处理或其它制造步骤期间保护衬底的材料。举例来说,当衬底是半导体衬底时,材料可为在后续蚀刻步骤期间保护衬底的边缘区域的耐蚀刻材料。合适的耐蚀刻材料的实例是氧化硅。可使用可通过PE-CVD沉积的其它保护材料,例如SiN、SiON、SiOC或SiC。然而,本发明不限于执行保护功能的材料的沉积。原则上,可通过PE-CVD沉积的任何材料可根据本发明以位置特定的方式沉积在衬底的外周处。
在替代实施例中,代替图2及3中所示的非常规衬底支架,可使用常规的衬底支架。常规的衬底支架具有用于接收衬底的平坦上表面。衬底小于衬底支架的上表面及完全位于上表面的界限内。换句话说,衬底相对于衬底支架的定位一般如在图1的下部部分中所示。因此,衬底的后表面不暴露于等离子体及材料不沉积在其上。替代地,材料沉积在在衬底的外围区域中的前表面上。在沉积在例如圆形半导体晶片的圆形衬底上的情况下,这产生一般环形的前侧沉积图案。材料还可沉积在衬底的边缘上。
可改变衬底支架及进气口结构的结构特性,以便控制材料在衬底上的位置特定的沉积。在一系列实验中,氧化硅使用图2及3中所示的设备沉积在200mm直径硅晶片上。在这些实验中,改变尺寸x1、d1、x2及d2,以改变沉积的氧化硅层的厚度及沉积朝向晶片的中心径向向内延伸的程度两者。使用N2O中2.5%SiH4的前驱气体混合物沉积氧化硅,其中总气体流量为820sccm。晶片温度为150℃及腔室压力为350mTorr。360W的13.56MHz RF功率施加到进气口结构。边缘区域的下表面与晶片衬底的前表面之间的间隙为26mm,使得当x1是15mm时,等离子体暗区通道深度是11mm,当x1是10mm时,等离子体暗区通道深度是16mm,及当x1是5mm时,等离子体暗区通道深度是21mm。结果在图5和6中展示。图5展示在用于进气口结构的中心区域的不同配置及尺寸的晶片的前表面上的沉积轮廓。展示随晶片直径而变的沉积厚度。在晶片的中心区域中观察到的噪声由于所使用的计量产生。由于手动地放置晶片,在x轴中观察到一些偏移。
结果展示通过减小进气口结构的中心区域与晶片的前表面之间的空间,可减小沉积层的厚度及可减小沉积从晶片边缘径向向内延伸的程度。还可通过改变进气口结构的中心区域的直径来调整沉积的径向向内程度。已经显示200nm至3000nm的沉积厚度是可能的,其中不同的沉积轮廓随晶片直径而变。
图6展示在用于衬底支架的中心区域的不同配置及尺寸的晶片的后表面上的沉积轮廓。展示随晶片直径而变的沉积厚度。在晶片的中心区域中观察到的噪声由于所使用的计量产生。图6展示沉积厚度及沉积从晶片边缘径向向内延伸的程度两者,可通过调适衬底支架的中心区域的几何形状来改变耗散速率。还应注意,沿着晶片,d2=190mm迹线在-95mm和95mm处的沉积厚度会急剧下降。这是由于台阶式中心部分的物理屏障阻止了超出这些点的沉积。
如上所述,通过使用图2及3的设备,可围绕晶片边缘的边缘沉积保护轴环。图7展示在晶片的(a)前表面及(b)后表面上的氧化硅沉积轮廓,指示实现图4中示意性地展示的种类的保护结构。
不希望受任何具体的理论或猜测所束缚,据相信,可在等离子体暗区通道中产生等离子体暗区。在此区域中不存在等离子体的情况下,除了由于激活前驱物质扩散到等离子体暗区中而可能发生的沉积之外,材料不会沉积到位于等离子体暗区下方的衬底的中心区域上。同样,不希望受任何具体的理论或猜测所束缚,提出可通过其产生等离子体暗区的两个机构。第一,向下悬垂的中心区域充当突起,所述突起减小电容耦合的等离子体系统中的第一及第二电极之间的间隔,使得放电阻抗增加到等离子体暗区通道中不可接近的水平。换句话说,引发等离子体至第一近似值的击穿电压取决于电容耦合的等离子体反应器中阳极与阴极之间的P(压力)及D(距离)。本发明在等离子体暗区通道中提供了低D,并且可选择所使用的条件,使得乘积PxD导致引发等离子体所需的过大的击穿电压。从物理上讲,这可能与距离D远小于等离子体暗区通道区域中气体分子的平均自由路径相关联。第二,在进气口结构的中心区域中没有进气口有助于防止前驱气体传递到等离子体暗区通道(进气口结构的中心区域还可充当物理屏障,所述物理屏障阻止从边缘中的进气口进入腔室的前驱气体进入等离子体暗区通道,尤其当使用从腔室的外围区域排出气体的周向泵送系统时)。
本发明可通过不同方式实施,并且技术人员将理解,上述实施例的各种修改及变型是可能的。举例来说,可使用具有不同地配置的中心区域的进气口结构,例如具有一或多个侧面的中心区域,这些侧面不垂直于边缘区域,而是倾斜,斜切或以其它方式不垂直于进气口结构的底座。

Claims (22)

1.一种电容耦合的等离子体增强化学气相沉积PE-CVD设备,其包括:
腔室;
第一电极,其包括位于所述腔室中的衬底支架;
第二电极,其包括位于所述腔室中的进气口结构,所述进气口结构包括边缘区域、相对于所述边缘区域向下突出的中心区域,及用于将PE-CVD前驱气体混合物引入到所述腔室的一或多个前驱气体入口,所述边缘区域及所述中心区域两者构成所述第二电极的一部分,其中所述前驱气体入口安置于所述边缘区域中,且所述中心区域与所述衬底支架间隔开以限定等离子体暗区通道;及
RF电源,其连接到所述进气口结构以向其供应RF功率。
2.根据权利要求1所述的设备,其中所述衬底支架包括边缘区域及用于接收衬底的中心区域,所述中心区域相对于所述边缘区域升高,其中所述进气口结构的所述中心区域与所述衬底支架的所述中心区域间隔开以限定所述等离子体暗区通道。
3.根据权利要求2所述的设备,其中所述进气口结构的所述中心区域与所述衬底支架的所述中心区域相对。
4.根据任一前述权利要求所述的设备,其中所述进气口结构的所述中心区域与所述衬底支架之间的间隔在2mm至20mm的范围内。
5.根据权利要求1至3中任一项所述的设备,其中所述进气口结构及所述衬底支架中的至少一个由金属材料。
6.根据权利要求5所述的设备,其中所述进气口结构及所述衬底支架中的至少一个由铝形成。
7.根据权利要求5所述的设备,其中所述进气口结构的所述中心区域及所述边缘区域都由金属材料形成且彼此电接触。
8.根据权利要求1至3中任一项所述的设备,其中所述进气口结构的所述中心区域相对于所述进气口结构的所述边缘区域向下突出在5mm至45mm的范围内的深度。
9.根据权利要求1至3中任一项所述的设备,其经配置使得所述进气口结构的所述中心区域与所述衬底支架之间的所述间隔可在所述设备中执行的电容耦合的PE-CVD工艺过程期间变化。
10.一种通过电容耦合的等离子体增强化学气相沉积PE-CVD将材料沉积在衬底的外围区域上的方法,其包括以下步骤:
提供设备,所述设备包括:腔室;第一电极,其包括位于所述腔室中的衬底支架;第二电极,其包括位于所述腔室中的进气口结构,所述进气口结构包括边缘区域、相对于所述边缘区域向下突出的中心区域,以及用于将PE-CVD前驱气体混合物引入到所述腔室的一或多个前驱气体入口,所述边缘区域及所述中心区域两者构成所述第二电极的一部分,其中所述前驱气体入口安置于所述边缘区域中,且所述中心区域与所述衬底支架间隔开以限定等离子体暗区通道;及RF电源,其连接到所述进气口结构以向其供应RF功率;
将所述衬底定位在所述衬底支架上;及
执行电容耦合的PE-CVD工艺,其中将RF功率提供给所述进气口结构,以生成在所述等离子体暗区通道中具有暗区的等离子体,从而使所述材料仅沉积在衬底的外围区域上。
11.根据权利要求10所述的方法,其中:
所述衬底支架包括边缘区域及用于接收衬底的中心区域,所述中心区域相对于所述边缘区域升高,其中所述进气口结构的所述中心区域与所述衬底支架的所述中心区域间隔开以限定所述等离子体暗区通道;
所述衬底比所述衬底支架的所述中心区域宽,且具有前表面、后表面及边缘表面,所述边缘表面连接所述前表面及所述后表面,使得当所述衬底位于所述衬底支架上时,所述前表面面向所述进气口结构,所述后表面背对所述进气口结构,且所述衬底的所述外围区域延伸出所述衬底支架的所述中心区域,由此将所述外围区域的所述后表面暴露于等离子体;及
所述执行所述电容耦合的PE-CVD工艺的步骤使所述材料沉积在所述衬底的所述外围区域中的所述后表面上。
12.根据权利要求11所述的方法,其中所述执行所述电容耦合的PE-CVD工艺的步骤还使所述材料沉积在所述衬底的所述边缘区域及所述外围区域中的所述前表面上。
13.根据权利要求10至11中任一项所述的方法,其中通过所述电容耦合的PE-CVD工艺沉积的所述材料是在后续蚀刻工艺期间保护所述衬底的保护材料。
14.根据权利要求13所述的方法,其中所述保护材料是氧化硅。
15.根据权利要求14所述的方法,其中所述PE-CVD前驱气体混合物包括SiH4及N2O。
16.根据权利要求13所述的方法,其中所述保护材料是SiN、SiON、SiOC或SiC。
17.根据权利要求10至12中任一项所述的方法,其中所述进气口结构的所述中心区域具有特性水平维度D1,所述衬底具有对应特性水平维度D,且比率D1/D在1.1至0.9。
18.根据权利要求10至12中任一项所述的方法,其中所述进气口结构的所述中心区域具有特性水平维度D1,所述衬底具有对应特性水平维度D,且比率D1/D在1.05至0.95的范围内。
19.根据权利要求11所述的方法,其中所述衬底支架的所述中心区域具有特性水平维度D2,所述衬底具有对应特性水平维度D,且比率D2/D在0.7至0.98。
20.根据权利要求11所述的方法,其中所述衬底支架的所述中心区域具有特性水平维度D2,所述衬底具有对应特性水平维度D,且比率D2/D在0.7至0.95的范围内。
21.根据权利要求10至12中任一项所述的方法,其中所述进气口结构的所述中心区域与所述衬底支架之间的间隔在所述电容耦合的PE-CVD工艺过程期间变化。
22.根据权利要求10至12中任一项所述的方法,其中所述衬底是半导体衬底。
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