CN113300717B - Efficient LDPC encoder circuit based on code rate self-adaptation - Google Patents
Efficient LDPC encoder circuit based on code rate self-adaptation Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/1151—Algebraically constructed LDPC codes, e.g. LDPC codes derived from Euclidean geometries [EG-LDPC codes]
Abstract
The invention discloses a high-efficiency LDPC encoder circuit based on code rate self-adaptation, which comprises: control unit, memory cell, selection element, high-efficient core cell and accumulator register unit, wherein: the control unit is used for sending the data in the storage unit to the high-efficiency core unit; the storage unit is used for storing the input matrix and the check data; the selection unit is used for selecting the data in the storage unit to be sent to the efficient core unit under the control of the control unit; the accumulation register unit is used for accumulating the calculation results of the high-efficiency core unit each time, and the proposed method effectively solves the problem that error correction cannot be carried out under severe signal-to-noise ratio under a changeable channel environment; by utilizing the signal-to-noise ratio information, the relationship between the performance of coding and the error correction performance can be dynamically balanced, so that the system efficiency is improved; the high-efficiency LDPC encoder framework not only ensures the transmission accuracy, but also effectively improves the transmission efficiency.
Description
Technical Field
The invention relates to the field of communication, in particular to a code rate self-adaptive efficient LDPC encoder circuit.
Background
In current digital communication systems, the transmission performance of the communication system is limited by the transmission robustness of data and the correctability of erroneous data. For this reason, channel coding techniques are often used in communication systems to cope with data errors caused by noise in transmission. In recent years, a Low Density Parity Check (LDPC) code has been proposed, which has many advantages such as low encoding and decoding complexity, high error correction performance, low error floor, and the like, and is widely used in the field of channel coding. However, since the check matrix usually has a large data size, the related circuits and system design are redundant. With the proposal of quasi-cyclic low-density parity check (QC-LDPC) codes, the coding circuit becomes simple, has smaller resource utilization rate and higher throughput, and is more suitable for hardware implementation. The current CCSDS near-ground standard adopts QC-LDPC code, which is called C2 code for short. This technique is heavily adopted in near-field applications.
However, at present, the channel environment for communication system transmission is more and more complex, and a plurality of environmental factors affect the stability of transmission. Especially in the case of variable channel conditions such as rainy or snowy weather, moving obstacles, etc., which all cause abrupt changes in the transmission channel. The signal-to-noise ratio of the abrupt channel may be severely faded, which exceeds the normal range of error correction at the original code rate. The consequence is that errors in data can occur, and in severe cases transmission failures can occur. How to deal with these variable channel environments has become an increasing concern.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a code rate self-adaptive high-efficiency LDPC encoder circuit.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that:
a code rate adaptation-based efficient LDPC encoder circuit, comprising: control unit, memory cell, selection element, high-efficient core cell and accumulator register unit, wherein:
the control unit is used for sending the data in the storage unit to the high-efficiency core unit;
the storage unit is used for storing the input matrix and the check data;
the selection unit is used for selecting the data in the storage unit to be sent to the efficient core unit under the control of the control unit;
the accumulation register unit is used for accumulating the calculation results of the high-efficiency core unit each time.
The scheme has the advantages that the code rate self-adaption information is effectively provided for the coding circuit, then the coding code length of the whole circuit is dynamically adjusted, and finally the coding data with different code rates are obtained, so that the decoding performance of the decoding circuit is effectively adjusted.
Further, the control unit includes an address counter, a 32-system counter, a 4-byte comparator, a first register and a first and gate, wherein an output end of the 32-system counter is connected to the first register and the address counter, an output end of the address counter is connected to an input end of the 4-byte comparator, another input end of the 4-byte comparator is linked to the storage unit and is used for obtaining an input matrix and check data in the storage unit, an output end of the address counter is connected to one input end of the and gate, an output end of the register is connected to another input end of the first and gate, and an output end of the and gate is connected to the selection unit.
The control unit circuit effectively compares the signal-to-noise ratio information with the coding mode required by the data, so as to check whether the current code rate requirement is met, and if the current code rate requirement is not met, effective code rate switching is carried out to match the decoding performance requirement under the signal-to-noise ratio.
Furthermore, the selection unit comprises a plurality of multiplexers and right shift registers with the same number, wherein the enabling ends of the plurality of multiplexers are sequentially cascaded, the output end of each level of multiplexer is connected with the input end of one right shift register, one input end of each level of multiplexer is connected to the storage unit, the other input end of each level of multiplexer is connected with the output end of the previous level of right shift register, one enabling end of the first level of multiplexer is connected with the output end of the first and gate, and the output end of the right shift register is connected to the high-efficiency core unit.
The beneficial effect of the above scheme is that the read-write code length in the storage unit is effectively changed, the sparse matrix is stored in the storage unit, and the code length is different according to the difference of the signal-to-noise ratio. The selection unit is controlled by the control unit and outputs corresponding matrix data to perform effective operation. Thereby effectively completing the code rate self-adapting function.
Furthermore, the storage unit is a matrix formed by a plurality of layers of data storage bits with the same length, wherein the first layer stores the first row data of the input matrix, the other layers store the check data, and each column of the matrix is used as an output and is respectively linked to the other input ends of the plurality of multiplexers.
The technical scheme has the advantages that the storage unit is realized by adopting a high-bit-width ROM structure, and the first row vector of the parity check matrix is stored inside the storage unit. And outputting data with different code lengths according to different code rates so as to facilitate subsequent product operation.
Further, the length of the data storage bits is the same as the number of the multiplexers and the right shift registers.
The beneficial effect of the above scheme is that the data of all sparse matrixes can be continuously circularly and rightly shifted during the calculation. The correctness of time sequence and data is ensured.
Further, the efficient core unit comprises a plurality of layers of parallel computing circuits, wherein each layer of parallel computing circuit simultaneously computes the input data streams of the plurality of layers in each clock cycle, and the accumulation computing is carried out on the accumulation register through the last layer of parallel computing circuit.
The scheme has the advantages that the parallelism degree of the whole operation is increased by the multilayer circuit, and the coding time of the whole circuit is effectively shortened by the high-parallelism mode. And accumulating the encoded data through a register so as to complete data iteration of the period.
Furthermore, a first layer of parallel computing circuit of the multilayer parallel computing circuit includes a plurality of and gates, wherein one input end of each and gate is connected to the output end of the right shift register, the other input end is connected to the first layer of input data stream, and the output end is used as the output of the current layer of parallel computing circuit.
The scheme has the advantages that for the two-input AND gate of each layer, the two-input AND gate is used as a multiplier of a binary field to complete binary multiplication operation between the sparse matrix and input data, and product data are temporarily stored through a register.
Furthermore, the rest of the multilayer parallel computing circuits in the multilayer parallel computing circuit have the same structure and comprise a plurality of and gates and exclusive or gates with the same number, wherein one input end of each and gate is respectively connected with the input data stream of the corresponding layer, and the other input end of each and gate is connected with the output end of the next-stage right shift register in the selection unit; one input end of each exclusive-OR gate is connected with the output end of the parallel computing circuit at the upper layer, the other input end of each exclusive-OR gate is connected with the output end of the current layer of the AND gate, the output end of each exclusive-OR gate is connected with the parallel computing circuit at the lower layer, and the output of the exclusive-OR gate in the last layer of the parallel computing circuit is used as the output end of the high-efficiency core unit.
The beneficial effect of the scheme is that the product result of the parallel circuit with 16 layers is accumulated, and the accumulation operation of the binary field is carried out through the two-input exclusive-OR gate. Compared with a logic addition circuit, the circuit has the characteristic of saving more logic resources.
Furthermore, the number of AND gates and XOR gates of each layer in the multilayer parallel computing circuit is the same as that of the right shift registers.
The scheme has the advantages that the binary domain accumulation operation is carried out through the two-input exclusive-OR gate, the complexity of respectively storing 16 layers of parallel circuits is effectively reduced through accumulation, and the storage operation in the clock period can be completed only through one group of registers.
Furthermore, the accumulator register unit comprises a plurality of exclusive-or gates and a register, wherein the number of the exclusive-or gates is the same as that of the exclusive-or gates, one input end of each exclusive-or gate is connected to the output end of the efficient core unit, the other input end of each exclusive-or gate is short-circuited with the output end of the register, the output end of each exclusive-or gate is connected with one input end of the register, and the output end of the register is the output of the code rate self-adaptive efficient LDPC encoder circuit.
The technical scheme has the advantages that a combination form of the register and the exclusive-OR gate is adopted, data are accumulated through the register through multiple rounds of iteration, and the accumulated value of the previous round is summed with the value to be accumulated of the current round through the exclusive-OR gate in a binary domain mode. Will eventually obtain the correct result
Drawings
FIG. 1 is a schematic diagram of the structure of the code rate adaptive high-efficiency LDPC encoder circuit according to the present invention.
Fig. 2 is a schematic diagram of a structure of a partitioned check matrix.
FIG. 3 is a simplified schematic diagram of a 4-byte comparator according to an embodiment of the present invention.
Fig. 4 is a simplified digital communication system according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
The invention is applied to the LDPC coding method through a code rate self-adaptive technology, and the coding rate is dynamically adjusted according to channel environment factors such as signal-to-noise ratio (SNR). The method mainly comprises the following steps: in a digital communication system, the block length of an LDPC check matrix is adjusted through signal-to-noise ratio information, and when the signal-to-noise ratio is low, the code length is shortened through a code rate self-adaptive technology to improve the error correction performance. When the signal-to-noise ratio is high, the code length is recovered through a code rate adaptive technology to improve the transmission performance. Based on the method, two circuit architectures are designed to ensure the hardware implementation of the method. Both architectures have better performance and lower resource utilization.
In order to guarantee the quasi-cyclic characteristics of QC-LDPC, a block shortening technology is adopted to shorten the code length, which effectively guarantees the characteristics of a quasi-cyclic matrix.
As can be seen from (1), the matrix H is composed of a circulant matrix. To ensure that the shortened matrix remains a QC-LDPC matrix, the smallest unit of shortening is defined as the circulant sub-matrix. We define the circulant sub-matrix of the same column as a block and the whole matrix H is divided into 16 blocks, each with 511 columns, as shown in fig. 2. By deleting the block, the code rate of the C2 code can be effectively changed, and the quasi-cyclic property is not changed.
For hardware implementation, the top 14 blocks (blocks) are the best choice to delete. The degree distribution of each node in the rule matrix is the same, which is not meaningful for the priority of deletion. So we have adopted a method of shortening in reverse order in C2 code, when shortening occurs, the 14 th block will be preferentially deleted.
In this shortening method, since a block is the minimum unit to be deleted, an arbitrary code rate cannot be generated, but 14 code rates can be selected as shown in table 1. The coding algorithm is shown in (2), where r is the code rate, the check sequence (p) in all code rates is 1022bits, but the new input vector (S)i) May vary in length.
TABLE 1 selectable code rates
In this shortening method, since a block is the minimum unit to be deleted, an arbitrary code rate cannot be generated, but 14 code rates can be selected as shown in table 1. The coding algorithm is shown in (2), where r is the code rate, the check sequence (p) in all code rates is 1022bits, but the new input vector (S)i) May vary in length.
Based on this, the present invention provides a code rate adaptive high efficiency LDPC encoder circuit, as shown in fig. 1, including: control unit, memory cell, selection element, high-efficient core cell and accumulator register unit, wherein:
the control unit is used for sending the data in the storage unit to the high-efficiency core unit;
the storage unit is used for storing the input matrix and the check data;
the selection unit is used for selecting the data in the storage unit to be sent to the efficient core unit under the control of the control unit;
the accumulation register unit is used for accumulating the calculation results of the high-efficiency core unit each time.
Specifically, the control unit comprises an address counter, a 32-bit counter, a 4-byte comparator, a first register and a first AND gate, wherein the output end of the 32-system counter is respectively connected with the first register and the address counter, the output end of the address counter is connected with the input end of a 4-byte comparator, the other input end of the 4-byte comparator is linked with the storage unit, used for obtaining the input matrix and the check data in the storage unit, the output end is connected with one input end of the AND gate, the output end of the register is connected with the other input end of the first AND gate, the output end of the AND gate is connected with the selection unit, in this embodiment, the control unit is composed of two counters and a comparator, the bit width of the snr is 4-bit, and the number of blocks in the matrix B replaces the true value of the snr at the current snr as the 4-bit input. When the input enable start is active, the loop times of the current block are accumulated in a 32-ary counter. When the carry signal is valid, the address counter is incremented by one, which is the address of the memory. The address of the Memory is compared with the snr by a comparator, and the address of the Memory cannot be larger than the snr, so that the function of converting the code rate is realized. Since the address less than or equal to snr is not important for the circuit function, part of the gate circuit in the conventional one-bit value comparator is simplified as shown in fig. 3, and the logic gate is reduced in the control unit.
The selection unit comprises a plurality of multiplexers with the same quantity and a right shift register, wherein the enabling ends of the plurality of selectors are sequentially cascaded, the output end of each level of multiplexer is connected with the input end of one right shift register, one input end of each level of multiplexer is connected to the storage unit, the other input end of each level of multiplexer is linked with the output end of the previous level of right shift register, one enabling end of the first level of multiplexer is connected with the output end of the first AND gate, and the output end of the right shift register is connected to the high-efficiency core unit.
The storage unit is a matrix formed by a plurality of layers of data storage bits with the same length, wherein the first layer stores the first row data of the input matrix, the other layers store the check data, and each column of the matrix is used as an output and is respectively linked to the other input ends of the plurality of multiplexers. In the embodiment, the architecture is composed of a memory, an efficient core and a control unit. And the first row of the matrix B is stored in the Memory, the check data is stored in the Memory, and the data is obtained by changing the input address of the Memory.
The high-efficiency core unit comprises a plurality of layers of parallel computing circuits, wherein each layer of parallel computing circuit simultaneously carries out clock cycle computation on a plurality of layers of input data streams and carries out accumulation computation on the accumulation register through the last layer of parallel computing circuit, specifically, the first layer of parallel computing circuit of the plurality of layers of parallel computing circuits comprises a plurality of AND gates, wherein one input end of each AND gate is respectively connected with the output end of the right shift register, the other input end of each AND gate is connected with the first layer of input data streams, and the output end of each AND gate is used as the output of the current layer of parallel computing circuit,
the other multilayer parallel computing circuits in the multilayer parallel computing circuit have the same structure and comprise a plurality of AND gates and XOR gates with the same number, wherein one input end of each AND gate is respectively connected with the input data stream of the corresponding layer, and the other input end of each AND gate is connected with the output end of the next-stage right shift register in the selection unit; one input end of each exclusive-OR gate is connected with the output end of the parallel computing circuit at the upper layer, the other input end of each exclusive-OR gate is connected with the output end of the current layer of the AND gate, the output end of each exclusive-OR gate is connected with the parallel computing circuit at the lower layer, and the output of the exclusive-OR gate in the last layer of the parallel computing circuit is used as the output end of the high-efficiency core unit.
In this embodiment, there are 16 layers of similar parallel computing circuits in the efficient kernel, and the first row vector is circularly right-shifted by 1bit from layer to layer. The first block of matrix B is computed first, while all blocks other than in the proposed miniaturized architecture are computed simultaneously. 512bit S due to 16 layers of circuits operating simultaneouslyiIs operated over 32 clock cycles. The 1022 registers storing the first row vector will be shifted circularly to the right by 16bits, and the mux will select whether to shift or reload the first row of the next block. First line and input vector SiThe products in the same column are summed by a 2-input exclusive-OR gate, and the summed result of each shift is accumulated by an accumulation register. When the operation of the ith block is finished, the first line of the (i + 1) th block is reloaded until the last block of the current signal-to-noise ratio is calculated.
In a specific manner of application, the coating is applied,
taking the simple digital communication system of fig. 4 as an example:
1) the data stream is processed by a Transmitter (Transmitter), passed through a noisy channel and sent to a Receiver (Receiver);
2) after a signal-to-noise ratio (SNR) is obtained by an encoder, a control unit evaluates the SNR, selects a corresponding code rate r, and simultaneously starts a comparator to detect an encoding period;
3) according to the code rate r, encoding an input vector, wherein a single input vector is 16bits, and only pure data (signal-to-noise ratio information SNR) is input;
4) data in the memory needs to be selected through the control unit and transmitted to the efficient core, and the data is subjected to encoding operation through the efficient core and a check matrix in the memory;
5) judging whether the coding delay reaches 64r/1-r clock cycles, executing the step 6), otherwise, executing the step 5);
6) the encoding process is finished, and the encoded data is modulated (modulation), transmitted through the channel, demodulated (modulation) to the LDPC decoding module, and the corresponding data is obtained after the information source decoding
The principle and the implementation mode of the invention are explained by applying specific embodiments in the invention, and the description of the embodiments is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (9)
1. A code rate adaptation-based efficient LDPC encoder circuit, comprising: control unit, memory cell, selection element, high-efficient core cell and accumulator register unit, wherein:
the control unit is used for sending data in the storage unit to the efficient core unit, and comprises an address counter, a 32-system counter, a 4-byte comparator, a first register and a first AND gate, wherein the output end of the 32-system counter is respectively connected with the first register and the address counter, the output end of the address counter is connected with the input end of the 4-byte comparator, the other input end of the 4-byte comparator is linked with the storage unit and used for acquiring an input matrix and check data in the storage unit, the output end of the control unit is connected with one input end of the AND gate, the output end of the register is connected with the other input end of the first AND gate, and the output end of the AND gate is connected with the selection unit;
the storage unit is used for storing the input matrix and the check data;
the selection unit is used for selecting the data in the storage unit to be sent to the efficient core unit under the control of the control unit;
the accumulation register unit is used for accumulating the calculation results of the high-efficiency core unit each time.
2. The code rate adaptive high efficiency LDPC encoder circuit according to claim 1, wherein the selection unit comprises a plurality of multiplexers and shift right registers, wherein a plurality of the multiplexer enable terminals are sequentially cascaded, the output terminal of each multiplexer is connected to the input terminal of a shift right register, one input terminal of each multiplexer is connected to the storage unit, the other input terminal of each multiplexer is connected to the output terminal of a shift right register, one enable terminal of a first multiplexer is connected to the output terminal of the first AND gate, and the output terminal of the shift right register is connected to the high efficiency core unit.
3. The code rate adaptation-based efficient LDPC encoder circuit according to claim 2, wherein the storage unit is a matrix comprising a plurality of layers of data storage bits with the same length, wherein a first layer stores the first row of data of the input matrix, and the remaining layers store the check data, and each column of the matrix is used as an output and is respectively linked to another input of the plurality of multiplexers.
4. The code rate adaptation-based high efficiency LDPC encoder circuit according to claim 3, wherein the data is stored as a length equal to the number of the multiplexers and right shift registers.
5. The code rate adaptation-based high efficiency LDPC encoder circuit according to claim 4, wherein the high efficiency core unit comprises a plurality of layers of parallel computation circuits, wherein each layer of parallel computation circuit performs clock cycle computation on the input data streams of the plurality of layers simultaneously, and the accumulation register is subjected to accumulation computation by the last layer of parallel computation circuit.
6. The code rate adaptive high efficiency LDPC encoder circuit according to claim 5, wherein the first layer of parallel computation circuits of the multi-layer parallel computation circuit comprises a plurality of AND gates, wherein one input terminal of each AND gate is connected to the output terminal of the right shift register, and the other input terminal is connected to the first layer of input data stream, and the output terminal is used as the output of the current layer of parallel computation circuit.
7. The code rate adaptive high-efficiency LDPC encoder circuit according to claim 6, wherein the rest of the multi-layer parallel computing circuits have the same structure and comprise a plurality of AND gates and XOR gates with the same number, wherein one input end of each AND gate is connected to the input data stream of the corresponding layer, and the other input end is connected to the output end of the next level shift register in the selection unit; one input end of each exclusive-OR gate is connected with the output end of the parallel computing circuit at the upper layer, the other input end of each exclusive-OR gate is connected with the output end of the current layer of the AND gate, the output end of each exclusive-OR gate is connected with the parallel computing circuit at the lower layer, and the output of the exclusive-OR gate in the last layer of the parallel computing circuit is used as the output end of the high-efficiency core unit.
8. The code rate adaptation-based high efficiency LDPC encoder circuit according to claim 7, wherein the number of AND gates and XOR gates in each layer of the multi-layer parallel computation circuit is the same as the number of right shift registers.
9. The code rate adaptation-based high efficiency LDPC encoder circuit according to claim 8, wherein the accumulator register unit comprises a plurality of same number of XOR gates and shift-right registers, wherein one input of each XOR gate is connected to the output of the high efficiency core unit, the other input of each XOR gate is shorted to the output of the shift-right register, and the output of each XOR gate is connected to one input of the shift-right register, and the output of each shift-right register is the output of the code rate adaptation-based high efficiency LDPC encoder circuit.
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