CN102624402B - LDPC (low density parity check) decoder - Google Patents

Abstract

The invention relates to an LDPC (low density parity check) decoder, which comprises p dual-port rams (random access memories), a second rom (read-only memory), a first data-shift unit, a subtracter, p calculators, a third ram, an adder, p FIFO (first in first out) queue buffers and a second data-shift unit. A data block Ci is composed of data from the same address i; the second rom is used for storing a check matrix H with grouping characteristics; the first data-shift unit is used for rotating the parallel output data of the dual-port data left x bits according to the serial number x (x is not equal to -1) of the submatrix P of the check matrix H, and the Px is a matrix formed by each column of the unitary matrix right shifting x bits; an input end of the subtracter is connected with the first data-shift unit, and an output end of the subtracter is connected with the calculators; the calculators are used for parallelly calculating the output difference d according to the check equation; an input end of the third ram storing d is connected with the calculators, an output end of the third ram is connected with the subtracter serving as a minuend, and the third ram is used for parallelly outputting the output data of each calculator; an input end of the adder is connected with the calculators; input ends of the p FIFO queue buffers are connected with the subtracter, and output ends of the p FIFO queue buffers are connected with the adder; an input end of the second data-shift unit is connected with the adder, an output end of the second data-shift unit is connected with the dual-port rams, and the second data-shift unit is used for replacing the original position data after shifting the calculated data reversely.

Description

A kind of ldpc decoder

Technical field

The present invention relates to compile and separate error correcting code field, be specifically related to a kind of low density parity check code (LDPC) decoder.

Background technology

Binary data is in transmitting procedure, usually some noises or interference can be run into, and cause when receiving, having error code appearance, when wireless transmission, these electronic noises cannot be avoided usually especially, when 330 receiving if there is error in data, a kind of mode, we can reject and require that the other side resends, but under many circumstances, data send in real time, do not allow operation above; Error correcting code just grows up for this reason, and in a communications system, usually use forward error correction detect and correct error code, low density parity check code (LDPC) is exactly a kind of block code.

When transmitting data, forward error correction can additionally increase some bits according to certain algorithm, these bits are for data being exactly redundancy, receiver can according to the check digit of the data received and redundancy, judge that the data transmitted are logical one or logical zero, or receiver can provide a probability, be used for representing that data are probability sizes of logical one or logical zero, such data are soft-decision data.Decode procedure uses maximum likelihood method usually, obtains a guess data the most close with former transmission data.At present, the forward error correction be widely used has a variety of, such as convolutional encoding, inner institute code (RS code), turbo code.LDPC is that latest developments are very fast and obtain a kind of block code of multiple host-host protocol accreditation, and its general decoding algorithm is sum-product algorithm (Summary-Product Rule).According to the principle of sum-product algorithm, people have developed again his approximate data---iterative algorithm, iterative algorithm can realize with hardware circuit, but existing method exists in realization, and complexity is high, resource occupation is large, efficiency is low, slow-footed problem, and this just hinders the extensive use of LDPC.As shown in Figure 1, the U.S. in first patent, the patent No. (US 6633856 B2), the technology frame chart adopted, it completes and once calculates needs two circulations and realize, treatment variable node 1708 and restraint joint 1709 respectively, and the processing time is long; Mainly employ two groups of memories 1707 and 1706 in iteration, also used two additional storages 1712 and 1710, the process of whole iterative process is more complicated, and the memory used is more, and resource occupation is large, for the control also relative complex of whole handling process.

Summary of the invention

The technical issues that need to address of the present invention are, how a kind of ldpc decoder is provided, adopt the circuit structure of parallel computation, by the mode of grouping, can realize calculating check equations all in a group simultaneously, whole iterative process is undertaken by group, and only employs same computing module and storage stack, with the memory resource reaching reduction complexity, reduction takies, raises the efficiency the object with speed.

Technical problem of the present invention solves like this: build a kind of ldpc decoder, comprising:

P dual-ported memory (ram A ^q), be positioned at data input pin, each data block C _ip data (C _i1, C _i2, C _i3... C _ip) stored in p described dual-ported memory (ram A ^q) same address i, wherein: p > q>=0, p be greater than 1 natural number, i, q are integers;

For storing the second memory (rom H) of check matrix H, (the ram A of dual-ported memory described in control connection ^q); Described check matrix H has packet characteristic;

First data shifts unit, input connects described dual-ported memory (ram A ^q), for according to the numbering x except x=-1 of check matrix H neutron array P to described dual-ported memory (ram A ^q) current address i parallel output data [C _i1, C _i2, C _i3... C _ip] ring shift left x position, wherein: be numbered the P of 0 ₀be the unit matrix of p × p, be numbered the P of-1 _-1be the full null matrix of p × p, except x=-1, be numbered the P of x _xp ₀often arrange the matrix behind the x position that moves to right ,-1≤x < p, x is integer;

Subtracter, an input connects the first data shifts unit as subtrahend;

P calculator, input connects described subtractor outputs, each calculator according to check equations to respective N number of serial input data C _jcalculate, parallel computation exports difference d _j, natural number N is more than or equal to natural number j;

For storing the 3rd memory (the ram d of all difference d _q), input connects p described calculator output, output connects described subtracter another input as minuend, for the result of calculation of each described calculator of parallel output when upper once iteration, i.e. and difference d;

Adder, an input connects described calculator output;

P First Input First Output buffer (FIFO ^q), another input that input connects described subtractor outputs, output connects described adder;

Second data shifts unit, input connects described adder output, output connects described dual-ported memory (ram A ^q), replace legacy data on described dual-ported memory correspondence position afterwards for exporting the datacycle x position that moves to right according to the numbering x of check matrix H neutron array P to adder.

According to ldpc decoder provided by the invention, described data input pin is serial input terminal, and this decoder also comprises the splitter of one point of p between described serial input terminal and dual-ported memory.

According to ldpc decoder provided by the invention, include, but are not limited to select following concrete form:

(1) N=3, p=7;

(2) N=24, p=10;

(3) N=96, p=20.

Ldpc decoder provided by the invention, adopt the circuit structure of parallel computation, comparatively prior art has the following advantages:

1, for the effective storage of result of calculation;

2, the scale of memory required in iteration is reduced;

3, overall decoding process complexity is reduced.

Accompanying drawing explanation

Below in conjunction with the drawings and specific embodiments, the present invention is described in detail further:

Fig. 1 is the structural principle block diagram of existing ldpc decoder;

Fig. 2 is the structural principle block diagram of ldpc decoder of the present invention;

Fig. 3 is calculator first component hardware logic schematic diagram in Fig. 2;

Fig. 4 is calculator second component hardware logic schematic diagram in Fig. 2;

Fig. 5 is the hardware logic structure schematic diagram of the ldpc decoder of the specific embodiment of the invention.

Embodiment

First, the present invention basis is described, block code and grouping matrix:

(1) block code

Usual block code can be expressed as (n, k), and n is block size, and k is information bit, and n-k is check digit.When coding, usually use generator matrix G, it is the matrix of a k × n; Input information is E, and it is the matrix (namely row vector) of a 1 × k, and the code character after coding is B, and it is the matrix of 1 × n.B=EG, gives one example: k=4, n=7; G is exactly the matrix of 4 × 7

$G=\left[\begin{array}{ccccccc}1& 0& 0& 0& 1& 1& 1\\ 0& 1& 0& 0& 1& 1& 0\\ 0& 0& 1& 0& 1& 0& 1\\ 0& 0& 0& 1& 0& 1& 1\end{array}\right]$

E is the row vector containing 4 elements, supposes, E=[E ₀e ₁e ₂e ₃]

B is the row vector containing 7 elements, supposes, B=[B ₀b ₁b ₂b ₃b ₄b ₅b ₆]

According to formula B=EG

$B=\left[\begin{array}{cccc}{E}_0& E_1& E_2& E_3\end{array}\right]\left[\begin{array}{ccccccc}1& 0& 0& 0& 1& 1& 1\\ 0& 1& 0& 0& 1& 1& 0\\ 0& 0& 1& 0& 1& 0& 1\\ 0& 0& 0& 1& 0& 1& 1\end{array}\right]=\left[\begin{array}{ccccccc}{E}_0& E_1& E_2& E_3& E_0+E_1+E_2& E_0+E_1+E_3& E_0+E_2+E_3\end{array}\right]$

So:

B ₀＝E ₀

B ₁＝E ₁

B ₂＝E ₂

B ₃＝E ₃

B ₄＝E ₀+E ₁+E ₂

B ₅＝E ₀+E ₁+E ₃

B ₆＝E ₀+E ₂+E ₃

Can find out, after coding, front 4 elements are still consistent with the A of input, and latter 3 is the check digit calculated.

After the modulated device of data B sends, propagate in noisy channel, at receiving terminal, the data that demodulator receives represent with C,

C＝[C ₀C ₁C ₂C ₃C ₄C ₅C ₆]

Verify the B whether C that receives is still original, when this just needs to check coding, whether check equations of application is set up, namely

C ₄＝C ₀+C ₁+C ₂

C ₅＝C ₀+C ₁+C ₃

C ₆＝C ₀+C ₂+C ₃

Whether these 3 equations are set up, and this verification relation is decided by check matrix H, H and G is one to one, and they meet GH ^t=0, H ^tit is the transposed matrix of H.According to G above, the check matrix H corresponding with him can be drawn,

$H=\left[\begin{array}{ccccccc}1& 1& 1& 0& 1& 0& 0\\ 1& 1& 0& 1& 0& 1& 0\\ 1& 0& 1& 1& 0& 0& 1\end{array}\right]$

So when decoding, as long as checking HC ^twhether be 0, C ^tit is the transposed matrix of C.Work as HC ^twhen=0, show that check equations is set up, data C is errorless; Otherwise data C is wrong.

${\mathrm{HC}}^T\left[\begin{array}{ccccccc}1& 1& 1& 0& 1& 0& 0\\ 1& 1& 0& 1& 0& 1& 0\\ 1& 0& 1& 1& 0& 0& 1\end{array}\right]{\left[\begin{array}{ccccccc}{C}_0& C_1& C_2& C_3& C_4& C_5& C_6\end{array}\right]}^T$

$=\left[\begin{array}{ccccccc}1& 1& 1& 0& 1& 0& 0\\ 1& 1& 0& 1& 0& 1& 0\\ 1& 0& 1& 1& 0& 0& 1\end{array}\right]\left[\begin{array}{c}{C}_0\\ C_1\\ C_2\\ C_3\\ C_4\\ C_5\\ C_6\end{array}\right]$

$=\left[\begin{array}{c}{C}_0+C_1+C_2+C_4\\ C_0+C_1+C_3+C_5\\ C_0+C_2+C_3+C_6\end{array}\right]$

Find have three check equations to need to calculate by deriving $\left\{\begin{array}{c}{C}_0+C_1+C_2+C_4=0\\ C_0+C_1+C_3+C_5=0\\ C_0+C_2+C_3+C_6=0\end{array}\right.$

Equation is set up, then data C is errorless; Otherwise data C is wrong.Verification relation when these three equations and coding $\begin{array}{c}{B}_4=E_0+E_1+E_2\\ B_5=E_0+E_1+E_3\\ B_6=E_0+E_2+E_3\end{array}$ Consistent (in the computing of a bit, 1+1=1-1=0).

According to analysis above, when decoding, topmost foundation is exactly check matrix H, and he determines the verification relation between information bit and check digit, is finally to carry out decoding by the mode of calculation check equation.

Patent of the present invention proposes a kind of Hardware Implementation of Parallel Iteration Decoding Method of LDPC code, but the method be not suitable for all LDPC code, and he can only be applied to the check matrix H of packet characteristic.

(2) divide into groups matrix (matrix of expansion)

Grouping matrix is the special matrix of a class, first, there is a basis matrix S (m × l, the capable l row of m), then expand it with a factor p, thus obtain a pm × pl matrix S ', in former basis matrix S 0 with a p × p complete zero submatrix replacement, in former basis matrix S 1 replaces (this submatrix is the form after the unit matrix of p × p or unit matrix move to right, and its each row and column all only have one 1) with the non-full zero submatrix of a p × p.

Suppose that S is the matrix of 3 × 7

$S=\left[\begin{array}{ccccccc}1& 1& 1& 0& 1& 0& 0\\ 1& 1& 0& 1& 0& 1& 0\\ 1& 0& 1& 1& 0& 0& 1\end{array}\right]$

P=3, first, we all p × p sub-matrix columns out,

$P_0=\left[\begin{array}{ccc}1& 0& 0\\ 0& 1& 0\\ 0& 0& 1\end{array}\right],$ It is exactly the unit matrix of 3 × 3

$P_1=\left[\begin{array}{ccc}0& 1& 0\\ 0& 0& 1\\ 1& 0& 0\end{array}\right],$ Be exactly P ₀in every row ring shift right one, rightmost one row have moved on to the Far Left of matrix

$P_2=\left[\begin{array}{ccc}0& 0& 1\\ 1& 0& 0\\ 0& 1& 0\end{array}\right],$ Be exactly P ₀in every row ring shift right two

$P_{-1}=\left[\begin{array}{ccc}0& 0& 0\\ 0& 0& 0\\ 0& 0& 0\end{array}\right],$ It is full null matrix

Then, P is used _-1to substitute in S original 0, use P ₀, P ₁, P ₂to come in alternative S original 1.Substituting with which submatrix specific to each 1 is to arrange arbitrarily, and we expand according to wherein a kind of alternative hypothesis, obtain 9 × 21 matrix S '

$S^{\&prime;}=\left[\begin{array}{ccccccccccccccccccccc}1& 0& 0& 0& 0& 1& 1& 0& 0& 0& 0& 0& 1& 0& 0& 0& 0& 0& 0& 0& 0\\ 0& 1& 0& 0& 0& 0& 0& 1& 0& 0& 0& 0& 0& 1& 0& 0& 0& 0& 0& 0& 0\\ 0& 0& 1& 0& 1& 0& 0& 0& 1& 0& 0& 0& 0& 0& 1& 0& 0& 0& 0& 0& 0\\ 0& 1& 0& 0& 1& 0& 0& 0& 0& 1& 0& 0& 0& 0& 0& 1& 0& 0& 0& 0& 0\\ 0& 0& 1& 1& 0& 1& 0& 0& 0& 0& 1& 1& 0& 0& 0& 0& 1& 0& 0& 0& 0\\ 1& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 1& 0& 0& 0\\ 0& 0& 1& 0& 0& 0& 1& 1& 0& 0& 1& 1& 0& 0& 0& 0& 0& 0& 1& 0& 0\\ 1& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 1& 0\\ 0& 1& 0& 0& 0& 0& 0& 0& 1& 1& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 1\end{array}\right]$

For convenience of description, we usually with this mode below express above 9 × 21 matrix

$S^{\&prime;}=\left[\begin{array}{ccccccc}{P}_0& P_2& P_0& P_{-1}& P_0& P_{-1}& P_{-1}\\ P_1& P_1& P_{-1}& P_0& P_{-1}& P_0& P_{-1}\\ P_2& P_{-1}& P_0& P_1& P_{-1}& P_{-1}& P_0\end{array}\right]$

The second, describe specific implementation of the present invention in detail:

(1) hardware configuration

Ldpc decoder of the present invention, structure as shown in Figure 2, specifically comprises:

P dual-ported memory (ram A ^q), be positioned at data input pin, each data block C _ip data (C _i1, C _i2, C _i3... C _ip) stored in p described dual-ported memory (ram A ^q) same address i, wherein: p > q>=0, p be greater than 1 natural number, i, q are integers;

For storing the second memory (rom H) of check matrix H, (the ram A of dual-ported memory described in control connection ^q); Described check matrix H has packet characteristic;

First data shifts unit, input connects described dual-ported memory (ram A ^q), for the numbering x (during x ≠-1) according to check matrix H neutron array P to described dual-ported memory (ramA ^q) current address i parallel output data [C _i1, C _i2, C _i3... C _ip] ring shift left x position, wherein: be numbered the P of 0 ₀be the unit matrix of p × p, be numbered the P of-1 _-1be the full null matrix of p × p, be numbered the P of x (during x ≠-1) _xp ₀often arrange the matrix behind the x position that moves to right ,-1≤x < p, x is integer;

Subtracter, an input connects the first data shifts unit as subtrahend;

P calculator, input connects described subtractor outputs, each calculator according to check equations to respective N number of serial input data C _j(N>=j > 0) calculates, and parallel computation exports difference d _j(N>=j > 0);

For storing the 3rd memory (the ram d of all difference d _qp > q>=0), input connects p described calculator output, output connects described subtracter another input as minuend, for the result of calculation of each described calculator of parallel output when upper once iteration, i.e. and difference d;

Adder, an input connects described calculator output;

P First Input First Output buffer (FIFO ^q), another input that input connects described subtractor outputs, output connects described adder;

Second data shifts unit, input connects described adder output, output connects described dual-ported memory (ram A ^q), replace legacy data on described dual-ported memory correspondence position afterwards for exporting the datacycle x position that moves to right according to the numbering x of check matrix H neutron array P to adder.

(2) detailed decoded operation and specific works step

1. input the storage of data

That deliver to decoder is log-likelihood ratio (LLR) the data C that demodulation exports, and these data have rbit (r >=3) bit wide, and are serial inputs.When stored in dual-port ram A, first divide into groups, in the structure of parallel computation, the number of grouping is consistent with the factor p of submatrix, and every p data are a data block, with i ( n is block size, and p is the factor of submatrix) mark different data blocks, according to the length of LDPC code block, i has different maximums.As under the same address that p data of same data block need stored in dual-port ram A, this p data can be read when reading so simultaneously; So we are individual for dual-port ram A p little dual-port ram A ^q(p > q>=0) realizes, p the data of same like this data block i, just can stored in the individual little dual-port ram A of p ^qall data are first divided into data block and store, just complete step 1 by the same address i of (p > q>=0).

2. data reading and preliminary treatment

According to the factor p of submatrix, one group can calculate p check equations, and the information of check equations is all stored in the check matrix H of LDPC code, and when encoding, H is the foundation of coding; When decoding, H is also the foundation of calculation check equation.In a decoder, we store H with a rom, before calculating, need will to participate in the data block of this group check equations from dual-port ram A according to the information of matrix H ^qread in (p > q>=0), this is mainly by control ram A ^qread address to realize, first, read first the data block i and C participating in this check equations _i1, C _i2, C _i3... C _ip, put in order (mode by moving to left or moving to right) of this p data is adjusted according to the numbering of check matrix H neutron array P.After displacement, the result d that when also will deduct last iteration, this group check equations calculates _i1, d _i2, d _i3... d _ip(not needing during iteration first), because the result that check equations calculates, be not available to affect he self calculating next time.Secondly, in the same way, read second data block, the 3rd data block that participate in this check equations, until N number of data block, N is the number of the data participating in this check equations, namely basis matrix S often in row element be the number of 1.In realization, p data in same data block be parallel work-flow (while), first data block, second data block, the 3rd data block, until N number of data block they are serial operation (time is successively order).Final output, the data flow that p group is parallel, each data flow C _j(N>=j > 0) comprises N number of serial data and namely constitutes check equations.

3. calculation check equation

Calculator, in the hardware configuration of LDPC realization of decoding, is a very important ring.It is responsible for calculation check equation, provides value and difference that input data need adjustment, for calculating afterwards provides correction.In the structure of parallel computation, the number of the calculator that we introduce is consistent with the factor p of submatrix, and for a calculator, its concrete step is: suppose that input serial data is C _j(N>=j > 0), first, verify whether this check equations is set up, and we calculate (hd is C _jsign bit, it is 1bit binary data, adds so summation operation here is just equivalent to mould two), its realize hardware logic structure as shown in Figure 3, wherein:

As correct=0, represent that the data sequence of input meets check equations;

As correct=1, represent that the data sequence of input does not meet check equations.

Difference d _j(N>=j > 0), with the C of input _jone to one, be also by symbol and amplitude dimerous, also calculate respectively in calculator.Symbol hd (the d of difference _j)=hd (C _j)+correct (being also that mould two adds here), its realize hardware logic structure as shown in Figure 3, wherein:

Difference d _jamplitude calculate need following step: first to find out serial data C _jmiddle amplitude min value MIN ₁, MIN ₁=min (amp (C _j)), and it is in sequence C _jin position v; Then sequence C is found out _jin amplitude second little value MIN ₂, MIN ₂=min (amp (C _j)), for (j ≠ v); 3rd calculates Ivl_out, lvl_out=max (0, MIN ₁-f (MIN ₂-MIN ₁)) wherein the expression formula of function f (x) be:

$f\left(x\right)=\begin{array}{ccc}\begin{array}{c}3\\ 2\\ 1\\ 0\end{array}& \mathrm{for}& \begin{array}{c}x<2\\ 2\&le;x<4\\ 4\&le;x<8\\ 8\&le;x\end{array}\end{array}$

Amp (d can be obtained thus _j):

amp(d _j)＝lvl_out，for(j≠v)；amp(d _v)＝MIN ₂

So difference d _jamplitude have 2 kinds of possible outputs, as j=v, amp (d _v)=MIN ₂; For other C _j(j ≠ v), amp (d _j)=lvl_out; Said above, the result of calculating will store, for serial data C _jin each data, all can difference d corresponding to Serial output one _j(N>=j > 0).P calculator concurrent working simultaneously, can parallel output p difference d _i1, d _i2, d _i3... d _ip, with p memory ram d _q, (p > q>=0) stores these data.

4. store revised data

After having calculated, the difference of parallel output and First Input First Output buffer (FIFO ^q) output be added; Then result is deposited by the second data shifts unit again and get back to dual-port ram A ^qin, then just can start the calculating of next check equations.

3rd, further describe in conjunction with the specific embodiment of the invention:

(1) hardware configuration

The ldpc decoder of the specific embodiment of the invention, structure as shown in Figure 5, specifically comprises:

The splitter of one point three, is positioned at data input pin, serial input is transferred to parallel input;

Three dual-ported memories, connect splitter corresponding ports;

For storing the second memory of check matrix H, dual-ported memory described in control connection; Described check matrix H has packet characteristic;

First data shifts unit, input connects described dual-ported memory, for according to the numbering x of check matrix H neutron array P to described dual-ported memory current address i parallel output data [C _i1, C _i2, C _i3... C _ip] ring shift left x position, wherein: be numbered the P of 0 ₀be the unit matrix of 3 × 3, be numbered the P of-1 _-1be the full null matrix of 3 × 3, be numbered the P of x (during x ≠-1) _xp ₀often arrange the matrix behind the x position that moves to right ,-1≤x < p, k is integer;

Subtracter, an input connects the first data shifts unit as subtrahend;

Three calculators, input connects described subtractor outputs, each calculator according to check equations to the respective individual serial input data C of N (in example N=4) _j(N>=j > 0) is (as [C in example ₀₀c ₁₂c ₂₀c ₄₀]) calculate, parallel computation exports difference d _j(N>=j > 0) is (as [d in example ⁰ ₀₀d ⁰ ₁₀d ⁰ ₂₀d ⁰ ₄₀]);

For storing the 3rd memory of all difference d, input connects three described calculator outputs, output connects described subtracter another input as minuend, for each described calculator of parallel output simultaneously or the difference d that exports of same time sequencing;

Adder, an input connects described calculator output;

Three First Input First Output buffers, another input that input connects described subtractor outputs, output connects described adder;

Second data shifts unit, input connects described adder output, output connects described dual-ported memory, for replacing data in original correspondence position according to the numbering x of check matrix H neutron array P afterwards to the x position that moves to right of the datacycle after calculating.

(2) detailed decoded operation and specific works step

Using the matrix S ' as the check matrix H of this example provided, illustrate the embodiment of whole parallel decoding above.

1. the storage of data input

For block code, input data by the input of code block one piece a piece, will suppose that current input code block is C,

C＝[C ₀C ₁C ₂C ₃C ₄C ₅C ₆C ₇C ₈C ₉C ₁₀C ₁₁C ₁₂C ₁₃C ₁₄C ₁₅C ₁₆C ₁₇C ₁₈C ₁₉C ₂₀]

Each input data are rbit (r >=3) LLR value (log-likelihood ratio), deposit in dual-port ram A, common way is one by one stored in ram A by input data, in the present invention, we first divide into groups input code block C, the foundation of grouping is the spreading factor p (in this instance p=3) of check matrix H, so first by the order of the data in C by input, and every 3 data one group; After grouping, C can be expressed as

C＝[C ₀₀C ₀₁C ₀₂C ₁₀C ₁₁C ₁₂C ₂₀C ₂₁C ₂₂C ₃₀C ₃₁C ₃₂C ₄₀C ₄₁C ₄₂C ₅₀C ₅₁C ₅₂C ₆₀C ₆₁C ₆₂]

Wherein C ₀₁in 0 represent the 0th group, in 1 expression group, label is the data of 1;

When storing, needing the dual-port ram A that 3 identical, being expressed as A ⁰, A ¹, A ².Label in each group is that the data of 0 are stored in A ⁰in; Label in each group is that the data of 1 are stored in A ¹in; Label in each group is that the data of 2 are stored in A ²in; Stored in address determined by little group #.

So, C ₀₀, C ₀₁, C ₀₂will successively stored in A ⁰, A ¹, A ²address 0 in;

C ₁₀, C ₁₁, C ₁₂will successively stored in A ⁰, A ¹, A ²address 1 in;

C ₆₀, C ₆₁, C ₆₂will successively stored in A ⁰, A ¹, A ²address 6 in;

After storing in this manner, when reading, just can by the data of same a small group (such as C ₀₀, C ₀₁, C ₀₂) read out simultaneously.

2. data reading and preliminary treatment

To stored in code block, be about to begin and carry out iterative decoding, main calculating is exactly verify each check equations, revises the LLR value of data by checking check equations.Before the computation, data need according to the needs of check equations from A ⁰, A ¹, A ²middle reading, then through preliminary treatment, then sends in calculator and calculates.

Contain the information of all check equations in check matrix H, according to the grouping situation of H itself, the calculating of check equations also will be divided into groups, all check equations in same group, walks abreast and calculates simultaneously.First by matrix multiplication HC ^t, list all check equations.

${\mathrm{HC}}^T=\left[\begin{array}{ccccccccccccccccccccc}1& 0& 0& 0& 0& 1& 1& 0& 0& 0& 0& 0& 1& 0& 0& 0& 0& 0& 0& 0& 0\\ 0& 1& 0& 1& 0& 0& 0& 1& 0& 0& 0& 0& 0& 1& 0& 0& 0& 0& 0& 0& 0\\ 0& 0& 1& 0& 1& 0& 0& 0& 1& 0& 0& 0& 0& 0& 1& 0& 0& 0& 0& 0& 0\\ 0& 1& 0& 0& 1& 0& 0& 0& 0& 1& 0& 0& 0& 0& 0& 1& 0& 0& 0& 0& 0\\ 0& 0& 1& 0& 0& 1& 0& 0& 0& 0& 1& 0& 0& 0& 0& 0& 1& 0& 0& 0& 0\\ 1& 0& 0& 1& 0& 0& 0& 0& 0& 0& 0& 1& 0& 0& 0& 0& 0& 1& 0& 0& 0\\ 0& 0& 1& 0& 0& 0& 1& 0& 0& 0& 1& 0& 0& 0& 0& 0& 0& 0& 1& 0& 0\\ 1& 0& 0& 0& 0& 0& 0& 1& 0& 0& 0& 1& 0& 0& 0& 0& 0& 0& 0& 1& 0\\ 0& 1& 0& 0& 0& 0& 0& 0& 1& 1& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 1\end{array}\right]\left[\begin{array}{c}{C}_{00}\\ C_{01}\\ C_{02}\\ C_{10}\\ C_{11}\\ C_{12}\\ C_{20}\\ C_{21}\\ C_{22}\\ C_{30}\\ C_{31}\\ C_{32}\\ C_{40}\\ C_{41}\\ C_{42}\\ C_{50}\\ C_{51}\\ C_{52}\\ C_{60}\\ C_{61}\\ C_{62}\end{array}\right]$

$=\begin{array}{c}\end{array}\left[\begin{array}{c}{C}_{00}+C_{12}+C_{20}+C_{40}\\ C_{01}+C_{10}+C_{21}+C_{41}\\ C_{02}+C_{11}+C_{22}+C_{42}\\ C_{01}+C_{11}+C_{30}+C_{50}\\ C_{02}+C_{12}+C_{31}+C_{51}\\ C_{00}+C_{10}+C_{32}+C_{52}\\ C_{02}+C_{10}+C_{31}+C_{60}\\ C_{00}+C_{21}+C_{32}+C_{61}\\ C_{01}+C_{22}+C_{30}+C_{62}\end{array}\right]$

Totally 9 check equations, because p=3, so by check equations by order every 3 group from top to bottom, the check equations with group realizes parallel computation.The data of carrying out parallel computation, when reading, read, for first group of check equations simultaneously.

1. give A simultaneously ⁰, A ¹, A ²address 0 is read in tax;

2. A ⁰, A ¹, A ²export data simultaneously, be designated as [C ₀₀c ₀₁c ₀₂], because be export simultaneously, so represent with a vector;

3. according to the numbering of check matrix H neutron array P, to [C ₀₀c ₀₁c ₀₂] be shifted;

$H=\left[\begin{array}{ccccccc}{P}_0& P_2& P_0& P_{-1}& P_0& P_{-1}& P_{-1}\\ P_1& P_1& P_{-1}& P_0& P_{-1}& P_0& P_{-1}\\ P_2& P_{-1}& P_0& P_1& P_{-1}& P_{-1}& P_0\end{array}\right]$

The corresponding first group of check equations of the first row above in H, the first submatrix P of the first row ₀represent [C ₀₀c ₀₁c ₀₂] shift value is 0, do not need displacement.

4. [the C after displacement ₀₀c ₀₁c ₀₂] just deliver to respectively 3 independently in calculator (during only for iteration first), during non-iteration first, the difference [d of this group check equations output when deduct last iteration ⁰ ₀₀d ⁰ ₀₁d ⁰ ₀₂] after, then deliver to 3 respectively independently in calculator.The calculating of difference can be described in the calculator below.

5. A is given ⁰, A ¹, A ²address 1 is read in tax;

6. A ⁰, A ¹, A ²export data simultaneously, be designated as [C ₁₀c ₁₁c ₁₂];

7. second submatrix P of the first row ₂represent [C ₁₀c ₁₁c ₁₂] shift value is 2, to [C ₁₀c ₁₁c ₁₂] ring shift left 2;

8. [the C after displacement ₁₂c ₁₀c ₁₁] just deliver to respectively 3 independently in calculator (during only for iteration first), during non-iteration first, the difference [d of this group check equations output when deduct last iteration ⁰ ₁₀d ⁰ ₁₁d ⁰ ₁₂] after, then deliver to 3 respectively independently in calculator.

Perform identical operation below, [C ₂₀c ₂₁c ₂₂], [C ₄₀c ₄₁c ₄₂] read, be shifted, deduct difference feeding calculator.

3. calculation check equation

Because be parallel computation, so will use multiple identical calculator simultaneously, be 3 in this instance, we analyze the process of a calculator, other identical.

We analyze the calculating of first check equations in first group of check equations below:

The serial data being input to check equations is: [C ₀₀c ₁₂c ₂₀c ₄₀]

Whether be 0, because C if first will calculate this check equations ₀₀the data of rbit, so the sign bit will getting him when calculating is added, hd (C ₀₀) be exactly get C ₀₀sign bit.

correct＝hd(C ₀₀)+hd(C ₁₂)+hd(C ₂₀)+hd(C ₄₀)

As correct=0, represent that the data sequence of input meets check equations;

As correct=1, represent that the data sequence of input does not meet check equations.

Afterwards, the difference exported is calculated

1. the symbol of calculated difference

hd(d ⁰ ₀₀)＝correct+hd(C ₀₀)

hd(d ⁰ ₁₀)＝correct+hd(C ₁₂)

hd(d ⁰ ₂₀)＝correct+hd(C ₂₀)

hd(d ⁰ ₄₀)＝correct+hd(C ₄₀)

2. the amplitude of calculated difference

First serial data [C to be found out ₀₀c ₁₂c ₂₀c ₄₀] middle amplitude min value MIN ₁, MIN ₁=min (amp (C ₀₀), amp (C ₁₂), amp (C ₂₀), amp (C ₄₀)) amp represents amplitude, and its position v in the sequence; Suppose MIN ₁=amp (C ₂₀), then find out the little value MIN of amplitude second in sequence ₂, MIN ₂=min (amp (C ₀₀), amp (C ₁₂), amp (C ₄₀)); Three, Ivl_out, lvl_out=max (0, MIN is calculated ₁-f (MIN ₂-MIN ₁)) wherein the expression formula of function f (x) be:

$f\left(x\right)=\begin{array}{ccc}\begin{array}{c}3\\ 2\\ 1\\ 0\end{array}& \mathrm{for}& \begin{array}{c}x<2\\ 2\&le;x<4\\ 4\&le;x<8\\ 8\&le;x\end{array}\end{array}$

There is Ivl_out and MIN ₂just can the amplitude of calculated difference, for the C that amplitude is minimum ₂₀,

Its

amp(d ⁰ ₂₀)＝MIN ₂

For other inputs

amp(d ⁰ ₀₀)＝amp(d ⁰ ₁₀)＝amp(d ⁰ ₄₀)＝lvl_out

Difference stored in memory, when this check equations of next iterative computation, will will read this difference, and deduct from list entries.

4. store revised data

The difference of first group of 3 check equations calculated is respectively:

[d ⁰ ₀₀d ⁰ ₁₀d ⁰ ₂₀d ⁰ ₄₀]

[d ⁰ ₀₁d ⁰ ₁₁d ⁰ ₂₁d ⁰ ₄₁]

[d ⁰ ₀₂d ⁰ ₁₂d ⁰ ₂₂d ⁰ ₄₂]

Be input as:

[C ₀₀C ₁₂C ₂₀C ₄₀]

[C ₀₁C ₁₀C ₂₁C ₄₁]

[C ₀₂C ₁₁C ₂₂C ₄₂]

After addition:

${\stackrel{\&OverBar;}{C}}_{00}=C_{00}+{d^0}_{00}{\stackrel{\&OverBar;}{C}}_{12}=C_{12}+{d^0}_{10}{\stackrel{\&OverBar;}{C}}_{20}=C_{20}+{d^0}_{20}{\stackrel{\&OverBar;}{C}}_{40}=C_{40}+{d^0}_{40}$

${\stackrel{\&OverBar;}{C}}_{01}=C_{01}+{d^0}_{01}{\stackrel{\&OverBar;}{C}}_{10}=C_{10}+{d^0}_{11}{\stackrel{\&OverBar;}{C}}_{21}=C_{21}+{d^0}_{21}{\stackrel{\&OverBar;}{C}}_{41}=C_{41}+{d^0}_{41}$

${\stackrel{\&OverBar;}{C}}_{02}=C_{02}+{d^0}_{02}{\stackrel{\&OverBar;}{C}}_{11}=C_{11}+{d^0}_{12}{\stackrel{\&OverBar;}{C}}_{22}=C_{22}+{d^0}_{22}{\stackrel{\&OverBar;}{C}}_{42}=C_{42}+{d^0}_{42}$

According to address when reading and the numbering of memory, the data after calculating are deposited back again

$\left[\begin{array}{c}{\stackrel{\&OverBar;}{C}}_{00}\\ {\stackrel{\&OverBar;}{C}}_{01}\\ {\stackrel{\&OverBar;}{C}}_{02}\end{array}\right]$ Deposit A respectively ⁰, A ¹, A ²address 0;

$\left[\begin{array}{c}{\stackrel{\&OverBar;}{C}}_{12}\\ {\stackrel{\&OverBar;}{C}}_{10}\\ {\stackrel{\&OverBar;}{C}}_{11}\end{array}\right]$ First to be shifted and become $\left[\begin{array}{c}{\stackrel{\&OverBar;}{C}}_{10}\\ {\stackrel{\&OverBar;}{C}}_{11}\\ {\stackrel{\&OverBar;}{C}}_{12}\end{array}\right]$ Afterwards, A is deposited respectively ⁰, A ¹, A ²address 1;

$\left[\begin{array}{c}{\stackrel{\&OverBar;}{C}}_{20}\\ {\stackrel{\&OverBar;}{C}}_{21}\\ {\stackrel{\&OverBar;}{C}}_{22}\end{array}\right]$ Deposit A respectively ⁰, A ¹, A ²address 2;

$\left[\begin{array}{c}{\stackrel{\&OverBar;}{C}}_{40}\\ {\stackrel{\&OverBar;}{C}}_{41}\\ {\stackrel{\&OverBar;}{C}}_{42}\end{array}\right]$ Deposit A respectively ⁰, A ¹, A ²address 4;

Data, stored in rear, complete the calculating of the check equations of a group; Again from step 2, calculate next group check equations, then complete an iteration for one time when all check equations all calculate; Second time iteration, from step 2, all calculates to all check equations and then completes second time iteration for one time.When completing in certain iteration, all check equations are all satisfied; Or iterations is when reaching the higher limit of setting, iteration ends decoding terminates.

Finally, the foregoing is only preferred embodiment of the present invention, all equalizations done according to the claims in the present invention scope change and modify, and all should belong to the covering scope of the claims in the present invention.

Claims (4)

1. a ldpc decoder, is characterized in that, comprising:

The splitter of one point of p, input port connects serial data input;

P dual-ported memory ram A ^q, connect p output port of described splitter respectively, each data block C _ip data C _i1, C _i2, C _i3... C _ipcorresponding to p described dual-ported memory ram A respectively ^q, be specifically all i stored in address, wherein: p > q>=0, p be greater than 1 natural number, i, q are integers;

For storing the second memory (rom H) of check matrix H, (the ram A of dual-ported memory described in control connection ^q); Described check matrix H has packet characteristic; The matrix with packet characteristic is the matrix of a pm × pl, and the matrix of described pm × pl is replaced forming with the non-full zero submatrix of a p × p by the complete zero submatrix replacement and all 1 of all 0 in the basis matrix of m × l with a p × p; Described non-full zero submatrix is the form after the unit matrix of p × p or unit matrix move to right, and each row and column of non-full zero submatrix all only have one 1;

First data shifts unit, input connects described dual-ported memory (ram A ^q), for according to the numbering x except x=-1 of submatrix P in check matrix H to described dual-ported memory (ram A ^q) current address i parallel output data [C _i1, C _i2, C _i3... Ci _p] ring shift left x position, wherein: be numbered the P of 0 ₀be the unit matrix of p × p, be numbered the P of-1 _-1be the full null matrix of p × p, except x=-1, be numbered the P of x _xp ₀often arrange the matrix behind the x position that moves to right ,-1≤x < p, x is integer;

Subtracter, an input connects the first data shifts unit as subtrahend;

P calculator, input connects described subtractor outputs, each calculator according to check equations to respective N number of serial input data block C _ichanging its numbering i is j, called after C _jafter calculate, parallel computation output block difference d _j, N is the number of the data participating in this check equations, and natural number j is less than or equal to natural number N;

For storing the 3rd memory (ram d of the data block difference that the last iterative computation of all calculators goes out _q), input connects p described calculator output, output and connects described subtracter another input as minuend, for the data block difference that each described calculator of parallel output goes out in upper once iterative computation;

Adder, an input connects described calculator output;

P First Input First Output buffer (FIFO ^q), another input that input connects described subtractor outputs, output connects described adder;

Second data shifts unit, input connects described adder output, output connects described dual-ported memory (ram A ^q), replace legacy data on described dual-ported memory correspondence position afterwards for exporting the datacycle x position that moves to right according to the numbering x of submatrix P in check matrix H to adder.

2. ldpc decoder according to claim 1, is characterized in that, p=3, N=4.

3. ldpc decoder according to claim 1, is characterized in that, p=10, N=24.

4. ldpc decoder according to claim 1, is characterized in that, p=20, N=96.