CN113300710B - Conversion circuit and digital-to-analog converter based on resistor voltage division and voltage interpolation - Google Patents
Conversion circuit and digital-to-analog converter based on resistor voltage division and voltage interpolation Download PDFInfo
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- CN113300710B CN113300710B CN202110431546.2A CN202110431546A CN113300710B CN 113300710 B CN113300710 B CN 113300710B CN 202110431546 A CN202110431546 A CN 202110431546A CN 113300710 B CN113300710 B CN 113300710B
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Abstract
The invention provides a conversion circuit and a digital-to-analog converter based on resistor voltage division and voltage interpolation, and relates to the technical field of integrated circuits. The circuit comprises: the resistor voltage dividing unit receives the reference voltage, the row selection signal and the column selection signal and outputs top voltage and bottom voltage to the voltage interpolation unit; the voltage interpolation unit receives the top voltage and the bottom voltage and outputs a result voltage. The resistor voltage dividing unit includes: the state of the switches is controlled by a row selection signal and a column selection signal, and the number of the unit resistors is determined by the number of coarse conversion bits; the voltage interpolation unit includes: the number of the PMOS transistors is determined by the number of the fine conversion bits. The conversion circuit of the invention greatly reduces the number of unit resistors and the number of switches, reduces the physical area occupied by the unit resistors and the switches, reduces the complexity of control logic and has higher practical value on the basis of ensuring high-precision conversion and good monotonicity of the digital-analog converter.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a conversion circuit and a digital-to-analog converter based on resistor voltage division and voltage interpolation.
Background
In the current digital-to-analog converter based on a resistor voltage division structure, which realizes the high-precision digital-to-analog conversion function, a large number of unit resistors and a large number of switches are needed, so that the physical area of the whole digital-to-analog converter is larger, and the control logic is more complex.
For example: taking a 16-bit digital-to-analog converter (Digital to Analog Convertor abbreviated DAC) as an example, if a resistor divider X-Y Selection structure is used, the number of switches and resistors required is large, a total of 65792 switches and 65536 unit resistors are required. Such a number of unit resistors and switches would occupy a larger physical area, and the control logic based on 65792 switches would be complex. Therefore, how to reduce the number of unit resistors and switches to reduce the physical area occupied by the digital-to-analog converter and reduce the complexity of control logic is a urgent problem to be solved on the basis of ensuring high-precision conversion and good monotonicity of the digital-to-analog converter.
Disclosure of Invention
The invention provides a conversion circuit and a digital-to-analog converter based on resistor voltage division and voltage interpolation, and provides a technical scheme which ensures high-precision conversion and good monotonicity of the digital-to-analog converter and reduces the number of unit resistors and switches.
The first aspect of the embodiment of the invention provides a conversion circuit based on resistor voltage division and voltage interpolation, which is used for converting digital quantity into corresponding analog quantity; the conversion circuit includes: a resistor voltage dividing unit and a voltage interpolation unit;
the resistor voltage dividing unit receives the reference voltage, the row selection signal and the column selection signal and outputs the top voltage and the bottom voltage to the voltage interpolation unit;
the voltage interpolation unit receives the top voltage, the bottom voltage and the finely converted digital codes and outputs a result voltage, and the result voltage represents an analog quantity corresponding to the digital quantity;
wherein the resistor divider unit includes: a plurality of unit resistors and a plurality of switches, wherein the states of the plurality of switches are controlled by the row selection signal and the column selection signal, and the number of the plurality of unit resistors is determined by the number of coarse conversion bits;
the top voltage and the bottom voltage characterize the result of the coarse transformation;
the voltage interpolation unit includes: the number of the PMOS tubes is determined by the number of the fine conversion bits.
Optionally, the plurality of switches includes: a row control switch;
the plurality of unit resistors are connected in series and connected in a serpentine manner between the reference voltage and ground potential;
the number of rows and columns formed by connecting the plurality of unit resistors in series in a serpentine manner are determined by the number of bits of the coarse conversion, and each row is provided with a row control switch;
two ends of each unit resistor in the plurality of unit resistors are respectively connected with a switch, one end of a first switch in the two switches is connected with the first end of the unit resistor, the other end of the first switch is connected with the first end of a row control switch where the unit resistor is arranged, and the second end of the row control switch outputs the top voltage to the voltage interpolation unit;
one end of a second switch of the two switches is connected with the second end of the unit resistor, the other end of the second switch is connected with the third end of a row control switch of the unit resistor, and the fourth end of the row control switch outputs the bottom end voltage to the voltage interpolation unit.
Optionally, the higher digit code in the coarse conversion digit generates the row select signal;
the low digit code in the coarse conversion digit generates the column selection signal;
and setting the lowest bit in the Gao Weishu codeword as a flag bit, determining that the row selection signal selects even rows when the flag bit is at a high level, and determining that the row selection signal selects odd rows when the flag bit is at a low level.
Optionally, the voltage interpolation unit includes: a positive input end module, a negative input end module and a folding and outputting module;
the positive input module includes: the plurality of PMOS tubes and the first PMOS tube;
the sources of the PMOS tubes are respectively connected with the source of the first PMOS tube and the source of the PMOS tube in the negative input end module;
the drains of the PMOS tubes are connected with the source of the third NMOS tube M12 in the folding and outputting module;
the grid electrode of each PMOS tube in the plurality of PMOS tubes is connected with two grid switches, the top end voltage is received through one grid switch, and the bottom end voltage is received through the other grid switch;
and the grid electrode of the first PMOS tube receives the bottom end voltage.
Optionally, the negative input terminal module includes: a third PMOS tube;
the source electrode of the third PMOS tube is respectively connected with the source electrodes of the PMOS tubes;
the grid electrode of the third PMOS tube is connected with the drain electrode of the sixth PMOS tube in the folding and outputting module;
and the drain electrode of the third PMOS tube is connected with the source electrode of the second NMOS tube in the folding and outputting module.
Optionally, the folding and outputting module includes: the second PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube, the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the first resistor, the second resistor, the first capacitor and the second capacitor;
the source electrode of the second PMOS tube receives the power supply voltage;
the grid electrode of the second PMOS tube receives bias voltage;
the drain electrode of the second PMOS tube is respectively connected with the source electrode of the third PMOS tube and the source electrodes of the plurality of PMOS tubes;
the source electrode of the fourth PMOS tube, the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube all receive the power supply voltage;
the grid electrode of the fourth PMOS tube is respectively connected with the grid electrode of the fifth PMOS tube, the drain electrode of the seventh PMOS tube and the drain electrode of the second NMOS tube;
the drain electrode of the fourth PMOS tube is connected with the source electrode of the seventh PMOS tube;
the drain electrode of the fifth PMOS tube is connected with the source electrode of the eighth PMOS tube;
the grid electrode of the sixth PMOS tube is respectively connected with the drain electrode of the eighth PMOS tube, the source electrode of the ninth PMOS tube, the drain electrode of the first NMOS tube and the first end of the first resistor;
the drain electrode of the sixth PMOS tube is respectively connected with the grid electrode of the third PMOS tube, the second end of the first capacitor, the second end of the second capacitor and the drain electrode of the sixth NMOS tube;
the grid electrode of the seventh PMOS tube and the grid electrode of the eighth PMOS tube both receive the bias voltage;
the grid electrode of the ninth PMOS tube receives the bias voltage;
the drain electrode of the ninth PMOS tube is respectively connected with the source electrode of the first NMOS tube, the drain electrode of the third NMOS tube, the first end of the second resistor and the grid electrode of the sixth NMOS tube;
the grid electrode of the first NMOS tube receives the bias voltage;
the grid electrode of the second NMOS tube and the grid electrode of the third NMOS tube both receive the bias voltage;
the source electrode of the second NMOS tube is respectively connected with the drain electrode of the third PMOS tube and the drain electrode of the fourth NMOS tube;
the source electrode of the third NMOS tube is respectively connected with the drain electrodes of the PMOS tubes, the drain electrode of the first PMOS tube and the drain electrode of the fifth NMOS tube;
the grid electrode of the fourth NMOS tube and the grid electrode of the fifth NMOS tube both receive the bias voltage;
the source electrode of the fourth NMOS tube, the source electrode of the fifth NMOS tube and the source electrode of the sixth NMOS tube are all grounded;
the second end of the first resistor is connected with the first end of the first capacitor;
the second end of the second resistor is connected with the first end of the second capacitor.
Optionally, the aspect ratio of the third PMOS transistor is determined by the number of bits of the fine transition.
Optionally, two gate switches connected to the gate of each of the plurality of PMOS transistors are controlled by the digital code in the fine conversion bit number;
for one of the plurality of PMOS transistors: the PMOS tube is assumed to correspond to the digital code of the lowest bit in the fine conversion digits;
a first gate switch of the two gate switches connected with the PMOS tube is closed when the lowest digital code in the fine conversion bit number is 1, and a second gate switch of the two gate switches connected with the PMOS tube is opened when the lowest digital code in the fine conversion bit number is 1, and the PMOS tube receives the top voltage;
and a first grid switch of the two grid switches connected with the PMOS tube is opened when the lowest digital code in the fine conversion bit number is 0, and a second grid switch of the two grid switches connected with the PMOS tube is closed when the lowest digital code in the fine conversion bit number is 0, so that the PMOS tube receives the bottom voltage.
Optionally, the aspect ratio of the PMOS transistors is determined by the number of bits of the fine conversion;
for one of the plurality of PMOS transistors: assuming that the PMOS tube corresponds to the digital code of the lowest bit in the fine conversion bits, the width-to-length ratio of the PMOS tube is 1W/L;
for one of the plurality of PMOS transistors: assuming that the PMOS tube corresponds to the digit of the second lower bit in the fine conversion digit, the width-to-length ratio of the PMOS tube is 2W/L;
for one of the plurality of PMOS transistors: and assuming that the PMOS tube corresponds to the digital code with one bit higher than the next lower bit in the fine conversion bit number, the width-to-length ratio of the PMOS tube is 4W/L.
A second aspect of an embodiment of the present invention provides a digital-to-analog converter, the digital-to-analog converter comprising: a conversion circuit as claimed in any one of the first aspects.
The conversion circuit based on resistance voltage division and voltage interpolation is used for converting digital quantity into corresponding analog quantity; the resistor voltage dividing unit receives the reference voltage, the row selection signal and the column selection signal, and outputs top voltage and bottom voltage to the voltage interpolation unit, wherein the top voltage and the bottom voltage represent the rough conversion result; the resistor voltage dividing unit specifically comprises: the state of the plurality of switches is controlled by the row selection signal and the column selection signal, and the number of the plurality of unit resistors is determined by the number of coarse conversion bits. That is, in the conversion circuit of the present invention, the number of unit resistors is not determined by the number of bits of the entire digital quantity, but by the number of bits of coarse conversion. For example: in a 16-bit DAC, the number of unit resistors is currently determined by 16 bits, and thus the unit powerThe number of resistors is 2 16 =65536. Assuming that the number of coarse conversion bits is 10 bits, the number of unit resistors is only 2 10 =1024. This clearly reduces the number of unit resistors, while the number of switches is determined by the unit resistors, the smaller the number of unit resistors naturally the smaller the number of switches, which clearly reduces the physical area occupied by the unit resistors and switches, and the natural control logic becomes simple due to the reduced number of switches.
Since the coarse conversion converts only part of the bits, the rest of the bits are converted by the fine conversion, and the fine conversion function is realized by the voltage interpolation unit. The voltage difference unit receives the top voltage and the bottom voltage, outputs a result voltage, and the result voltage represents an analog quantity corresponding to the digital quantity; the voltage interpolation unit includes: the number of the PMOS tubes is determined by the number of the fine conversion bits. That is, how many PMOS transistors are for the fine conversion bit number, for example: in a 16-bit DAC, assuming that the number of coarse conversion bits is 10 bits, then the number of fine conversion bits is 6 bits, then 6 PMOS transistors are required. The digital-to-analog conversion function of the digital-to-analog converter is realized through the structure, the number of unit resistors and switches is greatly reduced on the basis of ensuring high-precision conversion and good monotonicity of the digital-to-analog converter, the occupied physical area is further reduced, and the control logic complexity is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a conversion circuit based on resistor division and voltage interpolation according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a preferred resistive divider cell in an embodiment of the present invention;
fig. 3 is a schematic diagram of a preferred voltage interpolation unit in an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, a schematic diagram of a conversion circuit based on resistor voltage division and voltage interpolation according to an embodiment of the present invention is shown, where the conversion circuit according to the embodiment of the present invention is used for converting digital quantities into corresponding analog quantities, that is, implementing a digital-to-analog conversion function. The conversion circuit includes: and the resistor voltage dividing unit and the voltage interpolation unit. The resistor voltage dividing unit receives the reference voltage V REF The column selection signal and the row selection signal output a top voltage and a bottom voltage to the voltage interpolation unit, and the top voltage and the bottom voltage represent the rough conversion result. The voltage interpolation unit receives the top voltage, the bottom voltage and the finely converted digital code and outputs a result voltage V out The result voltage V out I.e. the analog quantity corresponding to the characterizing digital quantity.
The resistor voltage division unit realizes coarse conversion, the voltage interpolation unit realizes fine conversion, and the coarse conversion bit number is assumed to be M bit, and the fine conversion bit number is assumed to be N bit. The resistor voltage dividing unit includes: the state of the plurality of switches is controlled by the row selection signal and the column selection signal, and the number of the plurality of unit resistors is determined by the number of coarse conversion bits. The voltage interpolation unit includes: the number of the PMOS tubes is determined by the number of the fine conversion bits. Therefore, the resistor voltage division unit receives the M bit digital code, the specific number of the unit resistors is determined by the M bit digital code, and meanwhile, the specific values of the row selection signal and the column selection signal are determined based on the M bit digital code. The voltage interpolation unit receives the N bit digital codes, and the specific number of the PMOS tubes is determined by the N bit digital codes.
The digital-to-analog conversion function of the digital-to-analog converter is realized through the structure of the conversion circuit, the number of unit resistors and switches is greatly reduced on the basis of ensuring high-precision conversion and good monotonicity of the digital-to-analog converter, the occupied physical area is further reduced, and the control logic complexity is reduced.
The conversion circuit according to the embodiment of the present invention will be described below by taking a 16-bit DAC as an example, and the other-bit DAC may be referred to as a 16-bit DAC, and is not limited to this. The number of bits for coarse conversion is assumed to be 10 bits and the number of bits for fine conversion is assumed to be 6 bits. Referring to fig. 2, a schematic diagram of a preferred resistor divider block according to an embodiment of the present invention is shown, where fig. 2 includes: a plurality of resistors, a plurality of switches, a high bit decoder, and a low bit decoder.
Since the number of bits for performing the rough conversion is 10 bits, the number of unit resistances is 2 10 The resistor divider unit adopts an X-Y Selection structure, 1024 unit resistors are distributed on 32 row lines, which are serially connected and then connected in serpentine form to a reference voltage (V in fig. 2 REF ) And a ground potential (GND in fig. 2). For simplicity of illustration in FIG. 2, the first, second, thirty-first, and thirty-second rows are illustratively shown, respectively identified as X 1 、X 2 、X 31 X is as follows 32 Each row is provided with a row selection switch, shown as S in FIG. 2 32 Identify the thirty-two rows X 32 The remaining thirty rows are similar and are not separately identified.
Also exemplary are shown a first column, a second column, a thirty-first column, and a thirty-second column, respectively identified as Y 1 、Y 2 、Y 31 Y is as follows 32 . Each of 1024 unit resistors has two ends connected to a switch, a first switch of the two switches has one end connected to the first end of the unit resistor and the other end connected to the first end of a row control switch of the row in which the unit resistor is located, and a second end of the row control switch outputs a top voltage (V in fig. 2 TOP ) To a voltage interpolation unit; one end of a second switch of the two switches is connected with the second end of the unit resistor, and the other end is connected with the row control of the row where the unit resistor is arrangedThe third terminal of the switch is connected, and the fourth terminal of the row control switch outputs the bottom voltage (V in FIG. 2 BOT ) To the voltage interpolation unit.
Specifically, one of the symbols in FIG. 2 is designated as R 32 For example, the unit resistance of (2) and the rest of the unit resistance and the unit resistance R 32 The resistor connection modes are the same, and the unit resistor R 32 Line X of the third twelve of the present behaviors 32 The row selection switch is S 32 . Unit resistance R 32 Two ends of the resistor are respectively connected with the switch S 1 、S 2 Connected with a first switch S 1 Unit resistance R of one end and of (2) 32 One end of the resistor is connected with a first switch S 1 The other end of the switch is S with the row selection switch 32 Is connected with the first end 1 of the row selection switch S 32 The second terminal 2 and the row selection switch are S 32 Is matched with the first end 1 of the circuit board, so that the row selection switch is S 32 Can output a top voltage V at the second terminal 2 of (2) TOP To the voltage interpolation unit. Second switch S 2 Unit resistance R of one end and of (2) 32 The other end of the resistor is connected with a second switch S 2 The other end of the switch is S with the row selection switch 32 Is connected with the third terminal 3 of the row selection switch S 32 The fourth terminal 4 and the row selection switch are S 32 The third terminal 3 of (2) is used in combination, so the row selection switch is S 32 Can output the bottom voltage V at the fourth terminal 4 of (2) BOT To the voltage interpolation unit.
Depending on the nature of the X-Y Selection structure, the row select signal and column select signal need to be determined by a 10-bit digital code. Setting a high digital code in the coarse conversion bit number to generate a row selection signal; the low digit code in the coarse conversion digit generates a column selection signal; and setting the lowest bit in the high-bit digital code as a flag bit, determining that the row selection signal selects even rows when the flag bit is at a high level, and determining that the row selection signal selects odd rows when the flag bit is at a low level.
Specifically, since the coarse conversion is 10 bits: d (D) 15 ～D 6 Thus D is to 10 ～D 6 D is taken as the lower bit of 10 bits 15 ～D 11 D as the high order of the 10 bits 15 ～D 11 The value of (2) is input to the high-order decoder, which is based onThe value selects a row line D 10 ～D 6 The value of (2) is input to the low order decoder, which selects the column line based on the value. In this way, given the row selection signal X and the column selection signal Y, the unit resistance is selected, and the top voltage V is uniquely determined TOP And bottom voltage V BOT Therefore, the following two formulas can be obtained:
therefore, the following formula can be deduced:
since the high-order decoder generates the row selection control signal to select one of the 32 rows, the low-order decoder generates the column selection control signal to select one of the 32 unit resistors in that row, since the first tap of the odd-order row and the last tap of the even-order row determine the first voltage of that row, the low-order decoder has to exchange the direction selected by the low-order decoder depending on whether the high-order decoder points to the odd-order row or the even-order row, so the design makes use of D 11 If D as the flag bit of the low-order decoder 11 Is high, indicating that the high decoder selects even rows, if D 11 Is low, indicating that the high decoder selected the odd row.
Through the resistor voltage dividing unit, 10-bit coarse conversion is realized, and a coarse conversion result is generated: top voltage V TOP And bottom voltage V BOT After which the top voltage V TOP And bottom voltage V BOT And outputting to a voltage interpolation unit.
The voltage interpolation unit in the embodiment of the invention comprises: positive input end module, negative input end module and control method thereofA folding and outputting module; the positive input terminal module comprises: a plurality of PMOS tubes and a first PMOS tube; the negative input terminal module includes: the second PMOS tube and the third PMOS tube; the folding and outputting module includes: the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the first resistor, the second resistor, the first capacitor and the second capacitor. Referring to fig. 3, a schematic diagram of a preferred voltage interpolation unit according to an embodiment of the present invention is shown, where fig. 3 includes: a plurality of PMOS transistors, indicated by the dashed box 10 in fig. 3. First PMOS tube M 1 A second PMOS tube M 2 Third PMOS tube M 3 Fourth PMOS tube M 4 Fifth PMOS tube M 5 Sixth PMOS tube M 6 Seventh PMOS tube M 7 Eighth PMOS tube M 8 Ninth PMOS tube M 9 First NMOS tube M 10 Second NMOS tube M 11 Third NMOS tube M 12 Fourth NMOS tube M 13 Fifth NMOS tube M 14 Sixth NMOS tube M 15 A first resistor R 1 A second resistor R 2 First capacitor C 1 A second capacitor C 2 。
In FIG. 3, the multiple PMOS tubes in the virtual frame 10 are connected in parallel, and their sources are all connected to the first PMOS tube M 1 Source electrode of the second PMOS tube M 2 The drain electrodes are respectively connected; the drains of the PMOS tubes are all connected with the third NMOS tube M 12 Is connected with the source electrode of the transistor; the grid electrode of each PMOS tube in the plurality of PMOS tubes is connected with two grid switches, and the top voltage V is received through one grid switch TOP Receiving the bottom voltage V through another gate switch BOT The method comprises the steps of carrying out a first treatment on the surface of the Meanwhile, the first PMOS tube M 1 The gate of (2) receives the bottom voltage V BOT 。
Specifically, since the number of bits for performing fine conversion is 6 bits, namely: d (D) 5 ～D 0 Therefore, 6 PMOS transistors should be included in the virtual frame 10, and only 3 PMOS transistors are shown for illustration simplicity. The grid electrode of each PMOS tube is provided with two grid electrode switches which are controlled by digital codes in the fine conversion bit number; taking the leftmost PMOS transistor in the virtual frame 10 in fig. 3 as an example: the method comprisesMinimum bit D in the corresponding thin conversion bit number of PMOS tube 0 Digital codes of (2); a first gate switch of two gate switches connected with the PMOS tube, which has the lowest bit D in the fine conversion bit number 0 When the digital code of (2) is 1, closing; meanwhile, the second gate switch of the two gate switches connected with the PMOS tube is used for finely converting the digital code D of the lowest bit in the digits 0 When the voltage is 1, the PMOS tube is disconnected and receives the top voltage V TOP . In the figure D 0 Representing the controlled condition of the first gate switch, i.e. D 0 When=1, the first gate switch is closed, and D 0 When=1, it is notThe second gate switch is thus open.
Similarly, the first gate switch of the two gate switches connected with the PMOS tube has the lowest bit D in the thin conversion bit number 0 When the digital code of (2) is 0, the second gate switch of the two gate switches connected with the PMOS tube is disconnected, and the lowest bit D in the fine conversion bit number 0 Is closed when the digital code of (2) is 0, and the PMOS tube receives the bottom voltage V BOT 。
In the embodiment of the present invention, the aspect ratio of the plurality of PMOS transistors is determined by the number of bits of the fine conversion, taking the leftmost PMOS transistor in the virtual frame 10 of fig. 3 as an example: the PMOS tube corresponds to the lowest bit D in the fine conversion bit number 0 Therefore, the width-to-length ratio is W/L, and the thin conversion bit number is corresponding to the secondary low bit D by the PMOS tube next to the PMOS tube on the left 1 Therefore, the width-to-length ratio is 2W/L, and so on, the rightmost PMOS tube in the virtual frame 10 corresponds to the highest bit D in the thin-conversion bit number 5 Therefore, the width-to-length ratio is 32W/L.
The dummy frame 10 and the first PMOS transistor M 1 Form a positive input end module, a third PMOS tube M in the negative input end module 3 The structure of (2) is as follows:
third PMOS tube M 3 The source electrodes of the PMOS tubes in the virtual frame 10 are respectively connected with the source electrodes of the PMOS tubes; third PMOS tube M 3 The grid electrode of the sixth PMOS tube M6 is connected with the drain electrode of the sixth PMOS tube M; third PMOS tube M 3 Drain electrode of (d) and second NMOS transistor M 11 Is connected to the source of the (c). Wherein, the firstThree PMOS tubes M 3 The aspect ratio of (2) is determined by the number of bits of the fine conversion, since the number of bits of the fine conversion is 6,2 6 =64, thus the third PMOS transistor M 3 The aspect ratio of (2) is 64W/L.
The structure of the folding and outputting module is as follows: second PMOS tube M 2 The source of (2) receives a supply voltage VDD; second PMOS tube M 2 Is subject to a bias voltage V b1 The method comprises the steps of carrying out a first treatment on the surface of the Second PMOS tube M 2 Drain electrode of (C) and third PMOS tube M 3 The source electrodes of the PMOS tubes in the virtual frame 10 are respectively connected with the source electrodes of the PMOS tubes; fourth PMOS tube M 4 Source electrode of (V) PMOS tube M 5 Source electrode of (d) and sixth PMOS tube M 6 The sources of which all receive the power supply voltage; fourth PMOS tube M 4 Gate of (c) and fifth PMOS tube M 5 Gate electrode of (C), seventh PMOS tube M 7 Drain electrode of (2), second NMOS tube M 11 The drains of the two are respectively connected; fourth PMOS tube M 4 Drain electrode of (C) and seventh PMOS tube M 7 Is connected with the source electrode of the transistor; fifth PMOS tube M 5 Drain electrode of (c) and eighth PMOS tube M 8 Is connected with the source electrode of the transistor; sixth PMOS tube M 6 Gate and eighth PMOS tube M 8 Drain electrode of (C) and ninth PMOS tube M 9 Source of (a) first NMOS transistor M 10 Drain electrode of (a), a first resistor R 1 Are connected respectively at the first ends of the first and second ends.
Sixth PMOS tube M 6 Drain electrode of (C) and third PMOS tube M 3 Gate of (C), first capacitor C 1 A second end of (C), a second capacitor C 2 A second end of (d) and a sixth NMOS transistor M 15 The drains of the two are respectively connected; seventh PMOS tube M 7 Gate electrode of (v), eighth PMOS tube M 8 The gates of (a) all receive a bias voltage V b2 The method comprises the steps of carrying out a first treatment on the surface of the Ninth PMOS tube M 9 Is subject to a bias voltage V bp The method comprises the steps of carrying out a first treatment on the surface of the Ninth PMOS tube M 9 Drain electrode of (d) and first NMOS transistor M 10 Source electrode of the third NMOS tube M 12 Drain electrode of (2), second resistance R 2 Is connected to the first end of the sixth NMOS transistor M 15 The grid electrodes of the two are respectively connected; first NMOS tube M 10 Is subject to a bias voltage V bn The method comprises the steps of carrying out a first treatment on the surface of the Second NMOS tube M 11 Gate of (d), third NMOS transistor M 12 The gates of (a) all receive a bias voltage V b3 The method comprises the steps of carrying out a first treatment on the surface of the Second NMOS tube M 11 Source electrode of (C) and third PMOS tube M 3 Drain electrode of (d), fourth NMOS tube M 13 The drains of which are respectively connected.
Third NMOS tube M 12 The source electrode of the (2) and the drain electrodes of the plurality of PMOS tubes in the virtual frame 10, the first PMOS tube M 1 Drain electrode of (d) and fifth NMOS transistor M 14 The drains of the two are respectively connected; fourth NMOS tube M 13 Gate of (v) and fifth NMOS transistor M 14 The gates of (a) all receive a bias voltage V b4 The method comprises the steps of carrying out a first treatment on the surface of the Fourth NMOS tube M 13 Source electrode of (V) NMOS transistor M 14 Source electrode of (d), sixth NMOS transistor M 15 The sources of the (a) are all grounded GND; first resistor R 1 And the second end of the capacitor (C) 1 Is connected to the first end of the housing; second resistor R 2 And a second capacitor C 2 Is connected to the first end of the housing. First capacitor C 1 A second end of (C), a second capacitor C 2 A second end of the sixth PMOS tube M 6 Drain electrode of (d) and sixth NMOS transistor M 15 Is connected together to output the resulting voltage V out 。
According to the current I in the positive input terminal module p Should be equal to the current I in the negative input module n The principle of equal values of (a) can be given by:
wherein,μ p cox is the capacitance of the gate oxide layer per unit area, V THP Is the threshold voltage of the PMOS tube, V pi (i=1, 2,3,4,5, 6) is the gate terminal voltage of the plurality of pmos transistors.
The following formula can be obtained:
the method is simplified as follows:
V BoT +V p1 +2*V p2 +…32*V p6 ＝64*V out
wherein g m ＝2*k*(V x -V BOT -|V THP |)。
From this the following formula is calculated:
thus, the function of fine conversion is completed, namely, based on the combined action of the resistor voltage dividing unit and the voltage interpolation unit shown in the above figures 2 and 3, taking 10-bit coarse conversion and 6-bit fine conversion as examples, the digital-to-analog conversion of the 16-bit DAC is realized.
In summary, in the conversion circuit according to the embodiment of the present invention, the resistor voltage dividing unit receives the reference voltage, and outputs the row selection signal and the column selection signal generated based on the digital code of the coarse conversion bit number, and the top voltage and the bottom voltage representing the coarse conversion result are output to the voltage interpolation unit. The voltage difference unit receives the top voltage and the bottom voltage, and utilizes the positive input end module, the negative input end module and the folding and outputting module to realize fine conversion and output the result voltage representing the analog quantity corresponding to the digital quantity.
With the above structure, the number of unit resistors is not determined by the number of bits of the entire digital quantity, but by the number of bits of coarse conversion. The number of unit resistors is greatly reduced, the number of the switches is determined by the unit resistors, the smaller the number of the unit resistors is, the physical area occupied by the unit resistors and the switches is obviously greatly reduced, and the natural control logic is simplified due to the reduction of the number of the switches. On the basis of ensuring high-precision conversion and good monotonicity of the digital-to-analog converter, the number of unit resistors and switches is greatly reduced, the occupied physical area is further reduced, the control logic complexity is reduced, and the conversion circuit has high practical value.
Based on the above conversion circuit, the embodiment of the present invention further provides a digital-to-analog converter, where the digital-to-analog converter includes: a conversion circuit as claimed in any preceding claim.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.
Claims (8)
1. The conversion circuit is used for converting digital quantity into corresponding analog quantity; the conversion circuit includes: a resistor voltage dividing unit and a voltage interpolation unit;
the resistor voltage dividing unit receives the reference voltage, the row selection signal and the column selection signal and outputs the top voltage and the bottom voltage to the voltage interpolation unit;
the voltage interpolation unit receives the top voltage, the bottom voltage and the digital codes of the fine conversion digits and outputs a result voltage, and the result voltage represents an analog quantity corresponding to the digital quantity;
wherein, the resistance voltage division unit is used for realizing coarse conversion, and it includes: a plurality of unit resistors and a plurality of switches, wherein the states of the plurality of switches are controlled by the row selection signal and the column selection signal, and the number of the plurality of unit resistors is determined by the number of coarse conversion bits;
the top voltage and the bottom voltage characterize the result of the coarse transformation;
the voltage interpolation unit is used for realizing fine conversion, and comprises: the number of the PMOS tubes is determined by the number of the fine conversion bits;
the plurality of switches includes: a row control switch;
the plurality of unit resistors are connected in series and connected in a serpentine manner between the reference voltage and ground potential;
the number of rows and columns formed by connecting the plurality of unit resistors in series in a serpentine manner are determined by the number of bits of the coarse conversion, and each row is provided with a row control switch;
two ends of each unit resistor in the plurality of unit resistors are respectively connected with a switch, one end of a first switch in the two switches is connected with the first end of the unit resistor, the other end of the first switch is connected with the first end of a row control switch where the unit resistor is arranged, and the second end of the row control switch outputs the top voltage to the voltage interpolation unit;
one end of a second switch of the two switches is connected with the second end of the unit resistor, the other end of the second switch is connected with the third end of a row control switch of the unit resistor, and the fourth end of the row control switch outputs the bottom end voltage to the voltage interpolation unit;
the upper digit code in the coarse conversion digit generates the row selection signal;
the low digit code in the coarse conversion digit generates the column selection signal;
and setting the lowest bit in the Gao Weishu codeword as a flag bit, determining that the row selection signal selects even rows when the flag bit is at a high level, and determining that the row selection signal selects odd rows when the flag bit is at a low level.
2. The conversion circuit according to claim 1, wherein the voltage interpolation unit includes: a positive input end module, a negative input end module and a folding and outputting module;
the positive input module includes: the plurality of PMOS tubes and the first PMOS tube;
the sources of the PMOS tubes are respectively connected with the source of the first PMOS tube and the source of the PMOS tube in the negative input end module;
the drains of the PMOS tubes are connected with the source of the third NMOS tube in the folding and outputting module;
the grid electrode of each PMOS tube in the plurality of PMOS tubes is connected with two grid switches, the top end voltage is received through one grid switch, and the bottom end voltage is received through the other grid switch;
and the grid electrode of the first PMOS tube receives the bottom end voltage.
3. The conversion circuit of claim 2, wherein the negative input terminal module comprises: a third PMOS tube;
the source electrode of the third PMOS tube is respectively connected with the source electrodes of the PMOS tubes;
the grid electrode of the third PMOS tube is connected with the drain electrode of the sixth PMOS tube in the folding and outputting module;
and the drain electrode of the third PMOS tube is connected with the source electrode of the second NMOS tube in the folding and outputting module.
4. A conversion circuit according to claim 3, wherein the folding and outputting module comprises: the second PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube, the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the first resistor, the second resistor, the first capacitor and the second capacitor;
the source electrode of the second PMOS tube receives the power supply voltage;
the grid electrode of the second PMOS tube receives bias voltage;
the drain electrode of the second PMOS tube is respectively connected with the source electrode of the third PMOS tube and the source electrodes of the plurality of PMOS tubes;
the source electrode of the fourth PMOS tube, the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube all receive the power supply voltage;
the grid electrode of the fourth PMOS tube is respectively connected with the grid electrode of the fifth PMOS tube, the drain electrode of the seventh PMOS tube and the drain electrode of the second NMOS tube;
the drain electrode of the fourth PMOS tube is connected with the source electrode of the seventh PMOS tube;
the drain electrode of the fifth PMOS tube is connected with the source electrode of the eighth PMOS tube;
the grid electrode of the sixth PMOS tube is respectively connected with the drain electrode of the eighth PMOS tube, the source electrode of the ninth PMOS tube, the drain electrode of the first NMOS tube and the first end of the first resistor;
the drain electrode of the sixth PMOS tube is respectively connected with the grid electrode of the third PMOS tube, the second end of the first capacitor, the second end of the second capacitor and the drain electrode of the sixth NMOS tube;
the grid electrode of the seventh PMOS tube and the grid electrode of the eighth PMOS tube both receive the bias voltage;
the grid electrode of the ninth PMOS tube receives the bias voltage;
the drain electrode of the ninth PMOS tube is respectively connected with the source electrode of the first NMOS tube, the drain electrode of the third NMOS tube, the first end of the second resistor and the grid electrode of the sixth NMOS tube;
the grid electrode of the first NMOS tube receives the bias voltage;
the grid electrode of the second NMOS tube and the grid electrode of the third NMOS tube both receive the bias voltage;
the source electrode of the second NMOS tube is respectively connected with the drain electrode of the third PMOS tube and the drain electrode of the fourth NMOS tube;
the source electrode of the third NMOS tube is respectively connected with the drain electrodes of the PMOS tubes, the drain electrode of the first PMOS tube and the drain electrode of the fifth NMOS tube;
the grid electrode of the fourth NMOS tube and the grid electrode of the fifth NMOS tube both receive the bias voltage;
the source electrode of the fourth NMOS tube, the source electrode of the fifth NMOS tube and the source electrode of the sixth NMOS tube are all grounded;
the second end of the first resistor is connected with the first end of the first capacitor;
the second end of the second resistor is connected with the first end of the second capacitor.
5. The conversion circuit according to claim 3, wherein the aspect ratio of the third PMOS transistor is determined by the number of bits of the fine conversion.
6. The conversion circuit of claim 2, wherein two gate switches connected to the gate of each of the plurality of PMOS transistors are controlled by the digital code of the fine conversion bit number;
for any one of the plurality of PMOS transistors: a first grid switch of the two grid switches connected with the PMOS tube is closed when the digital code of the thin conversion digit which is controlled to be closed or opened is 1, and a second grid switch of the two grid switches connected with the PMOS tube is opened when the digital code of the thin conversion digit which is controlled to be closed or opened is 1, and the PMOS tube receives the top voltage;
and a first grid switch of the two grid switches connected with the PMOS tube is opened when the digital code of the thin conversion digit which is controlled to be closed or opened is 0, and a second grid switch of the two grid switches connected with the PMOS tube is closed when the digital code of the thin conversion digit which is controlled to be closed or opened is 0, and the PMOS tube receives the bottom voltage.
7. The conversion circuit according to claim 2, wherein the aspect ratio of the plurality of PMOS transistors is determined by the number of bits of the fine conversion;
for one of the plurality of PMOS transistors: assuming that the PMOS tube corresponds to the digital code of the lowest bit in the fine conversion bits, the width-to-length ratio of the PMOS tube is 1W/L;
for one of the plurality of PMOS transistors: assuming that the PMOS tube corresponds to the digit of the second lower bit in the fine conversion digit, the width-to-length ratio of the PMOS tube is 2W/L;
for one of the plurality of PMOS transistors: and assuming that the PMOS tube corresponds to the digital code with one bit higher than the next lower bit in the fine conversion bit number, the width-to-length ratio of the PMOS tube is 4W/L.
8. A digital-to-analog converter, the digital-to-analog converter comprising: a conversion circuit as claimed in any one of claims 1 to 7.
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