CN113300710A

CN113300710A - Conversion circuit and digital-to-analog converter based on resistance voltage division and voltage interpolation

Info

Publication number: CN113300710A
Application number: CN202110431546.2A
Authority: CN
Inventors: 石迎; 鲁文高; 张雅聪; 安泊伟; 祝润坤; 陈中建
Original assignee: Peking University
Current assignee: Peking University
Priority date: 2021-04-21
Filing date: 2021-04-21
Publication date: 2021-08-24
Anticipated expiration: 2041-04-21
Also published as: CN113300710B

Abstract

The invention provides a conversion circuit and a digital-to-analog converter based on resistance voltage division and voltage interpolation, and relates to the technical field of integrated circuits. The circuit comprises: the resistance voltage dividing unit receives the reference voltage, the row selection signal and the column selection signal and outputs a top voltage and a bottom voltage to the voltage interpolation unit; the voltage interpolation unit receives the top voltage and the bottom voltage and outputs a result voltage. The resistance voltage-dividing unit includes: the state of the switch is controlled by a row selection signal and a column selection signal, and the number of the unit resistors is determined by coarse conversion bits; the voltage interpolation unit includes: and a plurality of PMOS tubes, the number of which is determined by the number of the fine conversion bits. The conversion circuit greatly reduces the number of unit resistors and the number of switches, reduces the physical area occupied by the unit resistors and the switches, reduces the complexity of control logic and has higher practical value on the basis of ensuring high-precision conversion and good monotonicity of the digital-to-analog converter.

Description

Conversion circuit and digital-to-analog converter based on resistance voltage division and voltage interpolation

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a conversion circuit and a digital-to-analog converter based on resistance voltage division and voltage interpolation.

Background

At present, in a digital-to-analog converter which is based on a resistance voltage division structure and realizes a high-precision digital-to-analog conversion function, because a large number of unit resistors and a large number of switches are needed, the physical area of the whole digital-to-analog converter is large, and the control logic is complex.

For example: taking a 16-bit Digital-to-Analog converter (DAC for short), if the X-Y Selection structure is divided by resistors, the number of switches and resistors is large, and 65792 switches and 65536 unit resistors are required. Such a number of unit resistors and switches occupies a large physical area, and the control logic based on 65792 switches is also complicated. Therefore, how to reduce the number of unit resistors and switches to reduce the physical area occupied by the digital-to-analog converter and reduce the complexity of control logic on the basis of ensuring high-precision conversion and good monotonicity of the digital-to-analog converter is a problem to be solved urgently.

Disclosure of Invention

The invention provides a conversion circuit and a digital-to-analog converter based on resistance voltage division and voltage interpolation, and provides a technical scheme which not only ensures high-precision conversion and good monotonicity of the digital-to-analog converter, but also reduces the number of unit resistors and switches.

The first aspect of the embodiments of the present invention provides a conversion circuit based on resistance voltage division and voltage interpolation, where the conversion circuit is configured to convert a digital quantity into a corresponding analog quantity; the conversion circuit includes: a resistance voltage division unit and a voltage interpolation unit;

the resistance voltage dividing unit receives a reference voltage, a row selection signal and a column selection signal and outputs a top voltage and a bottom voltage to the voltage interpolation unit;

the voltage interpolation unit receives the top end voltage, the bottom end voltage and the finely converted digital code and outputs a result voltage, and the result voltage represents an analog quantity corresponding to the digital quantity;

wherein, the resistance voltage division unit includes: the state of the switches is controlled by the row selection signal and the column selection signal, and the number of the unit resistors is determined by the number of coarse conversion bits;

the top and bottom voltages characterizing the result of the coarse conversion;

the voltage interpolation unit includes: and the number of the PMOS tubes is determined by the number of the fine conversion bits.

Optionally, the plurality of switches comprises: a row control switch;

the plurality of unit resistors are connected in series to be connected in a serpentine shape between the reference voltage and a ground potential;

the number of rows and the number of columns formed by the unit resistors which are connected in series in a snake shape are determined by the number of bits of the coarse conversion, and each row is provided with a row control switch;

two ends of each unit resistor in the plurality of unit resistors are respectively connected with a switch, one end of a first switch in the two switches is connected with the first end of the unit resistor, the other end of the first switch is connected with the first end of a row control switch of a row where the unit resistor is located, and the second end of the row control switch outputs the top voltage to the voltage interpolation unit;

one end of a second switch of the two switches is connected with the second end of the unit resistor, the other end of the second switch is connected with the third end of the row control switch of the unit resistor, and the fourth end of the row control switch outputs the bottom voltage to the voltage interpolation unit.

Optionally, the row selection signal is generated by a high-order digital code in the coarse conversion bit number;

generating the column selection signal by a low-order digit code in the coarse conversion digit;

and setting the lowest bit in the high-order digital code as a flag bit, determining that the even-numbered lines are selected by the line selection signal when the flag bit is at a high level, and determining that the odd-numbered lines are selected by the line selection signal when the flag bit is at a low level.

Optionally, the voltage interpolation unit includes: the input end module comprises a positive input end module, a negative input end module and a folding and output module;

the positive input module comprises: the PMOS tubes and the first PMOS tube;

the PMOS tubes are connected in parallel, and the source electrodes of the PMOS tubes are respectively connected with the source electrode of the first PMOS tube and the source electrode of the PMOS tube in the negative input end module;

the drain electrodes of the PMOS tubes are connected with the source electrode of a third NMOS tube M12 in the folding and output module;

the grid electrode of each PMOS tube in the PMOS tubes is connected with two grid electrode switches, the top end voltage is received through one grid electrode switch, and the bottom end voltage is received through the other grid electrode switch;

and the grid electrode of the first PMOS tube receives the bottom voltage.

Optionally, the negative input module includes: a third PMOS tube;

the source electrode of the third PMOS tube is respectively connected with the source electrodes of the PMOS tubes;

the grid electrode of the third PMOS tube is connected with the drain electrode of a sixth PMOS tube in the folding and output module;

and the drain electrode of the third PMOS tube is connected with the source electrode of a second NMOS tube in the folding and output module.

Optionally, the folding and outputting module includes: a second PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first resistor, a second resistor, a first capacitor and a second capacitor;

the source electrode of the second PMOS tube receives a power supply voltage;

the grid electrode of the second PMOS tube receives bias voltage;

the drain electrode of the second PMOS tube is respectively connected with the source electrode of the third PMOS tube and the source electrodes of the PMOS tubes;

the source electrode of the fourth PMOS tube, the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube receive the power supply voltage;

the grid electrode of the fourth PMOS tube is respectively connected with the grid electrode of the fifth PMOS tube, the drain electrode of the seventh PMOS tube and the drain electrode of the second NMOS tube;

the drain electrode of the fourth PMOS tube is connected with the source electrode of the seventh PMOS tube;

the drain electrode of the fifth PMOS tube is connected with the source electrode of the eighth PMOS tube;

the grid electrode of the sixth PMOS tube is respectively connected with the drain electrode of the eighth PMOS tube, the source electrode of the ninth PMOS tube, the drain electrode of the first NMOS tube and the first end of the first resistor;

the drain electrode of the sixth PMOS tube is respectively connected with the gate electrode of the third PMOS tube, the second end of the first capacitor, the second end of the second capacitor and the drain electrode of the sixth NMOS tube;

the grid electrode of the seventh PMOS tube and the grid electrode of the eighth PMOS tube both receive the bias voltage;

the grid electrode of the ninth PMOS tube receives the bias voltage;

the drain electrode of the ninth PMOS tube is respectively connected with the source electrode of the first NMOS tube, the drain electrode of the third NMOS tube, the first end of the second resistor and the grid electrode of the sixth NMOS tube;

the grid electrode of the first NMOS tube receives the bias voltage;

the grid electrode of the second NMOS tube and the grid electrode of the third NMOS tube both receive the bias voltage;

the source electrode of the second NMOS tube is respectively connected with the drain electrode of the third PMOS tube and the drain electrode of the fourth NMOS tube;

the source electrode of the third NMOS tube is respectively connected with the drain electrodes of the PMOS tubes, the drain electrode of the first PMOS tube and the drain electrode of the fifth NMOS tube;

the grid electrode of the fourth NMOS tube and the grid electrode of the fifth NMOS tube both receive the bias voltage;

the source electrode of the fourth NMOS tube, the source electrode of the fifth NMOS tube and the source electrode of the sixth NMOS tube are all grounded;

the second end of the first resistor is connected with the first end of the first capacitor;

and the second end of the second resistor is connected with the first end of the second capacitor.

Optionally, the width-to-length ratio of the third PMOS transistor is determined by the number of bits of the fine conversion.

Optionally, two gate switches connected to the gate of each of the plurality of PMOS transistors are controlled by the digital code in the fine conversion bit number;

for one of the PMOS tubes: assuming that the PMOS transistor corresponds to the digital code of the lowest bit in the fine conversion bits;

a first grid switch of the two grid switches connected with the PMOS tube is closed when the digital code of the lowest bit in the fine conversion bit number is 1, and meanwhile, a second grid switch of the two grid switches connected with the PMOS tube is opened when the digital code of the lowest bit in the fine conversion bit number is 1, and the PMOS tube receives the top voltage;

and a first grid switch of the two grid switches connected with the PMOS tube is disconnected when the digital code of the lowest bit in the fine conversion bit number is 0, and meanwhile, a second grid switch of the two grid switches connected with the PMOS tube is closed when the digital code of the lowest bit in the fine conversion bit number is 0, and the PMOS tube receives the bottom voltage.

Optionally, the width-to-length ratio of the plurality of PMOS transistors is determined by the number of bits of the fine conversion;

for one of the PMOS tubes: assuming that the PMOS tube corresponds to the digital code of the lowest bit in the fine conversion bit numbers, the width-to-length ratio of the PMOS tube is 1W/L;

for one of the PMOS tubes: if the PMOS tube corresponds to the number of the second lowest bit in the fine conversion bit number, the width-to-length ratio of the PMOS tube is 2W/L;

for one of the PMOS tubes: assuming that the PMOS transistor corresponds to a digital code one bit higher than the second lowest bit in the fine conversion bit number, the width-to-length ratio of the PMOS transistor is 4W/L.

A second aspect of an embodiment of the present invention provides a digital-to-analog converter, including: a conversion circuit as claimed in any one of the first aspect.

The invention provides a conversion circuit based on resistance voltage division and voltage interpolation, which is used for converting a digital quantity into a corresponding analog quantity; the resistance voltage dividing unit receives the reference voltage, the row selection signal and the column selection signal, outputs a top voltage and a bottom voltage to the voltage interpolation unit, and the top voltage and the bottom voltage represent the result of the coarse conversion; the resistance voltage division unit specifically includes: the state of the switches is controlled by a row selection signal and a column selection signal, and the number of the unit resistors is determined by the number of coarse conversion bits. That is, in the conversion circuit of the present invention, the number of unit resistors is not determined by the number of bits of the entire digital quantity, but by the number of coarse conversion bits. For example: in a 16-bit DAC, the number of unit resistors is currently determined by 16 bits, and thus the number of unit resistors is 2¹⁶65536. Assuming that the number of coarse conversion bits is 10 bits, the number of unit resistors is only 2¹⁰1024. This undoubtedly greatly reduces the number of unit resistors, the number of switches being determined by the unit resistors, the smaller the number of natural switches, which undoubtedly greatly reduces the physical area occupied by the unit resistors and the switches, and the natural control logic becomes simple due to the reduction in the number of switches.

Since only part of the bits are converted by the coarse conversion, the rest of the bits are converted by the fine conversion, and particularly, the voltage interpolation unit realizes the fine conversion function. The voltage difference unit receives the top end voltage and the bottom end voltage and outputs a result voltage, and the result voltage represents an analog quantity corresponding to the digital quantity; the voltage interpolation unit includes: and the number of the PMOS tubes is determined by the number of the fine conversion bits. That is, what the number of fine conversion bits is, there are how many PMOS transistors, for example: in a 16-bit DAC, assuming that the number of coarse conversion bits is 10 bits, the number of fine conversion bits is 6 bits, and 6 PMOS transistors are required. The structure realizes the digital-to-analog conversion function of the digital-to-analog converter, greatly reduces the number of unit resistors and switches on the basis of ensuring high-precision conversion and good monotonicity of the digital-to-analog converter, further reduces the physical area occupied by the digital-to-analog converter, and reduces the complexity of control logic.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.

FIG. 1 is a block diagram of a conversion circuit based on resistor division and voltage interpolation according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a preferred resistance voltage divider unit according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a preferred voltage interpolation unit in the embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, a schematic block diagram of a conversion circuit based on resistance voltage division and voltage interpolation according to an embodiment of the present invention is shown, where the conversion circuit is used to convert a digital quantity into a corresponding analog quantity, that is, to implement a digital-to-analog conversion function. The conversion circuit includes: a resistance voltage division unit and a voltage interpolation unit. The resistance voltage-dividing unit receives a reference voltage V_REFAnd the row selection signal and the column selection signal output a top voltage and a bottom voltage to the voltage interpolation unit, wherein the top voltage and the bottom voltage represent the result of the coarse conversion. The voltage interpolation unit receives the top voltage, the bottom voltage and the finely converted digital code and outputsVoltage V of the output result_outThe resulting voltage V_outI.e. an analog quantity characterizing the digital quantity.

The resistance voltage division unit realizes coarse conversion, the voltage interpolation unit realizes fine conversion, and the number of coarse conversion bits is assumed to be M bits, and the number of fine conversion bits is assumed to be N bits. The resistance voltage-dividing unit includes: the state of the switches is controlled by a row selection signal and a column selection signal, and the number of the unit resistors is determined by the number of coarse conversion bits. The voltage interpolation unit includes: and the number of the PMOS tubes is determined by the number of the fine conversion bits. Therefore, the resistance voltage division unit receives the M-bit digital code, the M-bit digital code determines the specific number of the unit resistance, and the specific values of the row selection signal and the column selection signal are determined based on the M-bit digital code. The voltage interpolation unit receives the digital code of N bit, and the specific number of the PMOS tubes is determined by the digital code of N bit.

The structure of the conversion circuit realizes the digital-to-analog conversion function of the digital-to-analog converter, greatly reduces the number of unit resistors and switches on the basis of ensuring high-precision conversion and good monotonicity of the digital-to-analog converter, further reduces the physical area occupied by the digital-to-analog converter, and reduces the complexity of control logic.

The conversion circuit according to the embodiment of the present invention will be described below specifically taking a 16-bit DAC as an example, but the DAC with other bits may refer to the structure of the 16-bit DAC, which is not an example. It is assumed that the number of bits subjected to coarse conversion is 10 bits and the number of bits subjected to fine conversion is 6 bits. Referring to fig. 2, a schematic diagram of a preferred resistance voltage division unit in an embodiment of the present invention is shown, where fig. 2 includes: the circuit comprises a plurality of resistors, a plurality of switches, a high-order decoder and a low-order decoder.

Since the number of bits for the coarse conversion is 10 bits, the number of unit resistors is 2¹⁰1024 resistance voltage dividing units having an X-Y Selection structure, 1024 unit resistances are distributed on 32 tracking lines, and after being connected in series, they are connected in a serpentine shape to a reference voltage (V in fig. 2)_REF) And ground potential (GND in fig. 2). For simplicity of illustration, the first, second, thirty-first and thirty-second rows, respectively identified asX₁、X₂、X₃₁And X₃₂Each row is provided with a row selection switch, denoted by S in FIG. 2₃₂Identify the third twelve rows X₃₂The remaining thirty rows of row select switches are similar and are not separately labeled.

Also shown by way of example are a first column, a second column, a thirty-first column, and a thirty-second column, respectively identified as Y₁、Y₂、Y₃₁And Y₃₂. Each of 1024 unit resistors has two ends connected to a switch, the first switch of the two switches has one end connected to the first end of the unit resistor and the other end connected to the first end of the row control switch of the row in which the unit resistor is located, and the second end of the row control switch outputs the top voltage (V in fig. 2)_TOP) To a voltage interpolation unit; one end of the second switch of the two switches is connected with the second end of the unit resistor, the other end of the second switch is connected with the third end of the row control switch of the row where the unit resistor is positioned, and the fourth end of the row control switch outputs the bottom end voltage (V in figure 2)_BOT) To the voltage interpolation unit.

In particular, one of the symbols in FIG. 2 is denoted as R₃₂The unit resistance of (2) is taken as an example, and the remaining unit resistance and the unit resistance R₃₂The connection mode of the resistors is the same, and the unit resistor R₃₂The row is the third twelve rows X₃₂The row selection switch is S₃₂. Specific resistance R₃₂Two ends of the resistor are respectively connected with the switch S₁、S₂Connected, first switch S₁And a unit resistance R of₃₂One end of the resistor is connected with a first switch S₁The other end of the line selection switch is S₃₂Is connected with the first end 1, and the row selection switch is S₃₂The second terminal 2 and the row selection switch are S₃₂The first terminal 1 of (a) is used in combination, so that the row selection switch is S₃₂Can output a top voltage V_TOPTo the voltage interpolation unit. A second switch S₂And a unit resistance R of₃₂The other end of the resistor is connected with a second switch S₂The other end of the line selection switch is S₃₂Is connected with the third terminal 3, the row selection switch is S₃₂The fourth terminal 4 and the row selection switch are S₃₂To (1) aThree terminals 3 are used together, so that the row selection switch is S₃₂The fourth terminal 4 can output a bottom voltage V_BOTTo the voltage interpolation unit.

Depending on the nature of the X-Y Selection structure, the row select signal and the column select signal need to be determined by 10-bit digital codes. Setting high-order digital codes in the coarse conversion digit numbers to generate row selection signals; generating a column selection signal by using a low-bit digital code in the coarse conversion bit number; and setting the lowest bit in the high-bit digital code as a flag bit, determining that the even lines are selected by the line selection signal when the flag bit is at a high level, and determining that the odd lines are selected by the line selection signal when the flag bit is at a low level.

Specifically, since the coarse conversion is 10 bits: d₁₅～D₆Thus will D₁₀～D₆As the lower of the 10 bits, D₁₅～D₁₁As the upper of 10 bits, D₁₅～D₁₁Is input to a high-order decoder, which selects a column line, D, on the basis of the value₁₀～D₆The value of (d) is input to a lower decoder which selects a column line according to the value. In this way, given the row selection signal X and the column selection signal Y, the unit resistance is selected and the top voltage V is uniquely determined_TOPAnd a bottom voltage V_BOTTherefore, the following two formulae can be obtained:

therefore, the following formula can be calculated:

since the high-order decoder generates a row selection control signal to select one of the 32 rows, and the low-order decoder generates a column selection control signal to select the 32 unit cells in the rowOne of the resistors, since the first tap of the odd row and the last tap of the even row determine the first voltage of this row, the lower decoder must therefore switch the direction of selection of the lower decoder depending on whether the upper decoder is pointing in the odd or even row, so the design uses D₁₁As a flag bit of a low-order decoder, if D₁₁High indicates that the even row is selected by the high decoder, and D is selected₁₁Low indicates that the odd rows are selected by the high decoder.

Through the resistance voltage division unit, 10-bit coarse conversion is realized, and the result of the coarse conversion is generated: top voltage V_TOPAnd a bottom voltage V_BOTAfter then the top voltage V_TOPAnd a bottom voltage V_BOTAnd outputting the voltage to a voltage interpolation unit.

The voltage interpolation unit in the embodiment of the invention comprises: the input end module comprises a positive input end module, a negative input end module and a folding and output module; the positive input module includes: the PMOS transistors are connected with the first PMOS transistor; the negative input end module includes: a second PMOS tube and a third PMOS tube; the folding and output module includes: the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube, the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the first resistor, the second resistor, the first capacitor and the second capacitor. Referring to fig. 3, a schematic structural diagram of a preferred voltage interpolation unit in the embodiment of the present invention is shown, where fig. 3 includes: a plurality of PMOS transistors, identified by dashed box 10 in fig. 3. First PMOS transistor M₁A second PMOS transistor M₂And the third PMOS transistor M₃And the fourth PMOS transistor M₄The fifth PMOS transistor M₅Sixth PMOS transistor M₆Seventh PMOS transistor M₇Eighth PMOS transistor M₈Ninth PMOS transistor M₉A first NMOS transistor M₁₀A second NMOS transistor M₁₁And the third NMOS transistor M₁₂And the fourth NMOS tube M₁₃The fifth NMOS transistor M₁₄And a sixth NMOS transistor M₁₅A first resistor R₁A second resistor R₂A first capacitor C₁A second capacitor C₂。

In FIG. 3, a plurality of PMOS transistors are connected in parallel within a virtual frame 10, and the source electrodes thereof are connected to a first PMOS transistor M₁Source electrode of the PMOS transistor M₂The drain electrodes are respectively connected; the drain electrodes of the PMOS tubes are all connected with the third NMOS tube M₁₂Is connected to the source of (a); the grid electrode of each PMOS tube in the PMOS tubes is connected with two grid electrode switches, and the grid electrode switch receives top end voltage V_TOPReceiving a bottom voltage V through another gate switch_BOT(ii) a Meanwhile, the first PMOS transistor M₁The grid electrode receives the bottom voltage V_BOT。

Specifically, since the number of bits for performing the fine conversion is 6 bits, that is: d₅～D₀Therefore, there should be 6 PMOS transistors in the dashed box 10, and only 3 PMOS transistors are exemplarily shown for simplicity of illustration. The grid of each PMOS tube is provided with two grid switches controlled by the digital code in the fine conversion digit; taking the leftmost PMOS transistor in the dashed box 10 of fig. 3 as an example: the PMOS transistor corresponds to the lowest bit D in the fine conversion bit number₀The digital code of (a); the first gate switch of the two gate switches connected with the PMOS transistor has the lowest bit D in the fine conversion bits₀Is closed when the digital code of (1) is 1; meanwhile, the second grid switch of the two grid switches connected with the PMOS tube is the digital code D with the lowest bit in the fine conversion bit number₀Is disconnected at 1 time when the PMOS transistor receives a top voltage V_TOP. Using D in the figure₀Indicating a controlled condition of the first gate switch, i.e. D₀When 1, the first gate switch is closed, and D₀When 1, it is not

The second gate switch is thus open.

Similarly, the first gate switch of the two gate switches connected to the PMOS transistor has the lowest bit D in the fine conversion bits₀The digital code of (1) is 0, and simultaneously, the second grid switch of the two grid switches connected with the PMOS tube has the lowest bit D in the fine conversion bit number₀Is closed when the digital code is 0, and the PMOS tube receives the bottom voltage V_BOT。

In the embodiment of the inventionThe width-to-length ratio of the PMOS transistors is determined by the number of bits of the fine conversion, taking the leftmost PMOS transistor in the dotted frame 10 in FIG. 3 as an example: the PMOS transistor corresponds to the lowest bit D in the fine conversion bit number₀Therefore, the width-to-length ratio is W/L, and the PMOS tube close to the left of the PMOS tube corresponds to the second lower D of the fine conversion bits₁Therefore, the width-to-length ratio is 2W/L, and so on, the rightmost PMOS transistor in the virtual frame 10 corresponds to the highest bit D in the fine conversion bit number₅Therefore, the width-to-length ratio is 32W/L.

The dummy frame 10 and the first PMOS transistor M₁Form a positive input end module, and a third PMOS tube M in the negative input end module₃The structure of (1) is as follows:

third PMOS transistor M₃The source electrodes of the PMOS tubes in the virtual frame 10 are respectively connected with the source electrodes of the PMOS tubes; third PMOS transistor M₃The grid of the second PMOS tube M6 is connected with the drain of the sixth PMOS tube M6; third PMOS transistor M₃Drain electrode of and the second NMOS tube M₁₁Is connected to the source of (a). Wherein, the third PMOS transistor M₃The width-to-length ratio of (1) is determined by the number of finely converted bits, since the number of finely converted bits is 6, 2⁶64, the third PMOS transistor M₃Has a width-to-length ratio of 64W/L.

The structure of the folding and output module is as follows: second PMOS transistor M₂The source electrode of the transistor receives a power supply voltage VDD; second PMOS transistor M₂Receiving a bias voltage V at the gate_b1(ii) a Second PMOS transistor M₂Drain electrode of and third PMOS transistor M₃The source electrodes of the PMOS tubes in the virtual frame 10 are respectively connected with the source electrodes of the PMOS tubes; fourth PMOS transistor M₄Source electrode of the PMOS transistor M₅Source electrode and sixth PMOS transistor M₆The source electrodes of the first and second transistors receive a power supply voltage; fourth PMOS transistor M₄Grid and fifth PMOS tube M₅Grid electrode and seventh PMOS tube M₇Drain electrode of the first NMOS transistor M₁₁The drain electrodes of the first and second electrodes are respectively connected; fourth PMOS transistor M₄Drain electrode of and seventh PMOS transistor M₇Is connected to the source of (a); fifth PMOS transistor M₅Drain electrode of and eighth PMOS transistor M₈Is connected to the source of (a); sixth PMOS transistor M₆Grid and eighth PMOS tube M₈Drain electrode of (1), ninth PMOS tube M₉Source electrode of (1), first NMOS tube M₁₀Drain electrode of (1), first resistor R₁Respectively at a first endAnd (4) connecting.

Sixth PMOS transistor M₆Drain electrode of and third PMOS transistor M₃Gate electrode of, and first capacitor C₁Second terminal, second capacitor C₂Second terminal and sixth NMOS transistor M₁₅The drain electrodes of the first and second electrodes are respectively connected; seventh PMOS tube M₇Grid and eighth PMOS transistor M₈All receiving a bias voltage V_b2(ii) a Ninth PMOS tube M₉Receiving a bias voltage V at the gate_bp(ii) a Ninth PMOS tube M₉Drain electrode of and the first NMOS transistor M₁₀Source electrode of and third NMOS transistor M₁₂Drain electrode of (1), second resistor R₂First end and sixth NMOS tube M₁₅The grids are respectively connected; first NMOS transistor M₁₀Receiving a bias voltage V at the gate_bn(ii) a Second NMOS transistor M₁₁Grid electrode of and a third NMOS tube M₁₂All receiving a bias voltage V_b3(ii) a Second NMOS transistor M₁₁Source electrode of and third PMOS transistor M₃Drain electrode of (1), fourth NMOS tube M₁₃Are connected respectively.

Third NMOS transistor M₁₂The source electrode of the dummy frame 10, the drain electrodes of the PMOS tubes M and the first PMOS tube M₁Drain electrode of and the fifth NMOS transistor M₁₄The drain electrodes of the first and second electrodes are respectively connected; fourth NMOS transistor M₁₃Grid electrode of (1), fifth NMOS tube M₁₄All receiving a bias voltage V_b4(ii) a Fourth NMOS transistor M₁₃Source electrode of and the fifth NMOS transistor M₁₄Source electrode of (1), sixth NMOS tube M₁₅The sources of the first and second transistors are all grounded GND; a first resistor R₁Second terminal and first capacitor C₁Is connected with the first end of the first connecting pipe; a second resistor R₂Second terminal and second capacitor C₂Is connected to the first end of the first housing. A first capacitor C₁Second terminal, second capacitor C₂Second terminal and sixth PMOS transistor M₆Drain electrode of (1) and sixth NMOS transistor M₁₅Are connected together to output a resulting voltage V_out。

According to the current I in the positive input terminal module_pShould be related to the current I in the negative input terminal module_nThe following equation can be obtained by the principle that the values of (A) are equal in size:

wherein the content of the first and second substances,

μ_pcox is the gate oxide capacitance per unit area, V for carrier mobility_THPIs the threshold voltage of PMOS tube, V_pi(i ═ 1, 2, 3, 4, 5, 6) is the gate terminal voltage of the multiple pmos tubes.

This gives the following formula:

the formula is simplified as follows:

V_BoT+V_p1+2*V_p2+…32*V_p6＝64*V_out

wherein, g_m＝2*k*(V_x-V_BOT-|V_THP|)。

From this, the following equation is derived:

thus, the function of fine conversion is completed, that is, the digital-to-analog conversion of the 16-bit DAC is realized by the combined action of the resistance voltage dividing unit and the voltage interpolation unit shown in fig. 2 and 3, taking 10-bit coarse conversion and 6-bit fine conversion as an example.

In summary, in the conversion circuit according to the embodiment of the invention, the resistance voltage dividing unit receives the reference voltage, and outputs the top voltage and the bottom voltage representing the coarse conversion result to the voltage interpolation unit based on the row selection signal and the column selection signal generated by the digital code of the coarse conversion bits. The voltage difference unit receives the top voltage and the bottom voltage, and utilizes the positive input end module, the negative input end module and the folding and output module to realize fine conversion and output a result voltage representing an analog quantity corresponding to the digital quantity.

With the above configuration, the number of unit resistors is not determined by the number of bits of the entire digital quantity, but by the number of coarse conversion bits. The number of unit resistors is greatly reduced, and the number of switches is determined by the unit resistors, the smaller the number of natural switches, which undoubtedly greatly reduces the physical area occupied by the unit resistors and the switches, and the natural control logic becomes simple due to the reduction in the number of switches. On the basis of ensuring high-precision conversion and good monotonicity of the digital-to-analog converter, the number of unit resistors and switches is greatly reduced, so that the occupied physical area is reduced, the control logic complexity is reduced, and the conversion circuit has higher practical value.

Based on the foregoing conversion circuit, an embodiment of the present invention further provides a digital-to-analog converter, where the digital-to-analog converter includes: a conversion circuit as claimed in any preceding claim.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A conversion circuit based on resistance voltage division and voltage interpolation is characterized in that the conversion circuit is used for converting a digital quantity into a corresponding analog quantity; the conversion circuit includes: a resistance voltage division unit and a voltage interpolation unit;

the top and bottom voltages characterizing the result of the coarse conversion;

2. The conversion circuit of claim 1, wherein the plurality of switches comprises: a row control switch;

3. The conversion circuit according to claim 2, wherein the row selection signal is generated by a high-order digital code in the coarse conversion bit number;

4. The conversion circuit according to claim 1, wherein the voltage interpolation unit includes: the input end module comprises a positive input end module, a negative input end module and a folding and output module;

the positive input module comprises: the PMOS tubes and the first PMOS tube;

the drain electrodes of the PMOS tubes are connected with the source electrode of a third NMOS tube in the folding and output module;

and the grid electrode of the first PMOS tube receives the bottom voltage.

5. The conversion circuit of claim 4, wherein the negative input module comprises: a third PMOS tube;

6. The conversion circuit of claim 5, wherein the folding and output module comprises: a second PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first resistor, a second resistor, a first capacitor and a second capacitor;

the source electrode of the second PMOS tube receives a power supply voltage;

the grid electrode of the second PMOS tube receives bias voltage;

the grid electrode of the ninth PMOS tube receives the bias voltage;

the grid electrode of the first NMOS tube receives the bias voltage;

7. The conversion circuit of claim 5, wherein the aspect ratio of the third PMOS transistor is determined by the number of bits of the fine conversion.

8. The conversion circuit of claim 4, wherein two gate switches connected to the gate of each of the plurality of PMOS transistors are controlled by the digital code in the fine conversion bit number;

9. The conversion circuit of claim 8, wherein the width-to-length ratios of the plurality of PMOS transistors are determined by the number of bits of the fine conversion;

10. A digital-to-analog converter, the digital-to-analog converter comprising: a conversion circuit as claimed in any one of claims 1 to 9.