CN113299862A

CN113299862A - Display panel, preparation method thereof and display device

Info

Publication number: CN113299862A
Application number: CN202110734564.8A
Authority: CN
Inventors: 侯瑞; 冯川桂; 鲍建东; 王玉林; 刘瑞; 范鹏磊; 龚增超; 殷兆伟; 韩强; 李俊; 高波; 陈翊鑫; 孙建; 何春霖; 叶佳望; 陈振国; 范天琪; 杜忠波; 徐鹏; 徐童言
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-06-30
Filing date: 2021-06-30
Publication date: 2021-08-24

Abstract

The disclosure provides a display panel, a preparation method thereof and a display device, and belongs to the technical field of display. The display panel comprises a substrate base plate, a driving circuit layer, a pixel layer and a thin film packaging layer which are sequentially stacked. The thin film packaging layer comprises a first inorganic packaging layer, an organic packaging layer and a second inorganic packaging layer which are sequentially stacked and arranged on one side, far away from the substrate, of the pixel layer. The display panel includes a display area and a peripheral area surrounding the display area; the edges of the first inorganic encapsulation layer and the second inorganic encapsulation layer are located in the peripheral area. Wherein the slope angle of the edge of the first inorganic packaging layer is in the range of 40-90 degrees; the slope angle of the edge of the second inorganic packaging layer is in the range of 40-90 degrees. The display panel of the present disclosure can reduce the frame width of the display panel.

Description

Display panel, preparation method thereof and display device

Technical Field

The disclosure relates to the technical field of display, and in particular relates to a display panel, a manufacturing method thereof and a display device.

Background

In an AMOLED (active matrix organic electroluminescent diode) display panel, a thin film encapsulation layer is generally required to block water and oxygen intrusion. However, in the prior art, the boundary of the thin film encapsulation layer is difficult to be accurately defined, which results in a display panel having a large bezel.

The above information disclosed in the background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art that is known to a person of ordinary skill in the art.

Disclosure of Invention

The present disclosure is directed to a display panel, a manufacturing method thereof, and a display device, which can reduce the width of a frame of the display panel.

In order to achieve the purpose, the technical scheme adopted by the disclosure is as follows:

according to a first aspect of the present disclosure, a display panel is provided, which includes a substrate base plate, a driving circuit layer, a pixel layer, and a thin film encapsulation layer, which are sequentially stacked; the thin film packaging layer comprises a first inorganic packaging layer, an organic packaging layer and a second inorganic packaging layer which are sequentially stacked and arranged on one side of the pixel layer, which is far away from the substrate;

the display panel includes a display area and a peripheral area surrounding the display area; edges of the first inorganic encapsulation layer and the second inorganic encapsulation layer are located in the peripheral region;

wherein the slope angle of the edge of the first inorganic packaging layer is in the range of 40-90 degrees; the slope angle of the edge of the second inorganic packaging layer is in the range of 40-90 degrees.

In an exemplary embodiment of the present disclosure, the material of the second inorganic encapsulation layer is an oxygen-free inorganic material, and the second inorganic encapsulation layer covers an edge of the first inorganic encapsulation layer.

In one exemplary embodiment of the present disclosure, the thin film encapsulation layer further comprises a third inorganic encapsulation layer, the third inorganic encapsulation layer being located between the organic encapsulation layer and the second inorganic encapsulation layer;

the slope angle of the edge of the third inorganic packaging layer is in the range of 40-90 degrees; an edge of the third inorganic encapsulation layer is flush with an edge of the first inorganic encapsulation layer.

In an exemplary embodiment of the present disclosure, the display panel is provided with a blocking dam and an anti-cracking dam at the peripheral region;

the driving circuit layer comprises an inorganic dielectric layer and a passivation layer which are sequentially stacked on one side of the substrate;

and the inorganic medium layer is provided with a partition groove between the blocking dam and the anti-cracking dam, and the partition groove penetrates through the inorganic medium layer and exposes the substrate base plate.

In an exemplary embodiment of the present disclosure, the second inorganic encapsulation layer is disposed on a surface of the passivation layer on a side of the first inorganic encapsulation layer away from the display area.

In an exemplary embodiment of the present disclosure, the peripheral region includes a fan-out region and a non-fan-out region adjacent to the fan-out region; the driving circuit layer is provided with fan-out routing in the fan-out area;

the blocking groove comprises a first blocking groove located in the non-fan-out region;

and the passivation layer is provided with a partition hole exposing the substrate base plate in the first partition groove.

In an exemplary embodiment of the present disclosure, the display panel is further provided with crack detection traces; in the non-fan-out region, the crack detection trace is located between the first partition groove and the blocking dam.

the blocking groove comprises a second blocking groove positioned in the fan-out area;

the passivation layer covers the second isolation groove; the fan-out routing wire is arranged on one side, far away from the substrate base plate, of the passivation layer.

According to a first aspect of the present disclosure, there is provided a display device including the display panel of any one of the above.

According to a first aspect of the present disclosure, there is provided a method of manufacturing a display panel including a display area and a peripheral area surrounding the display area, the method including:

providing a substrate base plate;

forming a driving circuit layer on one side of the substrate base plate;

forming a pixel layer on one side of the driving circuit layer, which is far away from the substrate base plate;

forming a first packaging material layer covering the display area and the peripheral area on one side of the pixel layer far away from the substrate;

patterning the first packaging material layer to form a first inorganic packaging layer, wherein the edge of the first inorganic packaging layer is positioned in the peripheral area;

forming an organic encapsulation layer on one side of the first inorganic encapsulation layer far away from the substrate base plate;

forming a second packaging material layer covering the display area and the peripheral area on one side of the organic packaging layer far away from the substrate;

and patterning the second packaging material layer to form a second inorganic packaging layer, wherein the edge of the second inorganic packaging layer is positioned in the peripheral area.

Drawings

The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a schematic structural diagram of a display panel in the related art.

Fig. 2 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.

Fig. 3 is a schematic top view of a display panel according to an embodiment of the present disclosure.

Fig. 4 is a schematic cross-sectional view illustrating a structure of a display panel according to an embodiment of the present disclosure.

Fig. 5 is a schematic structural diagram of forming a first inorganic encapsulation layer according to an embodiment of the disclosure.

Fig. 6 is a schematic structural diagram illustrating the formation of a second packaging material layer according to an embodiment of the disclosure.

Fig. 7 is a schematic structural diagram of forming a second inorganic encapsulation layer according to an embodiment of the disclosure.

Fig. 8 is a schematic structural view illustrating the formation of partition holes according to an embodiment of the present disclosure.

Fig. 9 is a schematic diagram comparing structures of a display panel of the present disclosure and a display panel of the related art at a frame.

Fig. 10 is a schematic structural diagram illustrating a first packaging material layer formed according to an embodiment of the disclosure.

Fig. 11 is a schematic structural diagram of forming a third packaging material layer according to an embodiment of the disclosure.

Fig. 12 is a schematic structural diagram of forming a first inorganic encapsulation layer and a third inorganic encapsulation layer in an embodiment of the disclosure.

Fig. 13 is a schematic structural diagram illustrating the formation of a second packaging material layer according to an embodiment of the disclosure.

Fig. 14 is a schematic diagram comparing structures of a display panel of the present disclosure and a display panel of the related art at a frame.

Fig. 15 is a schematic diagram comparing structures of a display panel of the present disclosure and a display panel of the related art on one side of a fan-out area.

Fig. 16 is a process flow diagram of a display panel according to an embodiment of the disclosure.

The reference numerals of the main elements in the figures are explained as follows:

f100, a substrate base plate; f200, a driving circuit layer; f201, a buffer material layer; f204, a first gate insulating layer; f205, a second gate insulating layer; f206, an interlayer dielectric layer; f207, a first source drain metal layer; f208, a passivation layer; f209, a second source drain metal layer; f210, a planarization layer; f300, a pixel layer; f301, a pixel electrode layer; f302, a pixel definition layer; f303, supporting a column layer; f400, a thin film packaging layer; f401, a first inorganic packaging layer; f402, a second inorganic packaging layer; f403, a third inorganic packaging layer; f500, anti-cracking dam; f600, supporting the substrate; f700, detecting and routing cracks; g100, isolating grooves; g101, isolating holes; AA. A display area; BB. A peripheral region; CC. A binding region; DD. A fan-out region; BD. A bending zone.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure.

In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals denote the same or similar structures in the drawings, and thus detailed descriptions thereof will be omitted.

The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the disclosure can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the primary technical ideas of the disclosure.

When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.

The terms "a," "an," "the," and the like are used to denote the presence of one or more elements/components/parts; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc. The terms "first" and "second", etc. are used merely as labels, and are not limiting on the number of their objects.

The disclosed embodiments provide a display panel and a display device using the same. Referring to fig. 4, the display panel includes a base substrate F100, a driving circuit layer F200, a pixel layer F300, and a thin film encapsulation layer F400, which are sequentially stacked. Here, the pixel layer F300 may be provided with a light emitting element as a sub-pixel, and the driving circuit layer F200 is provided with a pixel driving circuit driving the light emitting element.

In the present disclosure, the base substrate F100 may be an inorganic base substrate F100 or an organic base substrate F100. For example, the material of the substrate F100 may be a glass material such as soda-lime glass (soda-lime glass), quartz glass, sapphire glass, or a metal material such as stainless steel, aluminum, or nickel. As another example, the material of the base substrate F100 may be Polymethyl methacrylate (PMMA), Polyvinyl alcohol (PVA), Polyvinyl phenol (PVP), Polyether sulfone (PES), polyimide, polyamide, polyacetal, Polycarbonate (PC), Polyethylene terephthalate (PET), Polyethylene naphthalate (PEN), or a combination thereof.

Alternatively, the substrate F100 may be a flexible substrate F100, and thus the display panel of the present disclosure may be a flexible display panel. In one embodiment of the present disclosure, the material of the substrate F100 may be a layer of flexible organic material, for example, the material of the substrate F100 may be Polyimide (PI). In other embodiments, the flexible substrate F100 may also be a composite of multiple layers of materials and include flexible organic materials, for example, the substrate F100 may include multiple polyimide layers and a barrier layer between the polyimide layers.

Alternatively, the material of the base substrate F100 may be a transparent material. As such, the display panel of the present disclosure may serve as a transparent display panel.

Illustratively, in one embodiment of the present disclosure, the material of the base substrate F100 may include one or more layers of organic transparent flexible material (e.g., polyimide layer, etc.). When the number of the organic transparent flexible material layers is multiple, an inorganic material layer, such as a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer, may be interposed between adjacent organic transparent flexible material layers. In this example, the substrate base plate F100 is a flexible transparent substrate base plate F100, so that the display panel of the present disclosure is a flexible transparent display panel. Referring to fig. 2, in the display device of the present disclosure, the flexible transparent display panel PNL may be attached on a rigid transparent substrate WG for transparent display, and the display panel may be adapted to a planar substrate or a curved substrate. Further, the rigid transparent substrate F600 may be a window glass or the like, for example, a shop window glass, an automobile window glass or the like.

In the present disclosure, referring to fig. 4, the driving circuit layer F200 is provided with a pixel driving circuit for driving the sub-pixels. Any one of the pixel driving circuits may include the transistor F200M and a storage capacitor (not shown in fig. 4). Further, the transistor may be a thin film transistor. The thin film transistor can be a top gate type thin film transistor, a bottom gate type thin film transistor or a double-gate type thin film transistor; the material of the active layer of the thin film transistor can be an amorphous silicon semiconductor material, a low-temperature polysilicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material or other types of semiconductor materials; the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor. In one embodiment of the present disclosure, the thin film transistor is a low temperature polysilicon transistor.

It is to be understood that the type between any two transistors in the respective transistors in the pixel driving circuit may be the same or different. For example, in one embodiment, in one pixel driving circuit, part of the transistors may be N-type transistors and part of the transistors may be P-type transistors. Still illustratively, in another embodiment of the present disclosure, in one pixel driving circuit, the material of the active layer of a part of the transistors may be a low temperature polysilicon semiconductor material, and the material of the active layer of a part of the transistors may be a metal oxide semiconductor material.

Alternatively, the driving circuit layer F200 may include a semiconductor layer F203, a gate insulating layer F240, a gate layer F250, an interlayer dielectric layer F206, a source-drain metal layer SD, a planarization layer F210, and the like, which are stacked between the substrate F100 and the pixel layer F300. Each of the thin film transistor and the storage capacitor may be formed of a semiconductor layer, a gate insulating layer, a gate electrode layer, an interlayer dielectric layer, a source-drain metal layer, and the like. The position relation of each film layer can be determined according to the film layer structure of the thin film transistor. For example, in one embodiment of the present disclosure, the driving circuit layer F200 may include a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, and a source-drain metal layer, which are sequentially stacked, and the thin film transistor formed in this way is a top gate thin film transistor. For another example, in another embodiment of the present disclosure, the driving circuit layer F200 may include a gate electrode layer, a gate insulating layer, a semiconductor layer, an interlayer dielectric layer, and a source-drain metal layer, which are sequentially stacked, and the thin film transistor formed in this way is a bottom gate thin film transistor.

Alternatively, the driving circuit layer F200 may also adopt a double-gate layer structure, i.e., the gate layers may include a first gate layer and a second gate layer, the gate insulating layer F240 may include a first gate insulating layer F204 for isolating the semiconductor layer from the first gate layer, and a second gate insulating layer F205 for isolating the first gate layer from the second gate layer. For example, in one embodiment of the present disclosure, the driving circuit layer F200 may include a semiconductor layer, a first gate insulating layer F204, a first gate layer, a second gate insulating layer F205, a second gate layer, an interlayer dielectric layer, and a source-drain metal layer, which are sequentially stacked on one side of the substrate F100.

Optionally, the driving circuit layer F200 may also adopt a dual source drain metal layer structure, that is, the source drain metal layer SD may include a first source drain metal layer F207 and a second source drain metal layer F209, and the two source drain metal layers may be isolated from each other by an insulating medium. The insulating medium may be an inorganic material (for example, a silicon nitride layer serving as the passivation layer F208), an organic material (for example, a resin layer serving as a planarization layer), or a stack of an inorganic material and an organic material (for example, a stack including the passivation layer F208 stacked on the first source-drain metal layer F207 and a planarization layer stacked on the passivation layer F208 may be included). For example, in one embodiment of the present disclosure, the driving circuit layer F200 may include a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer F206, a first source-drain metal layer F207, a passivation layer F208, and a second source-drain metal layer F209, which are sequentially stacked on one side of the substrate F100. In one embodiment of the present disclosure, the driving circuit layer F200 adopts a dual gate layer, dual source drain metal layer structure. Illustratively, the driving circuit layer F200 includes a semiconductor layer, a first gate insulating layer F204, a first gate layer, a second gate insulating layer F205, a second gate layer, an interlayer dielectric layer F206, a first source-drain metal layer F207, a passivation layer F208, a second source-drain metal layer F209, and a planarization layer F210, which are sequentially stacked.

Alternatively, the driving circuit layer F200 may further include a buffer material layer F201 disposed between the substrate F100 and the semiconductor layer, the gate electrode layer, and the like are disposed on a side of the buffer material layer F201 away from the substrate F100. The material of the buffer material layer F201 may be an inorganic insulating material such as silicon oxide or silicon nitride. The buffer material layer F201 may be one inorganic material layer or a plurality of inorganic material layers stacked. The buffer layer may improve a bonding force between the driving circuit layer F200 and the substrate F100, and provide a stable environment for the driving circuit layer F200.

In the present disclosure, the pixel layer F300 may be provided with light emitting elements electrically connected corresponding to the pixel driving circuit, and the light emitting elements may serve as sub-pixels of the display panel. In this manner, the pixel layer F300 is provided with light emitting elements distributed in an array, and each light emitting element emits light under the control of the pixel driving circuit. In the present disclosure, the light emitting element may be an organic electroluminescent diode (OLED), a Micro light emitting diode (Micro LED), a quantum dot-organic electroluminescent diode (QD-OLED), or other type of light emitting element. Illustratively, in one embodiment of the present disclosure, the light emitting element is an organic electroluminescent diode (OLED), and the display panel is an OLED display panel. As follows, a possible structure of the pixel layer F300 will be exemplarily described, taking the light emitting element as an organic electroluminescent diode as an example.

In this exemplary OLED display panel, the pixel layer F300 may include a pixel electrode layer F301, a pixel defining layer F302, a support pillar layer F303, an organic light emitting functional layer F304, and a common electrode layer F305, which are sequentially stacked. The pixel electrode layer F301 has a plurality of pixel electrodes in the display area AA of the display panel; the pixel defining layer F302 has a plurality of through pixel openings in the display area AA, which are disposed in one-to-one correspondence with the plurality of pixel electrodes, and any one of the pixel openings exposes at least a partial region of the corresponding pixel electrode. The support pillar layer F303 includes a plurality of support pillars in the display area AA, and the support pillars are located on the surface of the pixel defining layer F302 away from the substrate F100, so as to support a Fine Metal Mask (FMM) during an evaporation process. The organic light emitting functional layer covers at least the pixel electrode exposed by the pixel defining layer F302. The organic light emitting function layer may include an organic electroluminescent material layer, and may include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. Each film layer of the organic light-emitting functional layer may be prepared by an evaporation process, and a pattern of each film layer may be defined by a fine metal Mask or an Open Mask (Open Mask) during evaporation. The common electrode layer may cover the organic light emitting function layer in the display area AA. In this way, the pixel electrode, the common electrode layer, and the organic light emitting functional layer between the pixel electrode and the common electrode layer form the organic light emitting diode F300D, and any one of the organic light emitting diodes may serve as one sub-pixel of the display panel.

In some embodiments, the pixel layer F300 may further include a light extraction layer on a side of the common electrode layer away from the substrate F100 to enhance the light extraction efficiency of the organic light emitting diode.

In the present disclosure, the thin film encapsulation layer F400 is disposed on the surface of the pixel layer F300 away from the base substrate F100, and may include an inorganic encapsulation layer and an organic encapsulation layer alternately stacked. The inorganic packaging layer can effectively block outside moisture and oxygen, and prevents the organic light-emitting functional layer from being invaded by the moisture and the oxygen to cause material degradation.

In one embodiment of the present disclosure, the thin film encapsulation layer F400 may include a first inorganic encapsulation layer F401, an organic encapsulation layer IJP, and a second inorganic encapsulation layer F402, which are sequentially stacked and disposed on a side of the pixel layer F300 away from the substrate F100. The organic encapsulation layer IJP may be positioned between the adjacent first inorganic encapsulation layer F401 and second inorganic encapsulation layer F402 in order to achieve planarization and reduce stress between the inorganic encapsulation layers. In one embodiment of the present disclosure, the materials of the first inorganic encapsulation layer F401 and the second inorganic encapsulation layer F402 may be different, and specifically, the oxygen element content of the first inorganic encapsulation layer F401 may be higher than that of the second inorganic encapsulation layer F402. Therefore, the first inorganic encapsulation layer F401 has a high content of oxygen, and is beneficial to the preparation of the organic encapsulation layer, especially the leveling of the organic liquid material for preparing the organic encapsulation layer. The second inorganic sealing layer F402 has a lower content of oxygen element or even no oxygen element, so that it has a better water and oxygen blocking effect, and can improve the sealing effect of the display panel.

Alternatively, the first inorganic encapsulation layer F401 may adopt an inorganic dielectric material containing oxygen, for example, one of silicon oxide and silicon oxynitride, so as to facilitate the preparation of the organic encapsulation layer, and especially facilitate the leveling of the organic liquid material for preparing the organic encapsulation layer. In the preparation of the organic encapsulation layer, an organic liquid material (e.g., organic ink) may be added to the side of the first encapsulation layer F401 away from the substrate F100 by means of inkjet printing, and the organic liquid material is cured after being leveled to form the organic encapsulation layer. Wherein, the edge of the organic encapsulation layer does not exceed the edge of the first inorganic encapsulation layer F401.

Alternatively, the thickness of the first inorganic encapsulation layer F401 may be 0.01 to 1.5 micrometers, for example, 1 micrometer, 1.1 micrometer, 1.2 micrometer. Optionally, the second inorganic encapsulation layer F402 may be an oxygen-free inorganic material, that is, an inorganic dielectric material containing an oxygen-free element, and the second inorganic encapsulation layer F402 containing an oxygen-free element can effectively block external moisture and oxygen, so as to prevent moisture and oxygen from invading the organic light emitting functional layer to degrade the material, and prevent pixel failure from improving the yield and the lifetime of the display panel. Further, the second inorganic encapsulation layer F402 may wrap the edge of the first inorganic encapsulation layer F401. Further, the material of the second inorganic encapsulation layer F402 is silicon nitride.

Alternatively, the second inorganic encapsulation layer F402 may be disposed on the surface of the passivation layer F208 on a side of the first inorganic encapsulation layer F401 away from the display area AA. In the present disclosure, since the second inorganic encapsulation layer F402 does not contain oxygen, the attack of moisture and oxygen to the first inorganic encapsulation layer F401 can be blocked. In addition, in order to prevent moisture and oxygen from possibly corroding the lower portion of the first inorganic encapsulation layer F401, a second inorganic encapsulation layer F402 may be disposed on the surface of the passivation layer F208. Since the material of the passivation layer F208 is also silicon nitride containing no oxygen element, the first inorganic encapsulation layer F401 is completely covered by the silicon nitride material.

Referring to fig. 3, the display panel may include a display area AA and a peripheral area BB surrounding the display area AA from a top view. The edges of the first inorganic encapsulation layer F401 and the second inorganic encapsulation layer F402 are located in the peripheral area BB. Here, an edge of the organic encapsulation layer may be located between an edge of the display area AA and an edge of the first inorganic encapsulation layer F401.

Referring to fig. 3, the display panel is provided with a bonding area CC in a peripheral area BB, and a bonding pad for connecting a circuit board or a chip is provided in the bonding area CC. Between the bonding area CC and the display area AA, the peripheral area BB has a fan-out area DD, and the fan-out area DD is provided with a fan-out trace that electrically connects the display area AA and the bonding area CC. In this way, the peripheral area BB can be divided into a fan-out area DD with fan-out traces and a non-fan-out area without fan-out traces along the direction around the display area AA.

In some embodiments, referring to fig. 3, the peripheral area BB may also be provided with a bending area BD, which is located between the binding area CC and the display area AA. The display panel may be bent in the bending area BD so as to bend the bonding pad to the back surface of the display panel. In one embodiment of the present disclosure, the bending region BD may be located between the fan-out region DD and the bonding region CC.

Referring to fig. 3, in a peripheral area BB of the display panel, the display panel may include a barrier DAM and an anti-crack DAM F500. The DAM is located between the anti-crack DAM F500 and the display area AA, and can block an organic liquid material to restrict a boundary of the organic encapsulation layer.

The barrier DAM may be formed by an organic layer/inorganic layer stack in the driving circuit layer F200 and the pixel layer F300, and particularly may be formed by an organic layer stack. The first and second inorganic encapsulation layers F401 and F402 may cover the DAM, i.e., edges of the first and second inorganic encapsulation layers F401 and F402 may be located between the DAM and the crack prevention DAM F500. Therefore, the DAM further extends the contact length between the first inorganic packaging layer F401 and the pixel layer F300 and the contact length between the first inorganic packaging layer F401 and the second inorganic packaging layer F402, so that the water and oxygen invasion path can be extended, and the packaging effect is improved. In some embodiments, the DAM may have a closed loop shape to surround the display area AA. In other embodiments, the DAM may be disposed only at the non-fan-out area, which extends through the non-fan-out area in a direction surrounding the display area AA.

The anti-cracking dam F500 can be located at the edge of the display panel and used for preventing cracks caused during cutting of the display panel from extending to the display area AA and reducing the risk that the display area AA or the peripheral area BB of the display panel fails due to crack extension. In some embodiments, the crack prevention dam F500 may have a closed ring shape to surround the display area AA. In other embodiments, the crack prevention dam F500 may be disposed only on the non-fan-out region, which extends through the non-fan-out region in a direction surrounding the display area AA.

The display panel provided by the present disclosure, referring to fig. 16, can be prepared by the following preparation method:

step S110, providing a base substrate F100;

step S120, forming a driving circuit layer F200 on one side of the base substrate F100;

step S130, forming a pixel layer F300 on the side of the driving circuit layer F200 away from the substrate F100;

step S140, forming a first inorganic packaging layer F401 and an organic packaging layer on one side of the pixel layer F300 far away from the substrate F100; the organic packaging layer is positioned on one side of the first inorganic packaging layer F401 far away from the substrate F100;

in step S150, a second inorganic encapsulation layer F402 is formed on the side of the organic encapsulation layer away from the base substrate F100.

In the related art, the steps S140 and S150 form the first inorganic encapsulation layer F401 and the second inorganic encapsulation layer F402 using an open mask process. Specifically, in step S140, an inorganic material may be deposited under the shadow of an open mask to form the first inorganic encapsulation layer F401. In step S150, an inorganic material may be deposited under the shadow of an open mask to form a second inorganic encapsulation layer F402. Because of the gap between the open mask and the substrate, the deposition gas can follow the gap below the mask to form an encapsulating shadow (shadow) that extends beyond the boundary defined by the open mask. According to the related art, the structure of the obtained display panel PNL0 is shown in fig. 1. In the related art, the width of the encapsulation shadow (shadow) often exceeds 20 microns, such as 20-40 microns. Referring to fig. 1, the first inorganic encapsulation layer F401 and the second inorganic encapsulation layer F402 have a very small slope angle at their edges due to the existence of the encapsulation shadow (shadow), and occupy a large frame space. Furthermore, in order to avoid overlapping of the packaging shadow (shadow) onto the anti-cracking DAM F500, the display panel needs to set a distance between the DAM and the anti-cracking DAM F500 wide enough to completely accommodate the packaging shadow (shadow), which makes the display panel have a wider frame.

In order to solve the above problem, referring to fig. 5 to 7, the present disclosure forms a first inorganic encapsulation layer F401 in step S140 by: referring to fig. 5, a first packaging material layer covering the display area AA and the peripheral area BB is formed on a side of the pixel layer F300 away from the substrate F100; the first packaging material layer is subjected to a patterning operation to form a first inorganic packaging layer F401.

Furthermore, the present disclosure forms the second inorganic encapsulation layer F402 in step S150 by: referring to fig. 6, a second encapsulation material layer covering the display area AA and the peripheral area BB is formed on a side of the organic encapsulation layer away from the base substrate F100; referring to fig. 7, the second packaging material layer is patterned to form a second inorganic packaging layer F402, and an edge of the second inorganic packaging layer F402 is located in the peripheral area BB.

In step S140 of the present disclosure, a first encapsulation material layer may be directly deposited on a substrate without using a mask; at this time, the first packaging material layer covers the display area AA and the peripheral area BB, and the thickness of each position is uniform. Then, a patterning operation is performed on the first encapsulation material layer by using a photolithography process to form a desired first inorganic encapsulation layer F401. Since the first encapsulation material layer has a uniform thickness at each position, the edge of the first inorganic encapsulation layer F401 and the display area AA have the same thickness. Because the first packaging material layer is patterned by adopting a photoetching process, the slope angle of the edge of the first inorganic packaging layer F401 is larger and is in the range of 40-90 degrees, and particularly can be in the range of 50-80 degrees. Therefore, on one hand, the boundary of the first inorganic encapsulation layer F401 can be accurately defined, and a redundant space does not need to be reserved for encapsulating shadows (shadow); on the other hand, the slope angle of the first inorganic encapsulation layer F401 is large, and the space occupied by the edge is small. Because there is no interference of the encapsulation shadow (shadow) to the boundary of the first inorganic encapsulation layer F401, there is no need to reserve a corresponding space for the encapsulation shadow (shadow) between the DAM and the anti-crack DAM F500, which can effectively reduce the frame width of the display panel.

In step S150 of the present disclosure, the second encapsulation material layer may be directly deposited on the substrate without using a mask; at this time, the second packaging material layer covers the display area AA and the peripheral area BB, and the thickness of each position is uniform. Then, a patterning operation is performed on the second encapsulation material layer by using a photolithography process to form a desired second inorganic encapsulation layer F402. Since the second encapsulation material layer has a uniform thickness at each position, the edge of the second inorganic encapsulation layer F402 and the display area AA have the same thickness. Because the second packaging material layer is patterned by adopting a photoetching process, the slope angle of the edge of the second inorganic packaging layer F402 is larger and is in the range of 40-90 degrees, and particularly can be in the range of 50-80 degrees. Therefore, on one hand, the boundary of the second inorganic encapsulation layer F402 can be accurately defined, and a redundant space is not required to be reserved for encapsulating the shadow (shadow); on the other hand, the slope angle of the second inorganic encapsulation layer F402 is large, and the space occupied by the edge is small. Because there is no interference of the encapsulation shadow (shadow) to the boundary of the second inorganic encapsulation layer F402, there is no need to reserve a corresponding space for the encapsulation shadow (shadow) between the DAM and the anti-crack DAM F500, which can effectively reduce the frame width of the display panel.

Fig. 9 shows the display panel PNL prepared by the present embodiment, and shows a related art display panel PNL 0. In fig. 9, the positions of the Cutting lines (Cutting Line) of these display panels are also shown. Referring to fig. 9, since the display panel PNL of the present embodiment does not have interference of the encapsulation shadow (shadow) on the boundary of the second inorganic encapsulation layer F402, there is no need to reserve a corresponding space for the encapsulation shadow (shadow) between the DAM and the anti-crack DAM F500, which may effectively reduce the frame width of the display panel.

In some embodiments, the frame of the display panel can be reduced by 20-60 microns in the non-fan-out region, for example, by 40 microns, by the above-described manufacturing method of the present disclosure.

In some embodiments, the frame of the display panel in the fan-out region DD can be reduced by 100 to 400 micrometers, for example, by 300 micrometers, by the above-described manufacturing method of the present disclosure.

In one embodiment of the present disclosure, the patterning of the first encapsulation material layer may be done prior to the preparation of the organic encapsulation layer. Exemplarily, step S140 may specifically include:

step S210, forming a first packaging material layer covering the display area AA and the peripheral area BB on a side of the pixel layer F300 away from the substrate F100;

step S220, performing a patterning operation on the first encapsulation material layer to form a first inorganic encapsulation layer F401;

in step S230, an organic encapsulation layer is formed on a side of the first inorganic encapsulation layer F401 away from the substrate F100.

According to this embodiment, the first inorganic encapsulation layer F401 of the obtained display panel includes the first inorganic encapsulation layer F401, the organic encapsulation layer, and the second inorganic encapsulation layer F402, which are sequentially stacked. Here, the first inorganic encapsulation layer F401 and the second inorganic encapsulation layer F402 are formed in two different patterning operations, and thus edges of the two may not be uniform. In one embodiment of the present disclosure, the edge of the second inorganic encapsulation layer F402 may be outside the edge of the first inorganic encapsulation layer F401, so that the second inorganic encapsulation layer F402 covers the edge of the first inorganic encapsulation layer F401, and a better water and oxygen blocking effect is achieved.

Alternatively, in this embodiment, the thickness of the second inorganic encapsulation layer F402 may be 0.01 to 1.5 micrometers, for example, may be 1 micrometer, 1.1 micrometer, 1.2 micrometer, and the like. Thus, the organic encapsulation layer is covered by the thicker second inorganic encapsulation layer F402, and the longitudinal water and oxygen barrier effect of the first inorganic encapsulation layer F401 can be ensured.

Referring to fig. 10 to 13, in another embodiment of the present disclosure, the patterning of the first encapsulation material layer may be completed after the organic encapsulation layer is prepared. Exemplarily, step S140 may specifically include:

step S310, referring to fig. 10, forming a first packaging material layer covering the display area AA and the peripheral area BB on a side of the pixel layer F300 away from the substrate F100;

step S320, forming an organic encapsulation layer on a side of the first encapsulation material layer away from the substrate F100;

step S330, referring to fig. 11, forming a third encapsulation material layer covering the display area AA and the peripheral area BB on a side of the organic encapsulation layer away from the base substrate F100;

in step S340, referring to fig. 12, the first and third encapsulating material layers are patterned to form a first inorganic encapsulating layer F401 and a third inorganic encapsulating layer F403. Referring to the display panel PNL in fig. 14, a third inorganic encapsulation layer F403 is interposed between an organic encapsulation layer (not shown in fig. 14) and the second inorganic encapsulation layer F402.

Referring to fig. 14, according to this embodiment, the first inorganic encapsulation layer F401 of the obtained display panel PNL includes a first inorganic encapsulation layer F401, an organic encapsulation layer (not shown in fig. 14), a third inorganic encapsulation layer F403, and a second inorganic encapsulation layer F402, which are sequentially stacked. In this case, the first inorganic encapsulation layer F401 and the third inorganic encapsulation layer F403 are formed in the same patterning operation, so that the edges of the two layers are flush. Furthermore, the slope angle of the edge of the third inorganic encapsulating layer F403 is large, and may be in the range of 40 ° to 90 °, and particularly, may be in the range of 50 ° to 80 °. Also shown in fig. 14 is a display panel PNL0 in the related art, and cut lines of the display panel PNL and the display panel PNL 0. Referring to fig. 14, the display panel PNL of the present disclosure may accurately define the boundaries of the first inorganic encapsulation layer F401, the third inorganic encapsulation layer F403 and the second inorganic encapsulation layer F402, and may not generate a shadow (shadow), so that it has a smaller bezel compared to the display panel PNL0 in the related art.

Alternatively, in this embodiment, the material of the third inorganic encapsulating layer F403 may be the same as that of the second inorganic encapsulating layer F402 to further improve the water oxygen barrier effect of the first inorganic encapsulating layer F401.

Alternatively, in this embodiment, the thickness of the third inorganic encapsulation layer F403 may be in the range of 0.01 to 1.5 micrometers, for example, in the range of 0.6 to 1.0 micrometers. Illustratively, the thickness of the third inorganic encapsulation layer F403 may be 0.7 micrometers.

Alternatively, in this embodiment, the thickness of the second inorganic encapsulation layer F402 may be in the range of 0.01 to 1.5 micrometers, for example, in the range of 0.2 to 0.5 micrometers. Illustratively, the thickness of the second inorganic encapsulation layer F402 may be 0.3 micrometers.

In the present disclosure, the respective inorganic insulating dielectric film layers between the substrate F100 and the passivation layer F208 in the driving circuit layer F200 may be defined as inorganic dielectric layers as a whole. In this way, the driving circuit layer F200 includes an inorganic dielectric layer and a passivation layer F208 sequentially stacked on one side of the substrate F100. It is understood that the film layers in the driving circuit layer F200 have different structures, and the film layers included in the inorganic dielectric layer are correspondingly different, so as to be located between the substrate F100 and the passivation layer F208.

In some embodiments of the present disclosure, in preparing the driving circuit layer F200, a blocking groove G100 penetrating through the inorganic dielectric layer and exposing the substrate F100 may be formed on the inorganic dielectric layer, the blocking groove G100 being located between the inorganic dielectric layer and the blocking DAM F500. In this way, in the obtained display panel, a partition groove G100 is formed in the inorganic dielectric layer between the DAM and the anti-cracking DAM F500, and the partition groove G100 penetrates through the inorganic dielectric layer and exposes the substrate F100. In this way, the inorganic material in the inorganic dielectric layer is removed at the position of the partition groove G100. The partition groove G100 can further prevent the crack caused by the cutting of the display panel from spreading to the display area AA, so that the display area AA can be prevented from being affected by the crack generated during the cutting, thereby improving the service life of the display panel. In particular, in the present disclosure, the display area AA is more susceptible to cracks due to the reduction of the bezel of the display panel; the partition groove G100 can be matched with the anti-cracking dam F500, so that the extension of cracks to the display area AA can be prevented when the anti-cracking dam F500 fails, the stability of the display panel is further improved, and the potential risk caused by reduction of the frame is overcome.

The blocking groove G100 may be disposed at a partial position of the peripheral area BB or may be disposed around the display area AA. For example, in one embodiment of the present disclosure, the partition groove G100 may include a first partition groove G110 located at a non-fan-out area. The first partition groove penetrates the non-fan-out area in a direction surrounding the display area AA. Still illustratively, in another embodiment of the present disclosure, the partition groove G100 may include a second partition groove G120 located at the fan-out region DD. The second partition groove penetrates the fan-out area DD in a direction surrounding the display area AA. Further illustratively, the blocking groove G100 may include a first blocking groove and a second blocking groove, which may be connected to each other to form a closed loop shape around the display area AA.

In some embodiments of the present disclosure, the passivation layer F208 is provided with a blocking hole G101 exposing the substrate base plate F100 at the first blocking groove. The blocking hole G101 may penetrate the first blocking groove in an extending direction of the first blocking groove. In this way, the effect of blocking the cracks by the partition groove G100 can be further improved. In an embodiment of the disclosure, a dimension (i.e., a width) of the blocking hole G101 in a direction away from the display area AA may be 2 to 6 micrometers, for example, may be 3 micrometers. It is to be noted that the design size of the blocking hole G101 may be increased or decreased as appropriate according to the process, and may be 4 micrometers, 5 micrometers, 6 micrometers, or the like, for example.

In one embodiment of the present disclosure, in the non-fan-out region, the size between the edge of the first inorganic encapsulation layer F401 and the first partition groove is 3 to 8 micrometers, and for example, may be 5 micrometers. The dimension between the edge of the first blocking groove and the edge of the blocking hole G101 may be 3 to 8 micrometers, for example, 5 micrometers. In one embodiment of the present disclosure, a dimension between the first blocking groove and the crack stopper may be 3 to 8 micrometers, for example, may be 5 micrometers.

Optionally, in the non-fan-out region, the edge of the second inorganic encapsulation layer F402 does not exceed the edge of the side of the partition hole G101 close to the display area AA. As such, the second inorganic sealing layer F402 does not cover the blocking hole G101 to ensure the crack-blocking effect of the blocking groove G100. Further, in one embodiment of the present disclosure, an edge of the second inorganic encapsulation layer F402 extends into the first partition groove.

In some embodiments of the present disclosure, the passivation layer F208 may cover the second isolation groove, and the fan-out trace may be disposed on a side of the passivation layer F208 away from the substrate F100, for example, may be disposed on the second source-drain metal layer F209. Further, the fan-out traces may be covered by a planarization layer F210.

Optionally, referring to fig. 3, the display panel further includes a crack detection trace F700, where in the non-fan-out region, the crack detection trace F700 is located between the partition groove G100 and the anti-cracking dam F500. Thus, the crack detection trace F700 can detect the crack breaking through the anti-cracking dam F500 more sensitively. Of course, in other embodiments of the present disclosure, referring to fig. 8 and 14, the crack detection trace F700 may also be located between the partition groove G100 and the barrier DAM. Thus, the crack detection trace F700 can detect cracks that break through to the inner side (the side close to the display area) of the partition groove G100, and further more intuitively reflect risks faced by the display area.

Alternatively, in the preparation process of the display panel of the present disclosure, a supporting substrate F600 may be provided, and then the substrate F100, the driving circuit layer F200, the pixel layer F300, and the thin film encapsulation layer F400 may be sequentially formed on one side of the supporting substrate F600. After the preparation of the display panel is completed, the support substrate F600 may be peeled off to obtain the display panel.

In one embodiment of the present disclosure, the support substrate F600 may be a glass substrate.

Alternatively, in the manufacturing process of the display panel of the present disclosure, one large-sized substrate may be provided as a mother substrate, and the mother substrate may provide the support substrate F600 for a plurality of display panels. After the preparation of the display panel is completed, cutting (e.g., laser cutting) may be performed along a cutting line to obtain a plurality of display panels.

Optionally, in the manufacturing process of the display panel of the present disclosure, after the thin film encapsulation layer F400 is formed, a Temporary Protection Film (TPF) may be attached to a side of the thin film encapsulation layer F400 away from the base substrate F100, and then the temporary protection film is cut to expose the respective bonding pads of the display panel, so as to facilitate electrical detection and classification of the display panel. Fig. 15 shows a cutting position where the temporary protection film is cut at the fan-out area side of the display panel PNL0 in the related art and the display panel PNL of the present disclosure. Referring to fig. 15, in preparing the display panel PNL of the present disclosure, the cutting line is positioned at a side of the bending area BD away from the display area AA when cutting the temporary protective film. Therefore, the temporary protection film cutting area can be prevented from being arranged between the bending area BD and the display area AA, and the reduction effect of the inorganic packaging layer on the frame is reduced by the temporary protection film cutting area. In contrast, in the related art, the temporary protection film is generally cut on the side of the bending area BD close to the display area AA, which makes the display panel have a larger bezel on the fan-out area side.

It should be noted that although the various steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc., are all considered part of this disclosure.

It is to be understood that the disclosure is not limited in its application to the details of construction and the arrangements of the components set forth in the specification. The present disclosure is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications are within the scope of the present disclosure. It should be understood that the disclosure disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present disclosure. The embodiments of this specification illustrate the best mode known for carrying out the disclosure and will enable those skilled in the art to utilize the disclosure.

Claims

1. The display panel is characterized by comprising a substrate base plate, a driving circuit layer, a pixel layer and a thin film packaging layer which are sequentially stacked; the thin film packaging layer comprises a first inorganic packaging layer, an organic packaging layer and a second inorganic packaging layer which are sequentially stacked and arranged on one side of the pixel layer, which is far away from the substrate;

2. The display panel according to claim 1, wherein the material of the second inorganic encapsulation layer is an oxygen-free inorganic material, and the second inorganic encapsulation layer covers the edge of the first inorganic encapsulation layer.

3. The display panel of claim 1, wherein the thin film encapsulation layer further comprises a third inorganic encapsulation layer, the third inorganic encapsulation layer being positioned between the organic encapsulation layer and the second inorganic encapsulation layer;

4. The display panel according to claim 1, wherein in the peripheral region, the display panel is provided with a blocking dam and an anti-cracking dam;

the driving circuit layer comprises a passivation layer and an inorganic medium layer composed of inorganic insulating film layers between the passivation layer and the substrate base plate;

5. The display panel according to claim 4, wherein the second inorganic encapsulation layer is disposed on the passivation layer surface on a side of the first inorganic encapsulation layer away from the display area.

6. The display panel of claim 4, wherein the peripheral region comprises a fan-out region and a non-fan-out region adjacent to the fan-out region; the driving circuit layer is provided with fan-out routing in the fan-out area;

7. The display panel of claim 6, wherein the display panel is further provided with crack detection traces; in the non-fan-out region, the crack detection trace is located between the first partition groove and the blocking dam.

8. The display panel of claim 4, wherein the peripheral region comprises a fan-out region and a non-fan-out region adjacent to the fan-out region; the driving circuit layer is provided with fan-out routing in the fan-out area;

9. A display device comprising the display panel according to any one of claims 1 to 8.

10. A method for manufacturing a display panel, the display panel including a display area and a peripheral area surrounding the display area, the method comprising:

providing a substrate base plate;

forming a driving circuit layer on one side of the substrate base plate;