CN113299633A

CN113299633A - Stack-packaged semiconductor device assemblies including one or more windows and related methods and packages

Info

Publication number: CN113299633A
Application number: CN202110584662.8A
Authority: CN
Inventors: M·门罗
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2016-06-30
Filing date: 2017-06-21
Publication date: 2021-08-24
Also published as: WO2018005189A1; KR101997418B1; US20180005983A1; US20190051631A1; CN109314104A; TW201813048A; EP3479405A1; US10777530B2; KR20180138218A; JP6663041B2; US10121766B2; EP3479405A4; JP2019519103A; TWI657561B

Abstract

The present application relates to package-on-package semiconductor device assemblies including one or more windows and related methods and packages. A semiconductor device package for incorporation into a semiconductor device assembly may include a substrate including an array of conductive elements positioned on a lower surface of the substrate. A window may extend through the substrate from the lower surface of the substrate to an upper surface of the substrate. The array of conductive elements may at least partially laterally surround a perimeter of the window, and the substrate may extend laterally beyond the array of conductive elements. A semiconductor device may be supported on the upper surface of the substrate around a periphery of the array of conductive elements. The semiconductor device may be electrically connected to at least some of the conductive elements of the array by routing elements extending from the semiconductor device towards the window.

Description

Stack-packaged semiconductor device assemblies including one or more windows and related methods and packages

Related information of divisional application

The scheme is a divisional application. The parent application to this division is the invention patent application entitled "stacked package semiconductor device assembly including one or more windows and related methods and packages" filed as 2017, 6/21/d, and having application number 201780035273.1.

Priority claim

The present application is a national entry phase of international patent application publication No. WO2018/005189 claiming benefit of the application date of united states patent application No. 15/238,382, filed on 8/16/2016 and united states provisional patent application No. 62/356,929, filed on 6/30/2016, the entire contents of each of which are hereby incorporated herein by reference.

Technical Field

The present disclosure relates generally to semiconductor device assemblies in a Package On Package (POP) configuration. More particularly, the disclosed embodiments relate to semiconductor device assemblies employing windowed POP configurations and related methods and packages.

Background

A Package On Package (POP) configuration may be employed when operatively connecting individual semiconductor devices to one another. A POP configuration may be assembled by placing a first substrate having a first semiconductor device thereon over the top of a second substrate having a second semiconductor device thereon and electrically and mechanically securing the first substrate to the second substrate. Some such POP configurations may employ a windowed substrate. For example, U.S. patent publication No. 2014/0264946 to kimm (Kim), et al, 9/18/2014, the disclosure of which is incorporated herein by reference in its entirety, discloses a windowed POP configuration in which the first semiconductor device is positioned within a window extending through the second substrate, and the second semiconductor device is stacked on top of the first semiconductor device and electrically connected to the second substrate by wire bonding.

Disclosure of Invention

A semiconductor device package for incorporation into a semiconductor device assembly according to the present invention may include a substrate including an array of conductive elements positioned on a lower surface of the substrate. A window may extend through the substrate from the lower surface of the substrate to an upper surface of the substrate. The array of conductive elements may at least partially laterally surround a perimeter of the window, and the substrate may extend laterally beyond the array of conductive elements. A semiconductor device may be supported on the upper surface of the substrate around a periphery of the array of conductive elements. The semiconductor device may be electrically connected to at least some of the conductive elements of the array by routing elements extending from the semiconductor device towards the window.

A semiconductor device assembly according to the present invention may include: a first substrate comprising a first semiconductor device on the first substrate, and a first array of conductive elements positioned on an upper surface of the first substrate. A second substrate can overlie the first substrate, the second substrate including a second array of conductive elements positioned on a lower surface of the second substrate. At least some of the conductive elements of the second array may be electrically connected to corresponding conductive elements of the first array. The second substrate may include a window extending from the lower surface to an upper surface of the second substrate. The second substrate may be configured to support additional semiconductor devices around a perimeter of the window, at least a portion of an outer perimeter of the first substrate being coupled to an inner portion of the second substrate defining the perimeter of the window.

Methods of fabricating semiconductor device assemblies according to the present invention may involve: a processing unit supported on an upper surface of a first substrate is positioned at least partially through a window in a second substrate overlying the first substrate. At least some of the conductive elements of the first array of conductive elements positioned on the upper surface of the first substrate may be electrically connected with at least some of the corresponding conductive elements of the second array of conductive elements positioned on the lower surface of the second substrate.

Drawings

While the invention concludes with claims particularly pointing out and distinctly claiming specific embodiments, various features and advantages of embodiments within the scope of the invention may be more readily ascertained from the following description when read in conjunction with the accompanying drawings, in which:

FIG. 1 is a top perspective view of a semiconductor device package for incorporation into a semiconductor device assembly;

fig. 2 is a bottom view of the semiconductor device package of fig. 1;

FIG. 3 is a top perspective view of a semiconductor device assembly including the semiconductor device package of FIG. 1;

fig. 4 is a side view of the semiconductor device assembly of fig. 3;

FIG. 5 is an enlarged portion of a side view of the semiconductor device assembly shown in FIG. 4;

FIG. 6 is an enlarged portion of a side view of the semiconductor device assembly shown in FIG. 4 including a thermal management structure;

FIG. 7 is a further enlarged perspective view of the electrical connections of the semiconductor device assembly of FIG. 4;

fig. 8 is a bottom perspective view of a portion of the semiconductor device assembly of fig. 4; and

fig. 9 is a top view of another embodiment of a semiconductor device assembly.

Detailed Description

The illustrations presented in this disclosure are not meant to be actual views of any particular semiconductor device assembly, semiconductor device package, or components thereof, but are merely idealized representations which are employed to describe illustrative embodiments. Accordingly, the drawings are not necessarily to scale.

The disclosed embodiments relate generally to semiconductor device assemblies employing windowed POP configurations that can reduce assembly height, enable simpler routing between connected components, and better utilize available surface area. More particularly, embodiments of semiconductor device assemblies are disclosed that can position a first semiconductor device proximate to (e.g., at, adjacent to, at least partially received through) a window in an overlying substrate (e.g., joining a portion of the overlying substrate defining the window) and distributable to other semiconductor devices around a perimeter of the window.

As used in this disclosure, the terms "upper," "lower," "overlying," and other terms indicating relative orientations are used for convenience only and refer only to the orientation depicted in the figures. Semiconductor device assemblies and their components within the scope of the present invention, when deployed for practical use, may be oriented in any direction that is convenient and beneficial to the user. For example, when incorporated into a final product and deployed for use, the surface, which is in fact referred to in this disclosure as "up," may be oriented down to the side, angled, or moved between various orientations.

Referring to fig. 1, a top perspective view of a semiconductor device package 100 for incorporation into a semiconductor device assembly 102 (see fig. 3) is shown. The semiconductor device package 100 may include, for example, a substrate 104 on which a semiconductor device 106 is carried. The substrate 104 may comprise a thin plate, a thick plate, or a wafer of dielectric or semiconductor material, for example. More particularly, the substrate 104 may comprise, for example, a printed circuit board or a semiconductor wafer.

The window 108 may extend through the substrate 104 from a lower surface 110 of the substrate 104 to an upper surface 112 of the substrate 104. The window 108 may be, for example, a hole, opening, void, port, or other aperture that provides gas flow communication between the lower and

upper surfaces

110 and 112 of the substrate 104. In some embodiments, the shape of the perimeter of the window 108 may be the same as the shape of the perimeter of the substrate 104, such as shown in fig. 1. For example, both the window 108 and the perimeter of the substrate 104 may be rectangular (e.g., square). In other embodiments, the shape of the perimeter of the window 108 may be different than the shape of the perimeter of the substrate 104, as shown in fig. 9. In some embodiments, the geometric center of the window 108 may be at least substantially aligned with the geometric center of the substrate 104. For example, the point of greatest average distance to the lateral perimeter of the window 108 may be positioned in at least substantially the same location as the point of greatest average distance to the lateral perimeter of the substrate 104. In other embodiments, the geometric center of the window 108 may not be aligned with the geometric center of the substrate 104. In some embodiments, the window 108 may be laterally surrounded by the material of the substrate 104. For example, window 108 may be enclosed by contiguous surfaces of substrate 104 extending around window 108 and the perimeter of window 108 is defined by contiguous surfaces of substrate 104 extending around window 108. In other embodiments, window 108 may be laterally surrounded only by material portions of substrate 104 (e.g., such as on three or two sides). Although a single window 108 is depicted in fig. 1, a substrate 104 including multiple windows 108 may be employed.

The semiconductor device 106 may be supported and/or integrated on the upper surface 112 of the substrate 104 and may be distributed proximate the periphery of the window 108. The semiconductor device 106 may be positioned between the perimeter of the substrate 104 and the perimeter of the window 108 on any number of sides thereof. For example, the semiconductor device 106 may be laterally adjacent a window 108 proximate each of its corners on each of its sides, on its three sides or corners, on its two opposing sides or corners, on one of its sides or corners, or any combination of sides and corners, as shown in fig. 1.

The semiconductor device 106 may include, for example, functional components to operably connect to another semiconductor device package 122 (see fig. 4) to form a semiconductor device assembly (see fig. 3, 4). More particularly, the semiconductor device 106 may include, for example, a singulated chip (e.g., a rectangular prism) of semiconductor material (e.g., silicon, germanium, gallium) having integrated circuitry thereon to perform a predefined function. As a particular non-limiting example, the semiconductor device 106 may include a memory chip (e.g., Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Read Only Memory (ROM), Programmable Read Only Memory (PROM), Erasable Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory). In some embodiments, one or more of the semiconductor devices 106 represented in fig. 1 may include a stack of individual semiconductor devices.

In some embodiments, such as shown in fig. 1, an overmold 114 may be positioned at least partially around at least some of the semiconductor devices 106 on at least a portion of the upper surface 112 of the substrate 104. For example, the overmold 114 may completely cover the upper surface 112 of the substrate 104 and completely laterally surround the semiconductor device 106. More particularly, the overmold 114 may completely cover the upper surface 112 of the substrate 104 and completely cover the semiconductor devices 106 supported thereon. The overmold 114 may comprise, for example, a polymeric material (e.g., an epoxy). In other embodiments, the semiconductor device package 100 may lack any overmold 114, exposing at least a portion of the upper surface 112 of the substrate 104 and the semiconductor device 106 to the environment.

Fig. 2 is a bottom view of the semiconductor device package 100 of fig. 1. The semiconductor device package 100 may include an array 116 of conductive elements 118 positioned on the lower surface 110. The conductive elements 118 may include, for example, pads, bumps, balls, pillars, or other structures of conductive material (e.g., copper, gold, metal alloy) exposed at the lower surface 110 of the substrate 104. Array 116 may be positioned adjacent the perimeter of window 108. For example, the array 116 may extend around at least a portion of the perimeter of the window 108. More particularly, the array 116 may be positioned completely around the window 108 and directly laterally adjacent to the perimeter of the window 108 such that the array 116 is laterally spaced from the perimeter of the semiconductor device 106 and the substrate 104 on the upper surface 112 (see fig. 1). The semiconductor devices 106 may be positioned laterally between the perimeter of the array 116 and the perimeter of the substrate 104.

The routing element 120 may operatively connect the semiconductor device 106 to at least some of the conductive elements 118 of the array 116 of conductive elements 118. The routing elements 120 may include, for example, lines, traces or vias of conductive material that electrically connect the semiconductor devices 106 to the respective conductive elements 118 of the array 116. The routing elements 120 may extend from the semiconductor device 106 to the respective conductive elements 118 of the array 116 along the upper surface 112 (see fig. 1), the lower surface 110, or within the material of the substrate 104 toward the window 108.

As a specific, non-limiting example, a semiconductor device package for incorporation into a semiconductor device assembly in accordance with this invention may include a substrate including an array of conductive elements positioned at a lower surface of the substrate. A window may extend through the substrate from the lower surface to an upper surface of the substrate. An array of conductive elements may at least partially laterally surround a perimeter of the window, and the substrate may extend laterally beyond the array of conductive elements. A semiconductor device may be supported on the upper surface of the substrate around the perimeter of the array of conductive elements. A semiconductor device may be electrically connected to at least some of the conductive elements of the array by routing elements extending from the semiconductor device towards the window.

Fig. 3 is a top perspective view of the semiconductor device assembly 102 including the semiconductor device package 100 of fig. 1, and fig. 4 is a side view of the semiconductor device assembly 102 of fig. 3. Referring collectively to fig. 3 and 4, the semiconductor device package 100 may be assembled with another semiconductor device package 122 in a Package On Package (POP) configuration to form the semiconductor device assembly 102. Another semiconductor device package 122, which may be a first one of the semiconductor device packages 100 and 122 when viewed from bottom to top, may include, for example, a first substrate 124 and a first semiconductor device 127 carried by the first substrate 124.

The first substrate 124 of the first semiconductor device package 122 may underlie the second substrate 104 of the second semiconductor device package 100. The first substrate 124 may comprise, for example, a thin plate, slab, or wafer of dielectric or semiconductor material. More particularly, the first substrate 124 may comprise, for example, a printed circuit board or a semiconductor wafer. The first substrate 124 may include an array 126 of conductive elements 128 positioned on an upper surface 130 of the first substrate 124, the upper surface 130 facing the lower surface 110 of the second substrate 104. The conductive elements 128 may include structures such as pads, bumps, balls, pillars, paste, or other conductive materials exposed at the upper surface 130 of the first substrate 124.

At least some of the conductive elements 128 of the array 126 may be electrically connected to corresponding conductive elements 118 of the array 116. For example, the conductive elements 128 of the array 126 and the corresponding conductive elements 118 of the array 116 may be secured to one another (e.g., by solder connections) to operatively connect the first semiconductor device 127 to one or more additional semiconductor devices 106 (see fig. 1, 2) and to mechanically secure the first semiconductor device package 122 to the second semiconductor device package 100. In this embodiment, a portion of the second substrate 104 (e.g., the peripheral portion defining the window 108) and a portion of the first substrate 124 may overlap such that the conductive elements 128 of the array 126 may be electrically connected to corresponding conductive elements 118 of the array 118. For example, the portion of the second substrate 104 that defines the perimeter of the window 108 and the window 108 itself may collectively cover at least a majority (e.g., all) of the first substrate 124.

The surface area of the upper surface 130 of the first substrate 124 may be less than the surface area of the lower surface 110 of the second substrate 104. For example, the surface area of the lower surface 110 of the second substrate 104 may be at least about 1.1 times the surface area of the upper surface 130 of the first substrate 124. More particularly, the surface area of the lower surface 110 of the second substrate 104 may be, for example, at least about 1.5 times the surface area of the upper surface 130 of the first substrate 124. As particular non-limiting examples, the surface area of the lower surface 110 of the second substrate 104 may be at least about 2, 2.5, or 3 times the surface area of the upper surface 130 of the first substrate 124. The second substrate 104 may extend laterally beyond the perimeter of the first substrate 124 on at least one side. For example, the second substrate 104 may protrude laterally from the first substrate 124 on two sides, three sides, or all four sides. Because the second substrate 104 is larger than the first substrate 124, there may be a larger available surface area for the routing elements 120 (see fig. 2), enabling a larger number of connections to be made without reducing the size of the routing elements 120 (see fig. 2), thereby reducing cross-talk between the routing elements 120 (see fig. 2), and enabling a larger number of additional semiconductor devices 106 (see fig. 1, 2) to be deployed.

The first semiconductor device 127 may include, for example, functional components to be operably connected to one or more additional semiconductor devices 106 of the second semiconductor device package 100. More particularly, the first semiconductor device 127 may include, for example, a singulated chip of semiconductor material having integrated circuitry thereon to perform a predefined function. As a particular, non-limiting example, the semiconductor device 127 may include a processing unit (e.g., a logic circuit, a processor, a microprocessor). Although a single first semiconductor device 127 is depicted in fig. 3, in other embodiments, the first semiconductor device package 122 may include a plurality of semiconductor devices 127.

The first semiconductor device 127 extends at least partially through the window 108 from below the lower surface 110 of the second substrate 104 of the second semiconductor device package 100. For example, the first semiconductor device 127 and the window 108 may have a size, shape, and positioning that enables the first semiconductor device 127 to extend from proximate the upper surface 130 of the first substrate 124 into the window 108 and at least partially through the window 108, such that an upper surface 132 of the first semiconductor device 127 may be positioned within the window 108 between the upper surface 112 and the lower surface 110 of the second substrate 104, as shown in fig. 3. As another example, the first semiconductor device 127 may extend completely through the window 108 from proximate the upper surface 130 of the first substrate 124 such that an upper surface 132 of the first semiconductor device 127 is coplanar with the upper surface 112 of the second substrate 104, or positioned above the upper surface 112 of the second substrate 104. More particularly, the first semiconductor device 127 may extend completely through the window 108 from proximate the upper surface 130 of the first substrate 124 such that an upper surface 132 of the first semiconductor device 127 protrudes from the overmold 114. The height H of the semiconductor device assembly 102 may be reduced because the second substrate 104 may be closer to the first substrate 124 than if the window 108 were not otherwise present to receive the first semiconductor device 127 or a portion thereof, which would require a larger gap, which may also be characterized as a spacing between the first semiconductor substrate 124 and the second semiconductor substrate 104. In embodiments where the first semiconductor device package 122 includes a plurality of first semiconductor devices 127, the second substrate 104 may include a plurality of corresponding windows 108 in which at least some semiconductor devices are at least partially interposed, the windows 108 including (and at most) each of the first semiconductor devices 127.

As a specific, non-limiting example, a semiconductor device assembly according to this disclosure can include a first substrate comprising first semiconductor devices on the first substrate and a first array of conductive elements positioned on an upper surface of the first substrate. A second substrate may overlie the first substrate, the second substrate including a second array of conductive elements positioned at a lower surface of the second substrate. At least some of the conductive elements of the second array may be electrically connected to corresponding conductive elements of the first array. A second substrate may include a window extending through the second substrate from the lower surface to an upper surface of the second substrate. A second substrate may be configured to support additional semiconductor devices around a perimeter of the window, at least a portion of an outer perimeter of the first substrate coupled to an inner portion of the second substrate defining the perimeter of the window.

As another particular, non-limiting example, a method of fabricating a semiconductor device assembly according to such invention can involve positioning a processing unit supported on an upper surface of a first substrate at least in part through a window in a second substrate overlying the first substrate. At least some conductive elements of the first array of conductive elements positioned on the upper surface of the first substrate may be electrically connected with at least some corresponding conductive elements of the second array of conductive elements positioned on the lower surface of the second substrate.

Fig. 5 is an enlarged portion of a side view of the semiconductor device assembly 102 shown in fig. 4. The first semiconductor device package 122 may include an array 134 of conductive elements 136 positioned on a lower surface 138 of the first substrate 124, the lower surface 138 being positioned on an opposite side of the first substrate 124 from the upper surface 130. The conductive elements 136 may include structures of other conductive elements such as pads, bumps, balls, pillars, or conductive material exposed at the lower surface 138 of the first substrate 124. At least some of the conductive elements 136 of the array 134 may be electrically connected to corresponding conductive elements 128 of the array 126. For example, the conductive elements 136 of the array 134 and the corresponding conductive elements 128 of the array 126 may be operably connected to each other (e.g., by routing elements, vias) to operably connect the semiconductor device assembly 102 and its various semiconductor devices 106 and 127 (see fig. 3) to another device or structure including, for example, a high-level package (e.g., a motherboard).

Fig. 6 is an enlarged portion of a side view of the semiconductor device assembly 102 shown in fig. 4. In fig. 6, a portion of the second substrate 104 including the window 108 and a portion of the first semiconductor device 127 are specifically shown extending through a portion of the window 108. Additionally, overmold 114 has been omitted for clarity. In some embodiments, such as shown in fig. 6, a plane 142 coplanar with the upper surface 130 of the first semiconductor device 127 may intersect the second substrate 104. Another plane 144 coplanar with the lower surface 110 of the second substrate 104 may intersect the first semiconductor device 127.

In some embodiments, such as the embodiment shown in fig. 6, thermal management structure 140 may be supported on upper surface 130 of first semiconductor device 127. Thermal management structure 140 may include, for example, a heat sink, heat pipe, heat spreader, Peltier cooler, forced air cooler, fluid cooler, or other structure for conducting heat away from first semiconductor device 127. Thermal management structure 140 may be in direct contact with upper surface 130 or may include an optional thermal interface material 146 (e.g., a thermally conductive paste) interposed between thermal management structure 140 and upper surface 130. Because the windows 108 may allow more direct access to the first semiconductor device 127, the thermal management structure 140 may be positioned closer to the first semiconductor device 127, improving heat transfer away from the first semiconductor device 127.

Fig. 7 is a further enlarged perspective view of the electrical connections 148 of the semiconductor device assembly 102 of fig. 4. The thickness T of the electrical connection 148, including the

conductive elements

118 and 128 of the arrays 116 and 126 (see fig. 5), may be less than the thickness of the first semiconductor device 127 (see fig. 6). For example, the thickness T of the electrical connection 148 may be less than about 75% of the thickness of the first semiconductor device 127 (see fig. 6). More particularly, the thickness T of the electrical connection 148 may be, for example, less than about 50% of the thickness of the first semiconductor device 127 (see fig. 6). As a specific, non-limiting example, the thickness T of the electrical connection 148 may be less than about 25% of the thickness of the first semiconductor device 127 (see fig. 6). The reduced thickness T of the electrical connection 148 achieved by inserting at least a portion of the first semiconductor device 127 (see fig. 6) into the window 108 (see fig. 6) as opposed to utilizing a higher electrical connection to provide sufficient space to receive the first semiconductor device between the first substrate and the second substrate can reduce the overall height H (see fig. 4) of the semiconductor device assembly 102 (see fig. 4). As a particular non-limiting example, the

conductive elements

116 and 126 of the

arrays

116 and 126, respectively, may comprise balls of conductive material extending directly from the second substrate 104 to corresponding pads of conductive material that are at least substantially coplanar with the upper surface 132 of the first substrate 124.

Fig. 8 is a bottom perspective view of a portion of the semiconductor device assembly 102 of fig. 4. In some embodiments, the shape of the perimeter of the first substrate 124 may be at least substantially the same as the shape of the perimeter of the second substrate 104 (even though different sizes are shown). For example, in such embodiments, each of the first substrate 124 and the second substrate 104 may be rectangular (e.g., square) in shape.

In addition to providing a larger surface area to accommodate the routing elements 120, the surface area of the second substrate 104 may enable one or more electrical components 150 to be operably connected to the upper surface 112, the lower surface 110, or both. For example, at least one electrical component 150 is operatively connected to a portion of the lower surface 110 of the second substrate 104 that is laterally positioned beyond the perimeter of the first substrate 124. More particularly, the electrical component or the component 150 may be positioned on a bottom side of an overhanging portion of the second substrate 104. The thickness t of each of the electrical components 150 may, for example, be less than or equal to the height h of the first semiconductor device package 122, as measured from the lowermost portion of the conductive elements 136 of the array 134 to the upper surface 132 of the first substrate 124. More particularly, the thickness t of each of the electrical components 150 may be, for example, between about 10% and about 90% of the height h of the first semiconductor device package 122. As a particular non-limiting example, the thickness t of each of the electrical components 150 may be between about 40% and about 60% of the height h of the first semiconductor device package 122. In other embodiments, the thickness t of the one or more electrical components 150 may be, for example, greater than the height h of the first semiconductor device package 122, and any underlying structure may include a groove or window to at least partially receive the electrical component 150 therein. Electrical components 150 may include, for example, resistors, capacitors, inductors, integrated circuits, diodes, transistors, batteries, antennas, switches, and other electrical components operably connectable to a semiconductor device. Providing additional surface area for the electrical components 150 may allow for greater flexibility in the design of the semiconductor device assembly 102 and may reduce the overall surface area of the final product, as the electrical components 150 that would otherwise be positioned on another device or structure, such as a motherboard for example, may instead be included on the bottom side of the substrate 104.

In some embodiments, the one or more structural supports 152 may extend from below the first substrate 124 to the second substrate 104 distal to the geometric center of the second substrate 104. More particularly, the one or more structural supports 152 may extend from beneath the first substrate 124 to the second substrate 104 proximate a perimeter of the second substrate 104. The structural supports 152 may reduce strain on the perimeter of the second substrate 104, which may otherwise be suspended from the first substrate 124. The structural support or the structural supports 152 may include, for example, cylinders, posts, pins, screws, bolts, or other means extending from an underlying structure (e.g., a motherboard) to the second substrate 104. In some embodiments, the structural support 152 may be attached to the second substrate 104. In other embodiments, the structural support 152 may be in contact with or proximate to the lower surface 110 of the second substrate 104 without attaching it to the second substrate 104.

Fig. 9 is a top view of another embodiment of a semiconductor device assembly 202. When the semiconductor device assembly 202 has been completed, it may be operably connected to the underlying device to form a final product. For example, the array 134 (see FIG. 8) may be electrically connected to a mating array on the motherboard 254 to attach the semiconductor device assembly 202 to the motherboard 254 and form the final product. The support structure 152 (see fig. 8), if present, may extend from the motherboard 254 to the substrate 104.

In some embodiments, the shape of the perimeter of the second substrate 204 (see fig. 9) may be different from the shape of the perimeter of the first substrate 124 (see fig. 8). For example, the perimeter of the first substrate 124 (see fig. 8) may be rectangular, while the perimeter of the second substrate 204 may be irregular, similar to a pair of intersecting rectangles. More particularly, the perimeter of the second substrate 204 can extend at least substantially parallel to the corresponding perimeter of the underlying motherboard 254.

While certain illustrative embodiments have been described in connection with the accompanying drawings, those of ordinary skill in the art will recognize and appreciate that the scope of the present invention is not limited to the embodiments explicitly shown and described in the present invention. Rather, many additions, deletions, and modifications to the embodiments described in this disclosure may be made to produce embodiments within the scope of the invention, such as that specifically claimed, including legal equivalents. Furthermore, features from one disclosed embodiment may be combined with features of another disclosed embodiment while still being within the scope of the invention as contemplated by the inventors.

Claims

1. A semiconductor device assembly, comprising:

a first semiconductor device package comprising a first substrate, a first semiconductor device on the first substrate, a thermal management structure supported on an upper surface of the first semiconductor device, and a first array of conductive elements positioned on an upper surface of the first substrate;

a second substrate overlying the first substrate, the second substrate comprising a second array of conductive elements positioned on a lower surface of the second substrate, at least some of the conductive elements of the second array being electrically connected to corresponding conductive elements of the first array, a thickness of the conductive elements measured in a direction at least substantially perpendicular to the lower surface of the second substrate being less than a thickness of the first semiconductor device measured in the direction;

wherein the second substrate comprises a window extending from the lower surface to an upper surface of the second substrate, wherein at least a portion of the thermal management structure is positioned within the window, wherein the second array of conductive elements completely surrounds the window, at least a portion of an outer perimeter of the first substrate being coupled to an inner portion of the second substrate defining the perimeter of the window;

additional semiconductor devices located over the upper surface of the second substrate around a perimeter of the second substrate, the second substrate including routing elements extending from each side of the window toward the additional semiconductor devices around the perimeter of the second substrate; and

at least one electrical component supported on the lower surface of the second substrate laterally beyond a perimeter of the first substrate, the at least one electrical component having a thickness less than a height of the first substrate.

2. The semiconductor device assembly of claim 1, wherein the first semiconductor device extends at least partially through the window such that a plane coplanar with the lower surface of the second substrate intersects the first semiconductor device.

3. The semiconductor device assembly of claim 1, wherein the routing element comprises a line, trace, or via of conductive material.

4. The semiconductor device assembly of claim 1, wherein the thickness of the at least one electrical component is between 40% to 60% of the height of the first substrate.

5. The semiconductor device assembly of claim 1, wherein a surface area of the lower surface of the second substrate is greater than a surface area of the upper surface of the first substrate.

6. The semiconductor device assembly of claim 1, wherein the at least one electrical component comprises at least one of a resistor, a capacitor, an inductor, an integrated circuit, a diode, a transistor, a battery, an antenna, or a switch.

7. The semiconductor device assembly of claim 1, wherein the second array of conductive elements is positioned laterally adjacent the window such that the second array is laterally spaced apart from any additional semiconductor devices on the upper surface of the second substrate and a perimeter of the second substrate.

8. The semiconductor device assembly of claim 7, wherein the additional semiconductor device is configured to be positioned proximate the perimeter of the second substrate.

9. The semiconductor device assembly of claim 8, wherein the additional semiconductor device is configured to be positioned adjacent a corner proximate the perimeter of the second substrate.

10. The semiconductor device assembly of any one of claims 1-9, wherein the thickness of the conductive element is less than 75% of the thickness of the first substrate.

11. The semiconductor device assembly of any one of claims 1-9, wherein a perimeter of the second substrate exhibits a same shape as a perimeter of the first substrate.

12. The semiconductor device assembly of any one of claims 1-9, further comprising a structural support extending from beneath the first substrate to the second substrate distal to a geometric center of the second substrate.

13. The semiconductor device assembly of any one of claims 1-9, wherein the conductive elements of the first and second arrays each comprise a ball of conductive material extending directly from the second substrate to a corresponding pad of conductive material at least substantially coplanar with the upper surface of the first substrate.

14. An assembly of semiconductor device packages, comprising:

a first semiconductor device package, comprising:

a first substrate comprising a first array of conductive elements positioned on an upper surface of the first substrate;

a first semiconductor device on the upper surface of the first substrate; and

a thermal management structure supported on an upper surface of the first semiconductor device; and

a second semiconductor device package supported on the first semiconductor device package, comprising:

a second substrate comprising a second array of conductive elements positioned on a lower surface of the second substrate, a thickness of the conductive elements measured in a direction at least substantially perpendicular to the lower surface of the second substrate being less than a thickness of the first semiconductor device measured in the direction;

a window extending through the second substrate from the lower surface to an upper surface of the second substrate, the second array of conductive elements completely laterally around a perimeter of the window, the second substrate extending laterally beyond the second array of conductive elements;

additional semiconductor devices supported on the upper surface of the second substrate around a perimeter of the second substrate, the additional semiconductor devices being electrically connected to at least some of the conductive elements of the second array by routing elements extending from the additional semiconductor devices around the perimeter of the second substrate towards each side of the window; and

at least one electrical component supported on the lower surface of the second substrate laterally beyond a perimeter of the first substrate, the at least one electrical component having a thickness less than a height of the first substrate;

wherein at least a portion of the thermal management structure is positioned within the window, and wherein at least a portion of an outer perimeter of the first substrate is coupled to an inner portion of the second substrate defining the perimeter of the window.

15. The semiconductor device package assembly of claim 14, further comprising a structural support extending from beneath the first substrate to the second substrate distal to a geometric center of the second substrate.

16. The semiconductor device packaged assembly of claim 14 or 15, wherein the at least one electrical component comprises at least one of a resistor, a capacitor, an inductor, an integrated circuit, a diode, a transistor, a battery, an antenna, or a switch.

17. A method of fabricating a semiconductor device assembly, comprising:

positioning a processing unit supported on an upper surface of a first substrate at least partially through a window in a second substrate overlying the first substrate;

positioning a thermal management structure supported on an upper surface of the processing unit at least partially through the window;

electrically connecting at least some of a first array of conductive elements positioned on the upper surface of the first substrate with at least some of corresponding conductive elements of a second array of conductive elements positioned on a lower surface of the second substrate, the second array of conductive elements completely surrounding the window, the thickness of the conductive elements measured in a direction at least substantially perpendicular to the lower surface of the second substrate being less than the thickness of the first substrate measured in the direction;

supporting at least one electrical component on the lower surface of the second substrate laterally beyond the perimeter of the first substrate, the at least one electrical component having a thickness less than the height of the first substrate; and

supporting additional semiconductor devices on the upper surface of the second substrate around a perimeter of the second substrate, routing elements extending from each side of the window toward the additional semiconductor devices around the perimeter of the second substrate.

18. The method of claim 17, further comprising supporting a portion of the second substrate distal to a geometric center of the second substrate on a structural support extending from beneath the first substrate.

19. The method of claim 17, wherein electrically connecting at least some conductive elements of the first array with at least some corresponding conductive elements of the second array comprises flowing balls of conductive material extending directly from the second substrate to corresponding pads of conductive material at least substantially coplanar with the upper surface of the first substrate to electrically connect the balls of conductive material to the pads.

20. The method of any of claims 17, wherein supporting the at least one electrical component on the lower surface of the second substrate comprises supporting at least one of a resistor, a capacitor, an inductor, an integrated circuit, a diode, a transistor, a battery, an antenna, or a switch on the lower surface of the second substrate.