CN113299629B - Link unit, preparation method thereof and semiconductor packaging structure - Google Patents
Link unit, preparation method thereof and semiconductor packaging structure Download PDFInfo
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- CN113299629B CN113299629B CN202110384194.XA CN202110384194A CN113299629B CN 113299629 B CN113299629 B CN 113299629B CN 202110384194 A CN202110384194 A CN 202110384194A CN 113299629 B CN113299629 B CN 113299629B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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Abstract
The application provides a link unit, a preparation method thereof and a semiconductor packaging structure, wherein the link unit comprises a first medium layer positioned above a substrate; the first interposer comprises at least two first horizontal links which are arranged at intervals, and the two first horizontal links extend towards the outer sides of the link units along opposite directions respectively; a second interposer over the first interposer; the second interposer comprises at least two second horizontal links which are respectively positioned at two sides of the first horizontal link, the second horizontal links are perpendicular to the first horizontal link, and the two second horizontal links respectively extend towards the outer side of the link unit along opposite directions. The link unit respectively arranges the metal links in the upper and lower different film layers, so that the process complexity is reduced, the delay is reduced, and the transmission speed is improved. And the intermediate layer is divided into an active silicon intermediate layer and a passive silicon intermediate layer, so that the yield is improved, and the cost is reduced.
Description
Technical Field
The application relates to the technical field of semiconductor packaging, in particular to a link unit, a preparation method thereof and a semiconductor packaging structure.
Background
A Network on Chip (NoC) is a new communication method of a System on Chip (SoC). It is a major component of multi-core technology. The NoC method brings a brand new communication method on chip, which is significantly better than the performance of the traditional bus system (bus). Traditionally, NOCs are deployed on die (die) of a single chip, but as multi-chip integration technology advances, multiple die are integrated onto a single substrate, providing a platform for die integration. But the coarse pitch substrate interconnect can only provide limited bandwidth compared to on-chip interconnects, thereby reducing efficiency and increasing latency. To address the above issues, 2.5D packaging technology moves NOCs down onto the interposer, with which the system can achieve the yield and flexibility advantages of multi die integration while maintaining a high performance Network On Chip (NOC) architecture for connecting modules in modern socs.
However, the conventional intermediaries are all passive silicon intermediaries, which only contain metal connections, so the intermediaries do not contain active semiconductor devices such as routers, repeaters or FIFO queues. The disadvantage is that routing devices (Logic/gates) must be placed in the chiplet, reducing yield and increasing cost (die area is very expensive). And the passive silicon interposer is long-link, while for long-link, delay is a quadratic relation of distance, resulting in larger delay and lower transmission speed. In addition, it is difficult to implement a high frequency synchronous NOC on a passive silicon interposer because clocks cannot be generated on the passive silicon interposer and a buffer layer cannot be deployed to drive a low jitter clock network.
And the metal links are located in the same layer in the passive silicon interposer, which is another cause of propagation delay.
Disclosure of Invention
Aiming at the problems, the application provides a link unit, a preparation method thereof and a semiconductor packaging structure, and solves the technical problems of transmission delay, low yield and high cost caused by the conventional interposer packaging structure.
In a first aspect, the present application provides a link unit comprising:
a substrate:
a first interposer over the substrate; the first interposer comprises at least two first horizontal links which are arranged at intervals, and the two first horizontal links extend towards the outer sides of the link units along opposite directions respectively;
a second interposer over the first interposer; the second interposer comprises at least two second horizontal links which are respectively positioned at two sides of the first horizontal link, the second horizontal links are perpendicular to the first horizontal link, and the two second horizontal links respectively extend towards the outer side of the link unit along opposite directions;
at least two first pads and at least two second pads located over the second interposer;
Each first bonding pad is electrically connected with each first horizontal link through a first contact plug, and each second bonding pad is electrically connected with each second horizontal link through a second contact plug.
In some embodiments, in the above link unit, the first interposer further includes:
a first insulating layer over the substrate; wherein the first horizontal link is located within the first insulating layer surface;
a second insulating layer over the first insulating layer.
In some embodiments, in the above link unit, the first horizontal link includes:
a first metal layer;
a first seed layer located between the first metal layer and the first insulating layer.
In some embodiments, in the above link unit, the second interposer further includes:
a third insulating layer over the second insulating layer; wherein the second horizontal link is located within the third insulating layer surface;
and a fourth insulating layer over the third insulating layer.
In some embodiments, in the above link unit, the second horizontal link includes:
a second metal layer;
a second seed layer located between the second metal layer and the third insulating layer.
In some embodiments, in the above link unit, the first contact plug penetrates through the fourth insulating layer, the third insulating layer, and the second insulating layer.
In some embodiments, in the above link unit, the first contact plug includes:
a third seed layer in contact with the second insulating layer and the first horizontal link;
a third metal layer over the third seed layer.
In some embodiments, in the above link unit, the second contact plug penetrates through the fourth insulating layer.
In some embodiments, in the above link unit, the second contact plug includes:
a fourth seed layer in contact with the fourth insulating layer and the second horizontal link;
a fourth metal layer over the fourth seed layer.
In some embodiments, the above link unit further includes:
a fifth insulating layer over the second interposer;
and the fifth insulating layer is provided with a pad opening above the first contact plug and the second contact plug, and the first pad and the second pad are arranged in the pad opening and extend to the upper surface of the fifth insulating layer.
In some embodiments, in the above link unit, the materials of the first pad and the second pad include a barrier metal layer.
In a second aspect, the present application provides a method for preparing a link unit, including:
providing a substrate:
forming a first interposer over the substrate; the first interposer comprises at least two first horizontal links which are arranged at intervals, and the two first horizontal links extend towards the outer sides of the link units along opposite directions respectively;
forming at least two first contact plugs on the first interposer;
forming a second interposer over the first interposer; the second interposer comprises at least two second horizontal links which are respectively positioned at two sides of the first horizontal link, the second horizontal links are perpendicular to the first horizontal link, and the two second horizontal links respectively extend towards the outer side of the link unit along opposite directions;
forming at least two second contact plugs on the second interposer;
forming a first pad and a second pad over the second interposer at the first contact plug and the second contact plug locations, respectively;
Each first bonding pad is electrically connected with each first horizontal link through the first contact plug, and each second bonding pad is electrically connected with each second horizontal link through the second contact plug.
In some embodiments, in the method for manufacturing a link unit, forming a first interposer above the substrate includes the following steps:
forming an insulating layer over the substrate;
forming the first horizontal link within the first insulating layer surface;
a second insulating layer is formed over the first insulating layer.
In some embodiments, in the method for manufacturing a link unit, the forming the first horizontal link in the surface of the first insulating layer includes the following steps:
forming a first opening in a surface of the first insulating layer;
forming a first seed layer on the side wall and the bottom of the first opening;
and filling a first metal layer in the first opening to form the first horizontal link.
In some embodiments, in the method for manufacturing a link unit, at least two first contact plugs are formed on the first interposer, including the following steps:
forming at least two first through holes penetrating through the second insulating layer; wherein the bottom of the first through hole is in contact with the first horizontal link;
Forming a third seed layer on the side wall and the bottom of the first through hole;
forming a third metal layer in the first through hole to form a first contact plug; wherein the thickness of the third metal layer is greater than the total thickness of the second insulating layer and the second interposer.
In some embodiments, in the method for manufacturing a link unit, forming a second interposer above the first interposer includes the following steps:
forming a third insulating layer over the second insulating layer;
forming the second horizontal link within the third insulating layer surface;
forming a fourth insulating layer over the third insulating layer; wherein the first contact plug penetrates through the third insulating layer and the fourth insulating layer.
In some embodiments, in the method for manufacturing a link unit, the forming the second horizontal link in the surface of the third insulating layer includes the following steps:
forming a second opening in the third insulating layer surface;
forming a second seed layer on the side wall and the bottom of the second opening;
and filling a second metal layer in the second opening to form the second horizontal link.
In some embodiments, in the method for manufacturing a link unit, at least two second contact plugs are formed on the second interposer, including the following steps:
Forming at least two second through holes penetrating through the fourth insulating layer; wherein the bottom of the second through hole is in contact with the second horizontal link;
forming a fourth seed crystal layer on the side wall and the bottom of the second through hole;
forming a fourth metal layer in the second through hole; wherein the thickness of the fourth metal layer is greater than the thickness of the fourth insulating layer.
In some embodiments, in the method for manufacturing a link unit, after the step of forming at least two second contact plugs on the second interposer, the method further includes:
forming a fifth insulating layer over the second interposer;
and forming a pad opening above the first contact plug and the second contact plug on the fifth insulating layer.
In some embodiments, in the method for manufacturing a link unit, a first pad and a second pad are formed above the second interposer at the first contact plug and the second contact plug, respectively, and the method includes the following steps:
forming a first bonding pad and a second bonding pad in the bonding pad openings corresponding to the first contact plug and the second contact plug respectively;
wherein the first pad and the second pad extend to an upper surface of the fifth insulating layer.
In a third aspect, the present application provides a semiconductor package structure, including:
packaging a substrate;
a passive silicon interposer over the package substrate; wherein the passive silicon interposer comprises a plurality of link units according to any one of the first aspect or link units prepared by the preparation method according to any one of the second aspect, and each link unit is connected with each other through a first horizontal link and a second horizontal link;
an active silicon interposer over the passive silicon interposer; the active silicon interposer is electrically connected with the first bonding pad and the second bonding pad of the link unit through the first micro-bump;
a processing unit located above the active silicon interposer; the processing unit is electrically connected with the active silicon intermediate layer through a second micro-bump.
In some embodiments, in the semiconductor package structure, the active silicon interposer includes:
a first redistribution layer over the first micro bump; the first redistribution layer comprises a plurality of first interconnection parts, and the first interconnection parts are electrically connected with the first micro-bumps;
an active device located above the first redistribution layer; wherein the active device is electrically connected to the first interconnect;
A second redistribution layer over the active device; the second redistribution layer comprises a plurality of second interconnection parts, and the upper and lower ends of the second interconnection parts are respectively and electrically connected with the second micro-bumps and the active device.
One or more embodiments of the above-described solution may have the following advantages or benefits compared to the prior art:
the application provides a link unit, a preparation method thereof and a semiconductor packaging structure, wherein the link unit comprises a first medium layer positioned above a substrate; the first interposer comprises at least two first horizontal links which are arranged at intervals, and the two first horizontal links extend towards the outer sides of the link units along opposite directions respectively; a second interposer over the first interposer; the second interposer comprises at least two second horizontal links which are respectively positioned at two sides of the first horizontal link, the second horizontal links are perpendicular to the first horizontal link, and the two second horizontal links respectively extend towards the outer side of the link unit along opposite directions; each first bonding pad is electrically connected with each first horizontal link through a first contact plug, and each second bonding pad is electrically connected with each second horizontal link through a second contact plug. The link unit respectively arranges the metal links in the upper and lower different film layers, so that the process complexity is reduced, the delay is reduced, and the transmission speed is improved. And the intermediate layer is divided into an active silicon intermediate layer and a passive silicon intermediate layer, and active devices can be arranged in the active silicon intermediate layer, so that the number of active devices arranged in a small chip is reduced, the yield is improved, and the cost is reduced.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate the application and, together with the description, do not limit the application. In the drawings:
FIG. 1 is a schematic top view of a NOC system;
FIG. 2 is a schematic diagram of a front view of a link unit according to an exemplary embodiment of the present application;
FIG. 3 is a schematic top view of a first interposer in a link unit according to an exemplary embodiment of the present application;
FIG. 4 is a schematic top view of a second interposer in a link unit according to an exemplary embodiment of the present application;
fig. 5 is a schematic cross-sectional structure of a link unit according to an exemplary embodiment of the present application;
fig. 6 is a schematic structural view of a semiconductor package structure according to an exemplary embodiment of the present application;
FIG. 7 is a schematic cross-sectional view of an active silicon interposer in a semiconductor package structure according to an exemplary embodiment of the present application;
FIG. 8 is a schematic diagram illustrating the connection of a passive silicon interposer and an active silicon interposer in a semiconductor package structure according to an exemplary embodiment of the present application;
FIG. 9 is a schematic flow chart of a method for preparing a link unit according to an exemplary embodiment of the present application;
FIG. 10 is a flowchart illustrating a method for preparing a first interposer in a link unit according to an exemplary embodiment of the present disclosure;
fig. 11 to 15 are schematic cross-sectional structures of intermediate structures formed by relevant steps of a method for manufacturing a first interposer in a link unit according to an exemplary embodiment of the present application;
fig. 16 to 21 are schematic cross-sectional structures of intermediate structures formed by related steps of a method for manufacturing a first contact plug in a link unit according to an exemplary embodiment of the present application;
FIG. 22 is a flowchart illustrating a method for preparing a second interposer in a link unit according to an exemplary embodiment of the present disclosure;
fig. 23 to 26 are schematic cross-sectional structures of intermediate structures formed by relevant steps of a method for preparing a second interposer in a link unit according to an exemplary embodiment of the present application;
fig. 27 to 32 are schematic cross-sectional structures of intermediate structures formed by related steps of a method for manufacturing a second contact plug in a link unit according to an exemplary embodiment of the present application;
in the drawings, wherein like parts are designated by like reference numerals throughout, the drawings are not to scale;
1-node; 2-links; 3-bonding pads; a 10-link unit; 11-a substrate; 12-a first interposer; 121-a first horizontal link; 1212-a first metal layer; 1211-a first seed layer; 122-a first insulating layer; 1221-a first silicon oxide layer; 1222-a silicon nitride layer; 1223-a second silicon dioxide layer; 123-a second insulating layer; 1231-inorganic layer; 1232-organic layer; 13-a second interposer; 131-a second horizontal link; 1311-a second seed layer; 1312-a second metal layer; 132-a third insulating layer; 1321-insulating layer; 1322-insulating layer; 133-a fourth insulating layer; 1331-an inorganic layer; 1332-organic layer; 14-a fifth insulating layer; 15-a first contact plug; 151-a third seed layer; 152-a third metal layer; 16-a first bonding pad; 17-a second contact plug; 171-a fourth seed layer; 172-fourth metal layers; 18-a second bonding pad; 20-packaging a substrate; 30-an active silicon interposer; 31-first micro bumps; 32-a first redistribution layer; 33-active devices; 34-a second redistribution layer; 35-through silicon vias; 40-a processing unit; 41-second micro bumps; 50-third microbumps.
Detailed Description
The following will describe embodiments of the present application in detail with reference to the drawings and examples, thereby how to apply technical means to the present application to solve technical problems, and realizing processes achieving corresponding technical effects can be fully understood and implemented accordingly. The embodiments and the features in the embodiments can be combined with each other under the condition of no conflict, and the formed technical schemes are all within the protection scope of the application. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that, although the terms "first," "second," "third," etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
It will be understood that spatially relative terms, such as "above," "located above," "below," "located below," and the like, may be used herein for convenience of description to describe one element or feature as illustrated in the figures as connected with another element or feature. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the present application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present application. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of the regions illustrated herein, but include deviations in shapes that result, for example, from manufacturing.
For a thorough understanding of the present application, detailed structures and steps are set forth in the following description in order to illustrate the technical solutions set forth herein. Preferred embodiments of the present application are described in detail below, however, the present application may have other implementations in addition to these detailed descriptions.
The structure of the NOC system is shown in fig. 1, the NOC system comprises a plurality of nodes 1 (link sets), the nodes 1 (link sets) are connected with each other through metal links 2, each node 1 (link set) sets 4 links 2, and each link 2 is provided with a bonding pad 3 for realizing connection with active devices such as a router.
Example 1
Referring to fig. 2, the present embodiment provides a link unit 10, including: the substrate 11, the first interposer 12, the second interposer 13, the fifth insulating layer 14, the first contact plug 15, the second contact plug 17, the first pad 16, and the second pad 18.
The first interposer 12 is located above the substrate 11, and the first interposer 12 includes at least two first horizontal links 121 disposed at intervals, and the two first horizontal links 121 extend toward the outside of the link unit 10 in opposite directions (+y and-Y, i.e., a horizontal south direction and a horizontal north direction), respectively, as shown in fig. 3.
The second interposer 13 is located above the first interposer 12, and the second interposer 13 includes at least two second horizontal links 131 located on both sides of the first horizontal link 121, respectively, the second horizontal links 131 being perpendicular to the first horizontal link 121, and the two second horizontal links 131 extending toward the outside of the link unit 10 in opposite directions (+x and-X, i.e., horizontal east and west directions), respectively, as shown in fig. 4.
There is no contact between the first horizontal link 121 and the second horizontal link 131.
Therefore, the link unit 10 respectively sets the metal links in the upper and lower different film layers, and the different film layers are less limited by the process, so that the delay can be reduced, and the transmission speed can be improved. The reduction in delay, thereby enabling the NOC system to have higher NOC frequencies and greater transmission distances.
The fifth insulating layer 14 is located above the second interposer 13, and the fifth insulating layer 14 is provided with pad openings (not labeled in the figure) above the first contact plugs 15 and the second contact plugs 17, and the first pads 16 and the second pads 18 are disposed in the pad openings and extend to the upper surface of the fifth insulating layer 14.
At least two first pads 16 and at least two first contact plugs are provided, and each first pad 16 is electrically connected to each first horizontal link 121 through the first contact plug 15.
At least two second pads 18 and second contact plugs are provided, and each second pad 18 is electrically connected to each second horizontal link 131 through the second contact plug 17.
As shown in fig. 5, the first interposer 12 includes, in addition to the first horizontal link 121: a first insulating layer 122 and a second insulating layer 123.
Wherein the first insulating layer 122 is located above the substrate 11, and the first horizontal link 121 is located in the surface of the first insulating layer 122.
Specifically, the first insulating layer 122 includes a first silicon oxide layer 1221, a silicon nitride layer 1222, and a second silicon oxide layer 1223 stacked in this order, the first horizontal link 121 is disposed in the opening of the second silicon oxide layer 1223, the upper surface of the first horizontal link 121 is flush with the upper surface of the second silicon oxide layer 1223, and the lower surface of the first horizontal link 121 is in contact with the upper surface of the silicon nitride layer 1222.
The second insulating layer 123 is located above the first insulating layer 122, and specifically, the second insulating layer 123 includes an inorganic layer 1231 and an organic layer 1232 located above the inorganic layer 1231 for improving adhesion between the first interposer 12 and the second interposer 13.
The first horizontal link 121 includes: a first metal layer 1212, and a first seed layer 1211 between the first metal layer 1212 and the first insulating layer 122. The first seed layer 1211 is located at the sidewall and bottom of the opening of the second silicon oxide layer 1223, the first metal layer 1212 is filled in the opening, and the upper surface of the first metal layer 1212 is flush with the upper surface of the first insulating layer 122 (the second silicon oxide layer 1223). The material of the first metal layer 1212 includes electrolytic copper plating.
Similarly, the second interposer 13 includes, in addition to the second horizontal link 131: a third insulating layer 132 and a fourth insulating layer 133.
Wherein the third insulating layer 132 is located above the second insulating layer 123, and the second horizontal link 131 is located within the surface of the third insulating layer 132.
Specifically, the third insulating layer 132 includes an insulating layer 1321 and an insulating layer 1322 that are sequentially stacked, the second horizontal link 131 is disposed in an opening of the insulating layer 1322, an upper surface of the second horizontal link 131 is flush with an upper surface of the insulating layer 1322, and a lower surface of the second horizontal link 131 is in contact with an upper surface of the insulating layer 1321.
The fourth insulating layer 133 is over the third insulating layer 132, and the fourth insulating layer 133 includes an inorganic layer 1331 and an organic layer 1332.
The second horizontal link 131 includes: a second metal layer 1312, and a second seed layer 1311 located between the second metal layer 1312 and the third insulating layer 132. The second seed layer 1311 is located at the side wall and bottom of the opening of the insulating layer 1322, the first metal layer 1212 is filled in the opening, and the upper surface of the second metal layer 1312 is flush with the upper surface of (the insulating layer 1322 of) the third insulating layer 132. The material of the first metal layer 1212 includes electrolytic copper plating.
The first contact plug 15 penetrates the fourth insulating layer 133, the third insulating layer 132, and the second insulating layer 123 in this order from top to bottom. The height of the first contact plug 15 is greater than the total thickness of the fourth insulating layer 133, the third insulating layer 132, and the second insulating layer 123, so that the first pad 16 may be in contact with the first contact plug 15 through a pad opening on the fifth insulating layer 14 to achieve electrical connection.
The first contact plug 15 includes: a third seed layer 151 and a third metal layer 152 over the third seed layer 151. The second insulating layer 123 is provided with a via hole over the first horizontal link 121, and the third seed layer 151 is disposed at the sidewall and bottom of the via hole and contacts the first horizontal link 121.
The second contact plug 17 penetrates the fourth insulating layer 133, and the height of the second contact plug 17 is greater than the thickness of the fourth insulating layer 133, so that the second pad 18 may contact the second contact plug 17 through a pad opening on the fifth insulating layer 14 to achieve electrical connection.
The second contact plug 17 includes: a fourth seed layer 171, and a fourth metal layer 172 over the fourth seed layer 171. The fourth insulating layer 133 is provided with a via hole over the second horizontal link 131, and the fourth seed layer 171 is disposed at a sidewall and a bottom of the via hole and contacts the second horizontal link 131.
The material of the first pad 16 and the second pad 18 includes a barrier metal layer. The first pad 16 and the second pad 18 are used to make connections to other components.
The present embodiment provides a link unit 10, where the link unit 10 includes a first interposer 12 above a substrate 11; the first interposer 12 includes at least two first horizontal links 121 disposed at intervals, and the two first horizontal links 121 extend toward the outside of the link unit 10 in opposite directions; a second interposer 13 located above the first interposer 12; the second interposer 13 includes at least two second horizontal links 131 respectively located at two sides of the first horizontal link 121, the second horizontal links 131 are perpendicular to the first horizontal link 121, and the two second horizontal links 131 respectively extend towards the outside of the link unit 10 along opposite directions; each first pad 16 is electrically connected to each first horizontal link 121 through a first contact plug 15, and each second pad 18 is electrically connected to each second horizontal link 131 through a second contact plug 17. The link unit 10 is provided with the metal links in the upper and lower different film layers respectively, so that delay can be reduced, and transmission speed can be improved.
Example two
Referring to fig. 6, the first embodiment provides a semiconductor package structure, which includes: package substrate 20, passive silicon interposer, active silicon interposer 30, and processing unit 40.
The passive silicon interposer is located above the package substrate 20, and the passive silicon interposer includes a plurality of link units 10, and the structure of the link units 10 is described in the first embodiment, which is not repeated here. Wherein the respective link units 10 are connected to each other through a first horizontal link 121 and a second horizontal link 131.
The passive silicon interposer and the package substrate 20 are connected by a third micro bump 50.
An active silicon interposer 30 is located over the passive silicon interposer. Active silicon interposer technology is an alternative to passive silicon interposers in which the interposer is fabricated from standard CMOS processes (adding die thinning and through silicon via insertion techniques).
As shown in fig. 7, the active silicon interposer 30 includes: a first micro bump 31, a first redistribution layer 32, an active device 33, and a second redistribution layer 34.
As shown in fig. 8, the active silicon interposer 30 is electrically connected to the first pads 16 and the second pads 18 of the link cells 10 in the passive silicon interposer by the first micro bumps 31.
The first redistribution layer 32 is located above the first micro bump 31, and the first redistribution layer 32 includes a plurality of first interconnects 321, where the first interconnects 321 are electrically connected to the first micro bump 31.
The active device 33 is located above the first redistribution layer 32, and the active device 33 is electrically connected to the first interconnect 321. The active device 33 is electrically connected to the first micro bump 31 on both sides of the link unit 10 through-silicon vias 35 (Through Silicion Via, TSVs) for connection to a power supply.
The active devices 33 include routers, repeaters, and the like.
The router is called a communication node and is responsible for data communication between the resource nodes. The routers are responsible for communication in the NOC longitudinal direction, and the NOC network is made up of individual router nodes, each router being connected to a processor core or memory.
The NOC link may utilize routers to reduce propagation delay by deploying active devices 33 (in this case routers or repeaters) in the interposer, with long wire delays reduced from quadratic to linear in length. The reduction in delay, thereby enabling the NOC system to have higher NOC frequencies and greater transmission distances. In addition, the router is disposed in the interposer, avoiding the use of microbump capacitance and capacitance of electrostatic discharge (ESD) protection circuitry that is necessary to protect the chiplet interface during bonding, thereby reducing delay. And the active devices are arranged in the active silicon intermediate layer, so that the number of the active devices arranged in the small chip is reduced, the yield is improved, and the cost is reduced.
The second redistribution layer 34 is located above the active device 33, and the second redistribution layer 34 includes a plurality of second interconnects 341, where upper and lower ends of the second interconnects 341 are electrically connected to the second micro bumps 41 and the active device 33, respectively.
The processing unit 40 is located above the active silicon interposer 30, and the processing unit 40 is electrically connected to the active silicon interposer 30 through the second micro bump 41.
Embodiments of the present application provide a semiconductor package structure including a package substrate 20; a passive silicon interposer over the package substrate 20; wherein the passive silicon interposer comprises a number of link units 10; an active silicon interposer 30 located over the passive silicon interposer; wherein the active silicon interposer 30 is electrically connected to the first pads 16 and the second pads 18 of the passive silicon interposer through the first micro bumps 31; a processing unit 40 located above the active silicon interposer 30; wherein the processing unit 40 is electrically connected to the active silicon interposer 30 through the second micro bump 41. By the arrangement of the active silicon interposer, the cost is reduced, and the NOC link can utilize active devices to reduce transmission delay, so that the NOC system has higher NOC frequency and longer transmission distance.
Example III
On the basis of the first embodiment, this embodiment provides a method for manufacturing a link unit 10,
Fig. 9 is a schematic flow chart of a preparation method of the link unit 10 according to the embodiment of the present application.
As shown in fig. 9, the method for preparing the link unit 10 of the present embodiment includes the following steps:
step S110: a substrate 11 is provided.
Step S120: forming a first interposer 12 over a substrate 11; the first interposer 12 includes at least two first horizontal links 121 disposed at intervals, and the two first horizontal links 121 extend toward the outside of the link unit 10 in opposite directions.
As shown in fig. 10, in step S120, the first interposer 12 is formed over the substrate 11, and includes the following steps:
s122: as shown in fig. 11, an insulating layer 122 is formed over the substrate 11;
s124: as shown in fig. 12 to 14, a first horizontal link 121 is formed in the surface of the first insulating layer 122;
s126: as shown in fig. 15, a second insulating layer 123 is formed over the first insulating layer 122.
The first insulating layer 122 includes a first silicon oxide layer 1221, a silicon nitride layer 1222, and a second silicon oxide layer 1223, which are sequentially stacked.
Step S124 includes the steps of:
s124a: as shown in fig. 12, a first opening is formed in the surface of the first insulating layer 122;
s124b: as shown in fig. 13, a first seed layer 1211 is formed on the sidewalls and bottom of the first opening;
S124c: as shown in fig. 14, the first metal layer 1212 is filled in the first opening to form the first horizontal link 121.
Specifically, in step S124a, a photoresist 124 is first coated over the first insulating layer 122, then an etching window is formed by exposure and development, then an opening is formed on the second silicon oxide layer 1223 of the first insulating layer 122 through an etching process, the bottom of the opening is in contact with the upper surface of the silicon nitride layer 1222, and then the remaining photoresist 124 is removed.
Subsequently, in step S124b, the first seed layer 1211 is formed by a sputtering process.
Subsequently, in step S124c, a first metal layer 1212 is formed over the first seed layer 1211 by an electrochemical plating process using the first seed layer 1211 as a power supply layer, and the thickness of the first metal layer 1212 is greater than or equal to the depth of the opening in the silicon dioxide layer 1223, such that the first metal layer 1212 fills the opening.
After step S124c, the method further includes: the first metal layer 1212 is planarized by a Chemical Mechanical Polishing (CMP) process, and portions of the first metal layer 1212 and the first seed layer 1211 that extend beyond the openings are removed such that the upper surface of the remaining first metal layer 1212 is flush with the upper surface of the first insulating layer 122 (the second silicon oxide layer 1223).
The second insulating layer 123 includes an inorganic layer 1231 and an organic layer 1232 located above the inorganic layer 1231 for improving adhesion between the first interposer 12 and the second interposer 13.
Step S130: at least two first contact plugs 15 are formed on the first interposer 12.
Specifically, step S130 includes the following steps:
s130a: as shown in fig. 16 and 17, at least two first through holes (not labeled in the drawings) penetrating the second insulating layer 123 are formed; wherein the bottom of the first via is in contact with the first horizontal link 121;
s130b: as shown in fig. 18, a third seed layer 151 is formed on the sidewall and bottom of the first via hole;
s130c: forming a third metal layer 152 in the first via hole as in fig. 19 to 21 to form a first contact plug 15; wherein the thickness of the third metal layer 152 is greater than the total thickness of the second insulating layer 123 and the second interposer 13.
In step S130a, since the upper layer of the second insulating layer 123 is the organic layer 1232, the organic layer 1232 may be directly exposed and developed to form an etching window, and then the first via hole is formed on the second insulating layer 123 through an etching process.
In step S130c, in order to form the third metal layer 152 having a thickness greater than the total thickness of the second insulating layer 123 and the second intermediate layer 13, after the third seed layer 151 is formed, as shown in fig. 19, the plating resist 125 (having a thickness greater than the thickness of the second intermediate layer 13) is formed over the second insulating layer 123 where the third metal layer 152 is not required, only the third seed layer 151 on the sidewall and the bottom of the first via hole is exposed, and then electrochemical plating is performed using the third seed layer 151 as a power supply layer, and the third metal layer 152 having a thickness greater than the total thickness of the second insulating layer 123 and the second intermediate layer 13 is formed over the third seed layer 151 in the first via hole, as shown in fig. 20.
Subsequently, as shown in fig. 21, the plating resist 125 and the third seed layer 151 thereunder are removed.
Step S140: forming a second interposer 13 over the first interposer 12; the second interposer 13 includes at least two second horizontal links 131 respectively located at two sides of the first horizontal link 121, the second horizontal links 131 are perpendicular to the first horizontal link 121, and the two second horizontal links 131 respectively extend toward the outside of the link unit 10 along opposite directions.
Specifically, as shown in fig. 22, in step S140, the second interposer 13 is formed over the first interposer 12, including the steps of:
s142: as shown in fig. 23, a third insulating layer 132 is formed over the second insulating layer 123;
s144: as shown in fig. 24 and 25, a second horizontal link 131 is formed in the surface of the third insulating layer 132;
s146: as shown in fig. 26, a fourth insulating layer 133 is formed over the third insulating layer 132; wherein the first contact plug 15 penetrates the third insulating layer 132 and the fourth insulating layer 133.
Wherein the third insulating layer 132 includes an insulating layer 1321 and an insulating layer 1322 stacked in this order
Wherein, step S144 includes the following steps:
s144a: as shown in fig. 24, a second opening is formed in the surface of the third insulating layer 132;
S144b: forming a second seed layer 1311 on sidewalls and bottom of the second opening;
s144c: as shown in fig. 25, a second metal layer 1312 is filled in the second opening to form a second horizontal link 131.
Specifically, in step S144a, the photoresist 134 is first coated over the third insulating layer 132, then an etching window is formed through exposure and development, then an opening is formed on the insulating layer 1322 of the third insulating layer 132 through an etching process, the bottom of the opening is in contact with the upper surface of the insulating layer 1321, and then the remaining photoresist 134 is removed.
Subsequently, in step S144b, the second seed layer 1311 is formed by a sputtering process.
Subsequently, in step S144c, a second metal layer 1312 is formed over the second seed layer 1311 by an electrochemical plating process using the second seed layer 1311 as a power supply layer, and the thickness of the second metal layer 1312 is greater than or equal to the depth of the opening in the insulating layer 1322, so that the opening is filled with the second metal layer 1312.
After step S124c, the method further includes: portions of the second metal layer 1312 and the second seed layer 1311 that extend beyond the openings are removed so that the upper surface of the remaining second metal layer 1312 is flush with the upper surface of the third insulating layer 132 (insulating layer 1322).
It should be noted that, the first contact plug 15 penetrates the third insulating layer 132 and the fourth insulating layer 133, and the film deposited on the upper surface of the first contact plug 15 needs to be removed during or after the formation of the second interposer 13.
Step S150: at least two second contact plugs 17 are formed on the second interposer 13.
Specifically, step S150 includes the following steps:
s150a: as shown in fig. 27 and 28, at least two second through holes (not labeled in the drawings) penetrating the fourth insulating layer 133 are formed; wherein the bottom of the second via hole is in contact with the second horizontal link 131;
s150b: as shown in fig. 29, a fourth seed layer 171 is formed on the sidewalls and bottom of the second via hole;
s150c: as shown in fig. 30 to 32, a fourth metal layer 172 is formed in the second via hole; wherein the thickness of the fourth metal layer 172 is greater than the total thickness of the fourth insulating layer 133.
In step S150a, the fourth insulating layer 133 includes the inorganic layer 1331 and the organic layer 1332, so that the organic layer 1332 may be directly exposed and developed to form an etching window, and then a via hole is formed on the fourth insulating layer 133 through an etching process.
In step S150c, in order to form the fourth metal layer 172 having a thickness greater than that of the fourth insulating layer 133, after the fourth seed layer 171 is formed, as shown in fig. 30, the plating resist 135 is formed over the fourth insulating layer 133 where the fourth metal layer 172 is not required, only the fourth seed layer 171 on the sidewall and bottom of the second via hole is exposed, and then electrochemical plating is performed using the fourth seed layer 171 as a power supply layer, and the fourth metal layer 172 having a thickness greater than that of the fourth insulating layer 133 is formed over the fourth seed layer 171 in the second via hole, as shown in fig. 31.
Subsequently, as shown in fig. 32, the plating resist 135 and the fourth seed layer 171 thereunder are removed.
Similarly, during or after the formation of the second contact plug 17, the film deposited on the upper surface of the first contact plug 15 needs to be removed.
It should be noted that, after step S150, the method further includes: forming a fifth insulating layer 14 over the second interposer 13; a pad opening is formed over the first contact plug 15 and the second contact plug 17 on the fifth insulating layer 14.
Step S160: forming a first pad 16 and a second pad 18 above the second interposer 13 at the positions of the first contact plug 15 and the second contact plug 17, respectively; wherein each first pad 16 is electrically connected to each first horizontal link 121 through a first contact plug 15, and each second pad 18 is electrically connected to each second horizontal link 131 through a second contact plug 17.
In the case of including the fifth insulating layer 14, the first pads 16 and the second pads 18 are disposed within the pad openings of the fifth insulating layer 14 and extend to the upper surface of the fifth insulating layer 14.
The resulting structure is shown in fig. 5.
The material of the first pad 16 and the second pad 18 includes a barrier metal layer. The first pad 16 and the second pad 18 are used to make connections to other components.
It should be noted that, the method for preparing the link unit 10 is not limited to the above method, wherein the first contact plug 15 and the second contact plug 17 may be formed by performing the process synchronously after the deposition of the fourth insulating layer 133 of the second interposer 13, and the flow of the preparation method after the fourth insulating layer 133 may be: depositing the fourth insulating layer 133, forming contact holes, filling metal to form the first contact plug 15 and the second contact plug 17, depositing the fifth insulating layer 14, and forming the first pad 16 and the second pad 18.
The embodiment of the application provides a method for preparing a link unit 10, which comprises the steps of forming a first interposer 12 above a substrate 11; the first interposer 12 includes at least two first horizontal links 121 disposed at intervals, and the two first horizontal links 121 extend toward the outside of the link unit 10 in opposite directions; forming at least two first contact plugs 15 on the first interposer 12; forming a second interposer 13 over the first interposer 12; the second interposer 13 includes at least two second horizontal links 131 respectively located at two sides of the first horizontal link 121, the second horizontal links 131 are perpendicular to the first horizontal link 121, and the two second horizontal links 131 respectively extend toward the outside of the link unit 10 along opposite directions. The link unit 10 respectively arranges the metal links in the upper and lower different film layers, so that the process complexity is reduced, the delay is reduced, and the transmission speed is improved.
Although the embodiments disclosed in the present application are described above, the embodiments are only used for the convenience of understanding the present invention, and are not intended to limit the present invention. Any person skilled in the art to which this application pertains will be able to make any modifications and variations in form and detail of implementation without departing from the spirit and scope of the disclosure, but the scope of the invention shall be subject to the scope of the appended claims.
Claims (22)
1. A link unit comprising:
a substrate:
a first interposer over the substrate; the first interposer comprises at least two first horizontal links which are arranged at intervals, and the two first horizontal links extend towards the outer sides of the link units along opposite directions respectively;
a second interposer over the first interposer; the second interposer comprises at least two second horizontal links which are respectively positioned at two sides of the first horizontal link, the second horizontal links are perpendicular to the first horizontal link, and the two second horizontal links respectively extend towards the outer side of the link unit along opposite directions;
At least two first pads and at least two second pads located over the second interposer;
each first bonding pad is electrically connected with each first horizontal link through a first contact plug, and each second bonding pad is electrically connected with each second horizontal link through a second contact plug.
2. The link unit of claim 1, wherein the first interposer further comprises:
a first insulating layer over the substrate; wherein the first horizontal link is located within the first insulating layer surface;
a second insulating layer over the first insulating layer.
3. The link unit of claim 2, wherein the first horizontal link comprises:
a first metal layer;
a first seed layer located between the first metal layer and the first insulating layer.
4. The link unit of claim 2, wherein the second interposer further comprises:
a third insulating layer over the second insulating layer; wherein the second horizontal link is located within the third insulating layer surface;
and a fourth insulating layer over the third insulating layer.
5. The link unit of claim 4, wherein the second horizontal link comprises:
a second metal layer;
a second seed layer located between the second metal layer and the third insulating layer.
6. The link unit of claim 4, wherein the first contact plug penetrates the fourth insulating layer, the third insulating layer, and the second insulating layer.
7. The link unit according to claim 6, wherein the first contact plug includes:
a third seed layer in contact with the second insulating layer and the first horizontal link;
a third metal layer over the third seed layer.
8. The link unit of claim 5, wherein the second contact plug penetrates the fourth insulating layer.
9. The link unit according to claim 8, wherein the second contact plug includes:
a fourth seed layer in contact with the fourth insulating layer and the second horizontal link;
a fourth metal layer over the fourth seed layer.
10. The link unit of claim 1, further comprising:
a fifth insulating layer over the second interposer;
And the fifth insulating layer is provided with a pad opening above the first contact plug and the second contact plug, and the first pad and the second pad are arranged in the pad opening and extend to the upper surface of the fifth insulating layer.
11. The link cell of claim 1 wherein the material of the first and second pads comprises a barrier metal layer.
12. A method of making a link unit comprising:
providing a substrate:
forming a first interposer over the substrate; the first interposer comprises at least two first horizontal links which are arranged at intervals, and the two first horizontal links extend towards the outer sides of the link units along opposite directions respectively;
forming at least two first contact plugs on the first interposer;
forming a second interposer over the first interposer; the second interposer comprises at least two second horizontal links which are respectively positioned at two sides of the first horizontal link, the second horizontal links are perpendicular to the first horizontal link, and the two second horizontal links respectively extend towards the outer side of the link unit along opposite directions;
Forming at least two second contact plugs on the second interposer;
forming a first pad and a second pad over the second interposer at the first contact plug and the second contact plug locations, respectively;
each first bonding pad is electrically connected with each first horizontal link through the first contact plug, and each second bonding pad is electrically connected with each second horizontal link through the second contact plug.
13. The method of manufacturing of claim 12, wherein forming a first interposer over the substrate comprises:
forming an insulating layer over the substrate;
forming the first horizontal link within the first insulating layer surface;
a second insulating layer is formed over the first insulating layer.
14. The method of manufacturing according to claim 13, wherein forming the first horizontal link in the first insulating layer surface comprises the steps of:
forming a first opening in a surface of the first insulating layer;
forming a first seed layer on the side wall and the bottom of the first opening;
and filling a first metal layer in the first opening to form the first horizontal link.
15. The method of manufacturing of claim 13, wherein forming at least two first contact plugs on the first interposer comprises:
forming at least two first through holes penetrating through the second insulating layer; wherein the bottom of the first through hole is in contact with the first horizontal link;
forming a third seed layer on the side wall and the bottom of the first through hole;
forming a third metal layer in the first through hole to form a first contact plug; wherein the thickness of the third metal layer is greater than the total thickness of the second insulating layer and the second interposer.
16. The method of manufacturing of claim 13, wherein forming a second interposer over the first interposer comprises the steps of:
forming a third insulating layer over the second insulating layer;
forming the second horizontal link within the third insulating layer surface;
forming a fourth insulating layer over the third insulating layer; wherein the first contact plug penetrates through the third insulating layer and the fourth insulating layer.
17. The method of manufacturing according to claim 16, wherein forming the second horizontal link in the third insulating layer surface comprises the steps of:
Forming a second opening in the third insulating layer surface;
forming a second seed layer on the side wall and the bottom of the second opening;
and filling a second metal layer in the second opening to form the second horizontal link.
18. The method of manufacturing of claim 16, wherein forming at least two second contact plugs on the second interposer comprises:
forming at least two second through holes penetrating through the fourth insulating layer; wherein the bottom of the second through hole is in contact with the second horizontal link;
forming a fourth seed crystal layer on the side wall and the bottom of the second through hole;
forming a fourth metal layer in the second through hole; wherein the thickness of the fourth metal layer is greater than the thickness of the fourth insulating layer.
19. The method of manufacturing according to claim 12, wherein after the step of forming at least two second contact plugs on the second interposer, the method further comprises:
forming a fifth insulating layer over the second interposer;
and forming a pad opening above the first contact plug and the second contact plug on the fifth insulating layer.
20. The method of manufacturing of claim 19, wherein forming first and second pads over the second interposer at the first and second contact plug locations, respectively, comprises the steps of:
Forming a first bonding pad and a second bonding pad in the bonding pad openings corresponding to the first contact plug and the second contact plug respectively;
wherein the first pad and the second pad extend to an upper surface of the fifth insulating layer.
21. A semiconductor package structure, comprising:
packaging a substrate;
a passive silicon interposer over the package substrate; wherein the passive silicon interposer comprises a plurality of link units as claimed in any one of claims 1 to 11 or prepared by the preparation method as claimed in any one of claims 12 to 20, each of the link units being interconnected by a first horizontal link and a second horizontal link;
an active silicon interposer over the passive silicon interposer; the active silicon interposer is electrically connected with the first bonding pad and the second bonding pad of the link unit through the first micro-bump;
a processing unit located above the active silicon interposer; the processing unit is electrically connected with the active silicon intermediate layer through a second micro-bump.
22. The semiconductor package according to claim 21, wherein the active silicon interposer comprises:
A first redistribution layer over the first micro bump; the first redistribution layer comprises a plurality of first interconnection parts, and the first interconnection parts are electrically connected with the first micro-bumps;
an active device located above the first redistribution layer; wherein the active device is electrically connected to the first interconnect;
a second redistribution layer over the active device; the second redistribution layer comprises a plurality of second interconnection parts, and the upper and lower ends of the second interconnection parts are respectively and electrically connected with the second micro-bumps and the active device.
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