CN113097179A - Packaging structure with interposer - Google Patents
Packaging structure with interposer Download PDFInfo
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- CN113097179A CN113097179A CN202110342685.8A CN202110342685A CN113097179A CN 113097179 A CN113097179 A CN 113097179A CN 202110342685 A CN202110342685 A CN 202110342685A CN 113097179 A CN113097179 A CN 113097179A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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Abstract
The embodiment of the invention provides a packaging structure with an interposer, and relates to the technical field of integrated circuit chips. The packaging structure comprises: an active interposer; the M small chips are positioned above the active medium layer, fixedly connected with the active medium layer and electrically connected with each other; the passive interposer is positioned below the passive interposer and is fixedly connected with the active interposer; the packaging substrate is positioned below the passive interposer and fixedly connected with the passive interposer; wherein M is a positive integer greater than 1. According to the scheme, the advantages of the passive interposer and the active interposer are combined, so that the area of a chip can be saved, the production cost can be reduced, and the production yield can be improved.
Description
Technical Field
The present invention relates to the field of integrated circuit chip technology, and more particularly, to a package structure with an interposer.
Background
With the slowing down of moore's law and the increasing cost of semiconductor area, new architectures and packaging technologies have emerged, enabling system improvements through transistor process scaling. In recent years, multi-die integration techniques have received attention. Unlike modern System-on-a-chip (SOC) technologies that are fabricated monolithically on a single large chip, multiple semiconductor chips (each fabricated separately) are integrated into a single package structure.
Historically, multi-chip Module (MCM) packages have been used to integrate multiple chiplets onto a single substrate, providing a platform for chiplet integration. But compared to on-chip interconnects, coarse pitch substrate interconnects can only provide limited bandwidth, thereby reducing efficiency and increasing delay. However, these limitations can be addressed by using fine pitch silicon interposers, which have been used in commercial products to integrate 3D high bandwidth memory. Today, interposer technology is largely divided into passive and active interposers.
Traditionally, Networks On Chip (NOC) are deployed on dies within a Chip, which creates two problems: on the one hand, the network bandwidth is related to the number and density of metal layers on the chiplet, and increasing the metal layers increases the chip cost and yield; on the other hand, the network on chip consumes a lot of interconnect resources between chiplet chips.
If the passive interposer is adopted to deploy the NOC, the routing device must be placed in a small chip, so that the yield is reduced, and the cost of the chip area is increased; if the active interposer is adopted, the active device (such as a router or a repeater) is deployed on the interposer, and the manufacturing cost is several times that of the passive interposer; in addition, as the size of the active interposer silicon wafer increases, the production yield decreases, further increasing the cost.
Disclosure of Invention
The invention provides a packaging structure with an interposer, which aims to solve the problems that the yield is reduced and the manufacturing cost is high when the existing interposer technology is used for deploying NOC to a certain extent.
An embodiment of the present invention provides a package structure with an interposer, where the package structure includes:
an active interposer;
the M small chips are positioned above the active medium layer, fixedly connected with the active medium layer and electrically connected with each other;
the passive interposer is positioned below the active interposer and fixedly connected with the active interposer;
the packaging substrate is positioned below the passive interposer and fixedly connected with the passive interposer;
wherein M is a positive integer greater than 1.
Optionally, each of the M chiplets includes a first routing device, and the M chiplets are interconnected by the first routing device.
Optionally, the outer side of each chiplet of the M chiplets is wrapped with a packaging material;
first routing devices in different chiplets are interconnected through the encapsulation material by first conductive wires.
Optionally, when the number of the first routing devices included in the target chiplet of the M chiplets is N, the N first routing devices are electrically connected to each other;
wherein N is a positive integer greater than 1.
Optionally, the active interposer includes: a second routing device;
the second routing device is electrically connected to the first routing device.
Optionally, a through silicon via is disposed in the active interposer;
the second routing device is electrically connected with the first routing device through the through silicon via.
Optionally, the number of the second routing devices is multiple, and the multiple second routing devices are electrically connected with each other.
Optionally, the passive interposer includes a metal link, and the plurality of second routing devices are electrically connected through the metal link.
Optionally, the number of the second routing devices is greater than or equal to the number of the first routing devices.
Optionally, the active interposer and the passive interposer are both silicon interposers.
Aiming at the prior art, the invention has the following advantages:
in the embodiment of the invention, the M small chips are arranged above the active interposer and fixedly connected with the active interposer, and the passive interposer is arranged below the active interposer and fixedly connected with the active interposer, so that the advantages of the passive interposer and the active interposer are combined, the area of the chip can be saved, the production cost can be reduced, and the production yield can be improved.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments will be briefly described below.
FIG. 1 is a schematic diagram of a prior art configuration for deploying a NOC using a passive interposer;
FIG. 2 is a schematic diagram of a prior art NOC deployed using an active interposer;
FIG. 3 is a diagram illustrating a package structure using an active interposer according to the prior art;
FIG. 4 is a schematic diagram of a prior art active interposer-based network-on-chip 3D structure;
fig. 5 is a schematic diagram of a package structure according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that embodiments of the application may be practiced in sequences other than those illustrated or described herein, and that the terms "first," "second," and the like are generally used herein in a generic sense and do not limit the number of terms, e.g., the first term can be one or more than one. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/" generally means that a preceding and succeeding related objects are in an "or" relationship.
In describing embodiments of the present invention, some prior art will first be described in detail.
In the prior art, fine pitch silicon interposers utilize standard semiconductor interconnect technology, such as that found in 65nm process nodes, and use fine pitch micro-bump (e.g., microbump) dots to bond each chiplet. With interposer integration techniques, the system can achieve the yield and flexibility advantages of multi-chiplet integration while maintaining the network on chip NOC architecture for connecting modules in modern SOCs.
Today, passive interposers used in interposer technology contain only Metal interconnects, but no active Complementary Metal-Oxide-Semiconductor (CMOS) transistors. Active interposer technology used in interposer technology is an alternative to passive interposers, in which the active interposer is fabricated by standard CMOS processes, adding chip thinning technology and Through Silicon Via (TSV) insertion technology. The active interposer can provide a high speed relay link and move the NOC router onto the interposer, providing more network bandwidth than on a single-chip SOC.
Bandwidth can be increased if NOCs are deployed using passive interposers, but passive interposers contain only metal connections and no active semiconductor devices, such as: routers, repeaters, or first-in-first-out (FIFO) queues, and thus can only provide unrepeatered point-to-point connections between chiplets, i.e., chiplet-to-chiplet interconnects employ metal traces embedded in a passive interposer coupled to the microbumps of two chiplets, each microbump can be used to transmit a single signal, thus enabling high bandwidth and low latency connections.
For example: the structure of adopting a passive interposer to deploy NOC is shown in fig. 1, a chiplet a includes a kernel a1, a kernel a2, a network card a1, a network card a2, a router a1 and a router a 2; the core a1 is electrically connected with the core a2, the network card a1 is electrically connected with the network card a2, the router a1 is electrically connected with the router a2, the network card a1 is electrically connected with the core a1 and the router a1, and the network card a2 is electrically connected with the core a2 and the router a 2. The small chip B comprises a kernel B1, a kernel B2, a network card B1, a network card B2, a router B1 and a router B2; the kernel B1 is electrically connected with the kernel B2, the network card B1 is electrically connected with the network card B2, the router B1 is electrically connected with the router B2, the network card B1 is electrically connected with the kernel B1 and the router B1, and the network card B2 is electrically connected with the kernel B2 and the router B2. The NOC is deployed by adopting a passive interposer, and the passive interposer does not contain a transistor, so that the NOC can only provide non-relay point-to-point connection between a small chip a and a small chip B, CLK is an on-chip synchronous clock, and a Network Card is a Network Interface Card (NIC) for connecting a core and a router. Chiplet A-to-chiplet B interconnections employ metal traces trace embedded in a passive interposer, i.e., routers in chiplet A (router A1, router A2) and chiplet B (router B1, router B2) connect the microbumps above two chiplets (i.e., electrical connections between the passive interposer and chiplet A or chiplet B) through the passive interposer, with the routers on one chiplet coupled with the routers on the other chiplet. Therefore, compared with the data transmission of two small chips which are directly connected, the connection mode can realize the data transmission with high bandwidth and low time delay, and reduces the consumption of micro-bumps.
The adoption of the passive interposer for deploying the NOC has the defects that a routing device must be placed in a small chip, so that the yield is reduced, and the cost of the chip area is increased; for a long link, the delay time and the distance are quadratic, which easily causes larger delay and lower transmission speed; it is also difficult to implement a high frequency synchronous NOC on a passive interposer, since the clock cannot be generated on the passive interposer and buffer buffers cannot be deployed to drive a low jitter clock network.
If the NOC is deployed by adopting the active interposer, active devices (such as routers or repeaters) are deployed on the active interposer; the NOC link can reduce transmission delay by using a router, the delay of a long link is changed from a quadratic relation with distance to a linear relation, and the delay reduction results in higher NOC frequency and longer transmission distance; in addition, the router is deployed in the active interposer, which can avoid the use of micro-bump capacitance and capacitance of electrostatic discharge (ESD) protection circuits, which are necessary to protect the chiplet interface during bonding, thereby reducing delay; however, the active interposer adopts an advanced process, and the manufacturing cost is several times of that of the passive interposer; in addition, as the size of the active interposer silicon wafer increases, the production yield decreases, further increasing the cost.
For example: the structure of deploying the NOC by using the active interposer is shown in fig. 2, and a chiplet C includes a kernel C1, a kernel C2, a network card C1 and a network card C2; the kernel C1 is electrically connected with the kernel C2, the network card C1 is electrically connected with the network card C2, the network card C1 is electrically connected with the kernel C1, and the network card C2 is electrically connected with the kernel C2. The small chip D comprises a kernel D1, a kernel D2, a network card D1 and a network card D2; the kernel D1 is electrically connected with the kernel D2, the network card D1 is electrically connected with the network card D2, the network card D1 is electrically connected with the kernel D1, and the network card D2 is electrically connected with the kernel D2. A router C1, a router C2, a router D1 and a router D2 which are electrically connected with each other are arranged in the active interposer, the router C1 is electrically connected with a network card C1 in the chiplet C by using micro bumps, and the router C2 is electrically connected with a network card C2 in the chiplet C by using micro bumps (namely electrical connection pieces between the active interposer and the chiplet C or the chiplet D); the router D1 is electrically connected with the network card D1 in the small chip D by using a microbump, and the router D2 is electrically connected with the network card D2 in the small chip D by using a microbump; the active interposer is fabricated using standard CMOS processes, integrates active devices on the interposer, has a relayable link, and provides efficient synchronous transmission with a clock network on the active interposer. As shown in FIG. 3, the typical package structure further includes a package substrate, and an electrical connection is formed between the active interposer and the package substrate to reduce the consumption of resources on the upper chiplet C and chiplet D.
For example: network on chip 3D architecture based on active interposer as shown in fig. 4, R in the active interposer represents different Router; different N in the small chip C represents different network interface cards (namely network cards), different PE represents an arithmetic unit (PE) connected with different network interface cards, and different network interface cards in the small chip C are connected with different routers R in the active intermediate layer; similarly, different N in the chiplet D represents different network interface cards (i.e. network cards), different PE represents an arithmetic unit connected with different network interface cards, and different network interface cards in the chiplet D are connected with different routers R in the active interposer.
Therefore, an embodiment of the present invention provides a package structure with an interposer, where an active interposer is used to deploy a routing device, that is, a part of the routing device in a network on chip is removed from a small chip, so as to save the area of the small chip; the passive interposer is adopted to connect the active interposer, so that the production cost is reduced, and the production yield is improved.
Specifically, as shown in fig. 5, an embodiment of the present invention provides a package structure with an interposer, where the package structure specifically includes:
an active interposer 53;
m chiplets located over the active interposer 53 and fixedly connected to the active interposer 53, the M chiplets electrically connected to one another;
a passive interposer 54 located below the active interposer 54 and fixedly connected to the active interposer 53;
a package substrate positioned below the passive interposer 54 and fixedly connected to the passive interposer 54;
wherein M is a positive integer greater than 1.
Further, the active interposer and the passive interposer may both be silicon interposers.
In the above embodiments, the M chiplets are located above the active interposer 53, i.e., the active interposer 53 is disposed below the M chiplets; the passive interposer 54 is located below the active interposer 53, i.e., the active interposer 53 is disposed above the passive interposer 54; the package substrate is disposed below the passive interposer 54; in other words, the specific structure of the package structure is, from top to bottom: m chiplets, active interposer 53, passive interposer 54, package substrate, and fixedly connected in sequence. Wherein, the M chiplets can be arranged as desired, and are not particularly limited herein. For example: as shown in fig. 5, the value of M may be 2, that is, the package structure has 2 chiplets, namely a first chiplet 51 and a second chiplet 52, the first chiplet 51 and the second chiplet 52 are electrically connected, and the electrical connection manner may be through a conductive link, or the like.
In the above embodiments of the invention, the M chiplets are disposed over the active interposer 53 and fixedly connected to the active interposer 53, and the passive interposer 54 is disposed under the active interposer 53 and fixedly connected to the active interposer 53, so that the advantages of the passive interposer 54 and the active interposer 53 are combined, the chip area is saved, the production cost is reduced, and the production yield is improved.
Optionally, each of the M chiplets includes a first routing device, and the M chiplets are interconnected by the first routing device.
In the above embodiments, the first routing device may perform data processing, data synchronization, and data transmission of different portions within the chiplet, each intra-chiplet interface may connect two first routing devices within one chiplet, and each inter-chiplet interface may connect the first routing devices in different chiplets via an active interposer. The first routing device is a device capable of performing communication, and may be a processor, a router, a network card, and the like, which is not specifically limited herein.
Specifically, if the value of M is 2 and each chiplet includes a first routing device, the 2 chiplets are a first chiplet and a second chiplet, respectively; a first routing device included in the first chiplet is electrically connected to a first routing device included in the second chiplet. As shown in fig. 5, if M is 2 and each chiplet includes two first routing devices, the first routing devices included in the first chiplet 51 are: a third routing device 511 and a fourth routing device 512; the first routing devices contained in the second chiplet 52 are: fifth routing device 521 and sixth routing device 522; electrical connection of first chiplet 51 and second chiplet 52 can be made through fourth routing device 512 and fifth routing device 521 electrically connected.
It should be noted that, in the above embodiment, the value of M and the number of first routing devices in each chiplet are all examples, and are not limited.
Preferably, the outer side of each chiplet of the M chiplets is wrapped with a packaging material;
first routing devices in different chiplets are interconnected through the encapsulation material by first conductive wires.
In the above embodiments, each of the M chiplets is disposed in the packaging material, that is, the packaging material is wrapped around the outside of each chiplet, and two adjacent chiplets are not directly connected to each other and need to be connected to each other through the first conductive wire. For example: as shown in FIG. 5, the fourth routing device 512 in the first chiplet 51 is connected to one end of a first conductive wire 55 and the other end of the first conductive wire 55 is connected through the encapsulation material 56 to a fifth routing device 521 in the second chiplet 52.
Optionally, when the number of the first routing devices included in the target chiplet of the M chiplets is N, the N first routing devices are electrically connected to each other;
wherein N is a positive integer greater than 1.
In the above embodiments, the target chiplet can be one of the M chiplets, or the target chiplet can be multiple of the M chiplets, or the target chiplet can be the M chiplets. If the target small chip comprises N first routing devices, the N first routing devices are electrically connected; such as: the manner of electrical connection may be by a first electrically conductive line.
For example: as shown in fig. 5, if M is 2, the target chiplets are the first chiplet 51 and the second chiplet 52, and each chiplet contains two first routing devices, the third routing device 511 and the fourth routing device 512 in the first chiplet 51 are electrically connected, and the fifth routing device 521 and the sixth routing device 522 in the second chiplet 52 are electrically connected.
It should be noted that the number of the first routing devices included in the target chiplet is not limited to a plurality of first routing devices, but may be one, and the above embodiment is only an example.
Optionally, the active interposer includes: a second routing device;
the second routing device is electrically connected to the first routing device.
In the above embodiments, the active interposer includes a second routing device, and the second routing device is electrically connected to the first routing device, so as to electrically connect the active interposer and the chiplet. The second routing device is a device capable of performing communication, and may be a processor, a router, a network card, and the like, which is not specifically limited herein.
For example: as shown in FIG. 5, four second routing devices are included in the active interposer 53, with different second routing devices electrically connected to different first routing devices in the chiplet, thereby forming an electrical connection between the active interposer 53 and the chiplet.
Further, a through silicon via is arranged in the active interposer;
the second routing device is electrically connected with the first routing device through the through silicon via.
In the above embodiments, the active interposer is provided with a second routing device, the chiplet is disposed above the active interposer, and the first routing device in the chiplet is connected to the second routing device through the conductive line, the microbump, and the through-silicon via in the active interposer, respectively, to form a via. As shown in FIG. 5, the electrical connections between the chiplets (first chiplet 51, second chiplet 52) and the active interposer 53 are micro-bumps that serve as both permanent connections and electrical conduction.
Optionally, the number of the second routing devices is multiple, and the multiple second routing devices are electrically connected with each other.
As shown in fig. 5, in the above embodiment, the number of the second routing devices in the active interposer 53 is 4, which are: a seventh routing device 531, an eighth routing device 532, a ninth routing device 533, a tenth routing device 534; the seventh routing device 531 is electrically connected to the eighth routing device 532, the eighth routing device 532 is electrically connected to the ninth routing device 533, and the ninth routing device 533 is electrically connected to the tenth routing device 534, thereby achieving interconnection between the second routing devices in the active interposer 53.
Further, the passive interposer includes a metal link, and the plurality of second routing devices are electrically connected to each other through the metal link.
As shown in fig. 5, in the above embodiment, the passive interposer 54 includes a metal link 541 therein, where the metal link 541 is used to interconnect the second routing devices in the active interposer 53, that is, the active interposer 53 and the passive interposer 54 are connected by a micro bump, and the micro bump plays a role of fixed connection and electrical conduction, so that the seventh routing device 531 in the active interposer 53 is electrically connected to the eighth routing device 532 by the micro bump and the metal link 541, the eighth routing device 532 is electrically connected to the ninth routing device 533 by the micro bump and the metal link 541, and the ninth routing device 533 is electrically connected to the tenth routing device 534 by the micro bump and the metal link 541.
Optionally, the number of the second routing devices is greater than or equal to the number of the first routing devices. Preferably, as shown in fig. 5, the number of the second routing devices is the same as the number of the first routing devices, and the second routing devices are connected to the first routing devices in a one-to-one correspondence manner, so as to reduce the cost of the second routing devices.
To sum up, in the embodiments of the present invention, the second routing device in the active interposer is connected to the first routing device in the upper chiplet through the microbump and the TSV, and the first routing devices in the chiplets are interconnected, and the second routing device in the active interposer is interconnected through the metal link in the passive interposer, so that data can be transmitted through the metal link in the passive interposer, the second routing device in the active interposer, and the microbump on the chiplet; in addition, the manufacturing cost of the active interposer is far higher than that of the passive interposer, so that the NOC router is deployed by fully utilizing the active interposer, and meanwhile, the manufacturing difficulty of the active interposer is simplified as much as possible while the occupied area of an upper small chip is reduced by integrating the passive interposer, and the yield is improved.
In the description of the present invention, it is to be understood that the terms "left", "bottom", "one end", "top", "front", "other end", "up", "one side", "top", "rear", "front", "right", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.
In addition, it should be noted that unless otherwise expressly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may include, for example, a fixed connection, a removable connection, and an integral connection; can be mechanically or electrically connected; the terms may be directly connected or indirectly connected through an intermediate, and may be used for communicating the inside of two elements or interacting relation of two elements, unless otherwise specifically defined, and the specific meaning of the above terms in the present invention may be understood by those skilled in the art according to specific situations.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims (10)
1. A package structure having an interposer, comprising:
an active interposer;
the M small chips are positioned above the active medium layer, fixedly connected with the active medium layer and electrically connected with each other;
the passive interposer is positioned below the active interposer and fixedly connected with the active interposer;
the packaging substrate is positioned below the passive interposer and fixedly connected with the passive interposer;
wherein M is a positive integer greater than 1.
2. The package structure with the interposer as recited in claim 1, wherein each of the M chiplets contains a first routing device, the M chiplets being interconnected by the first routing device.
3. The package structure with interposer as claimed in claim 2, wherein each of the M chiplets has a packaging material wrapped around its outer side;
first routing devices in different chiplets are interconnected through the encapsulation material by first conductive wires.
4. The package structure with the interposer as recited in claim 2, wherein in the case that a target chiplet of the M chiplets contains N first routing devices, N first routing devices are electrically connected to each other;
wherein N is a positive integer greater than 1.
5. The package structure with the interposer as claimed in claim 2, wherein the active interposer comprises: a second routing device;
the second routing device is electrically connected to the first routing device.
6. The package structure with the interposer as claimed in claim 5, wherein the active interposer has through-silicon vias disposed therein;
the second routing device is electrically connected with the first routing device through the through silicon via.
7. The package structure with the interposer as recited in claim 5, wherein the second routing device is plural in number, and a plurality of second routing devices are electrically connected to each other.
8. The package structure with the interposer as recited in claim 7, wherein the passive interposer comprises metal links, and the plurality of second routing devices are electrically connected via the metal links.
9. The package structure with the interposer as recited in claim 5, wherein the number of second routing devices is greater than or equal to the number of first routing devices.
10. The package structure with the interposer as recited in claim 1, wherein the active interposer and the passive interposer are both silicon interposers.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115295065A (en) * | 2022-10-09 | 2022-11-04 | 南京邮电大学 | Core grain test circuit based on flexible configurable module |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115295065A (en) * | 2022-10-09 | 2022-11-04 | 南京邮电大学 | Core grain test circuit based on flexible configurable module |
| CN115295065B (en) * | 2022-10-09 | 2022-12-13 | 南京邮电大学 | Core grain test circuit based on flexible configurable module |
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