CN116845051A

CN116845051A - Packaging structure based on active silicon interposer and manufacturing method thereof

Info

Publication number: CN116845051A
Application number: CN202310803025.4A
Authority: CN
Inventors: 李翔宇; 刘亚斐; 麦宋平
Original assignee: Tsinghua University; Shenzhen Research Institute Tsinghua University
Current assignee: Tsinghua University; Shenzhen Research Institute Tsinghua University
Priority date: 2023-06-30
Filing date: 2023-06-30
Publication date: 2023-10-03

Abstract

The application provides a packaging structure based on an active silicon intermediate layer and a manufacturing method thereof, which are applied to the technical field of packaging structures based on the active silicon intermediate layer, wherein the packaging structure based on the active silicon intermediate layer comprises: a package carrier including a first pad array; an active silicon interposer over the package carrier, the active silicon interposer including a second pad array and a third pad array; a first metal lead for connecting the second pad array with the first pad array; the chip module is positioned above the active silicon intermediate layer, the chip module comprises at least one chip, the chip comprises a fourth pad array, pads in the fourth pad array and pads in the third pad array are arranged according to the same pad layout plan, and the fourth pad array is connected with the third pad array through a first bump. The TSV process is avoided, the process defects are reduced, the manufacturing difficulty and cost are reduced, and the packaging yield is improved. Multiplexing the active silicon intermediate layer is realized, and the cost of the active silicon intermediate layer is further reduced.

Description

Packaging structure based on active silicon interposer and manufacturing method thereof

Technical Field

The application relates to the technical field of packaging structures based on active silicon intermediaries, in particular to a packaging structure based on an active silicon intermediaries and a manufacturing method thereof.

Background

In the field of active silicon interposer based package structure technology, a silicon interposer may be placed between a package substrate and a die, with the silicon interposer (Silicon Interposer) being used to connect the die's external signals to the package substrate. In a conventional packaging structure system based on an active silicon interposer, external signals of a bare chip are connected to a packaging substrate through silicon through holes (Through Silicon Via, TSVs) on the active silicon interposer, and then the bare chip is connected to an external interface through the packaging substrate, however, the manufacturing difficulty of the silicon through holes is high, the cost is high, and in addition, process defects can be introduced in the manufacturing process of the silicon through holes, so that the failure risk of the packaging structure system based on the active silicon interposer is increased, and the reliability of the packaging structure system based on the active silicon interposer is reduced.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a package structure based on an active silicon interposer and a method for fabricating the same, so as to solve the above-mentioned problems.

In a first aspect, the present application provides an active silicon interposer-based package structure, comprising: a package carrier including a first pad array; an active silicon interposer over the package carrier, the active silicon interposer including a second pad array and a third pad array; a first metal lead for connecting the second pad array with the first pad array; the chip module is positioned above the active silicon intermediate layer, the chip module comprises at least one chip, the chip comprises a fourth pad array, pads in the fourth pad array and pads in the third pad array are arranged according to the same pad layout plan, and the fourth pad array is connected with the third pad array through a first bump.

In a preferred embodiment, the active silicon interposer includes a first surface and a second surface opposite to each other, the first surface corresponding to the chip module and the second surface corresponding to the package carrier; the second pad array and the third pad array are positioned on the first surface, the second pad array is positioned on the periphery of the first surface, and the third pad array is wrapped in the second pad array.

In a preferred embodiment, the third pad array includes at least one standard pad array set according to a pad layout plan, the fourth pad array includes at least one standard pad array set according to a pad layout plan, the standard pad array includes pads of the first functional area and pads of the second functional area, and the pads of the first functional area include one or more of the following pads: the first power supply pad, the first grounding pad, the system clock pad, the system reset pad and the programmable direct connection pad, and the pad of the second functional area comprises one or more of the following pads: a data gate pad, a channel reset pad, a data transfer pad, a second power pad, and a second ground pad.

In a preferred embodiment, when the number of standard land arrays in the third land array is greater than or equal to 2, the third land array has at least one pair of standard land arrays that are rotationally symmetrical.

In a preferred embodiment, when the number of standard pad arrays in the third pad array is greater than or equal to 2, the third pad array further includes a fifth pad array arranged between the standard pad arrays, the fifth pad array including a first power pad and a first ground pad.

In a preferred embodiment, the first metal lead is a bonding lead, the first bump is a micro bump, and the micro bump is integrally formed with a pad in the fourth pad array. The first bump includes, but is not limited to: micro bumps, copper bumps (consist of a copper pillar with a solder cap), bump-less hybrid Cu-Cu hybrid bonding, wherein bump-less hybrid bonding uses copper-copper direct bonding techniques that do not require micro bumps.

In a preferred embodiment, a predetermined space exists between the pads in the second pad array and the pads in the third pad array.

In a preferred scheme, the space between each bonding pad in the third bonding pad array is consistent with the space between each bonding pad in the fourth bonding pad array, and the bonding pads which are functionally corresponding in the third bonding pad array and the fourth bonding pad array are connected through the first bump.

In a preferred embodiment, the package carrier comprises any one of a package substrate, a package case, or a printed circuit board.

In a preferred embodiment, the package carrier may be a passive interposer or an active interposer.

In a second aspect, the present application provides a method of fabricating an active silicon interposer-based package structure, the method comprising: providing a packaging carrier and forming a first pad array on the packaging carrier; providing an active silicon intermediate layer, forming a second pad array on the first surface of the active silicon intermediate layer, and forming a third pad array on the first surface according to a pad layout plan; providing a chip module, wherein the chip module comprises at least one chip, and a fourth bonding pad array is formed on the chip according to bonding pad layout planning; connecting the fourth pad array with the third pad array through the first bump; the second surface of the active silicon interposer is disposed on the package carrier and is connected to the second pad array and the first pad array by a first metal lead, the second surface being opposite to the first surface.

According to the packaging structure based on the active silicon intermediate layer and the manufacturing method thereof, the active silicon intermediate layer is connected with the chip through the first salient points, so that higher communication bandwidth is provided through the first salient points, communication delay is reduced, and high-performance interconnection between the chips is ensured. The active silicon intermediate layer is connected with the packaging carrier through the first metal lead, the TSV technology is avoided, the technology defect caused by the manufacturing process of the through silicon vias is avoided, the failure risk of the packaging structure based on the active silicon intermediate layer is reduced, the reliability of the packaging structure based on the active silicon intermediate layer is improved, the manufacturing difficulty and cost of the active silicon intermediate layer are also reduced, and the packaging yield is improved. Further, the active silicon intermediaries and the bonding pads of the chips can be planned and set according to the same bonding pad layout, so that the active silicon intermediaries can support electrical interconnection of various different chips, multiplexing of the active silicon intermediaries is achieved, the active silicon intermediaries special for different chip designs are avoided, and the cost of the active silicon intermediaries is reduced.

Drawings

Fig. 1 is a schematic structural diagram of a package structure based on an active silicon interposer according to an embodiment of the present application.

Fig. 2A is a schematic diagram illustrating a package carrier as a package substrate in the package structure of fig. 1.

Fig. 2B is a structural diagram of the package carrier in the package structure of fig. 1.

Fig. 3 is a schematic diagram of a pad layout of a standard pad array according to an embodiment of the present application.

Fig. 4 is a schematic diagram illustrating an interface function between a chip and an active silicon interposer according to an embodiment of the present application.

Fig. 5 is a schematic diagram of a pad layout of a chip according to an embodiment of the present application.

Fig. 6 is a schematic diagram of a pad layout of an active silicon interposer according to an embodiment of the present application.

Fig. 7 is a schematic diagram of another pad layout of an active silicon interposer according to an embodiment of the present application.

FIG. 8 is a schematic diagram of the connection between the active silicon interposer and the chip shown in FIG. 7.

FIG. 9 is another schematic diagram of the connection of the active silicon interposer and the chip shown in FIG. 7.

Fig. 10 is a flowchart illustrating a method for manufacturing a package structure based on an active silicon interposer according to an embodiment of the present application.

Description of the main reference signs

Packaging structure 100 based on active silicon interposer

Packaging carrier 10

Active silicon interposer 20

Chip module 30

Chips 1, 2

First metal lead 40

First pad array 11

Upper surface 12

Lower surface 13

First surface 201

Second surface 202

Second pad array 21

Third pad array 22

Fourth land arrays 31, 31a, 31b, 801, 802, 803, 804,

901、902

Wire bond pads 111, 211

Bump pads 221, 311a, 311b

First bump 32

Packaging substrate 101

C4 bump array 14

C4 bump 141

Encapsulated shell 102

Cover plate 103

First functional areas 310, 320a, 320b

Second functional areas 320, 310a, 310b

First data path region 301

Second data access area 302

Third data path region 303

Fourth data Path region 304

Data transfer micro bump pads 401a, 401b,

First power supply micro bump pads 402a, 402b

First ground micro bump pads 403a, 403b

System clock micro bump pads 404a, 404b

System reset micro bump pads 405a, 405b

The chip corresponds to the surface 1a of the active silicon interposer

Standard pad arrays 300, 601, 602, 603, 604, 701,

702、703、704、

Fifth pad array 605, 705

Socket 23

The application will be further described in the following detailed description in conjunction with the above-described figures.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the present application.

All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without any inventive effort, are intended to be within the scope of the present application.

In the field of chip packaging technology, a package substrate and a die (or chip) may be connected by a silicon interposer. The silicon interposer is a chip based on silicon technology, and is used for connecting external signals of the bare chips to the packaging substrate, and when two or more bare chips are placed on the silicon interposer, the silicon interposer is also used for realizing electrical interconnection between the two or more bare chips and realizing data transmission between the two or more bare chips.

The silicon intermediaries include an active silicon intermediaries (active silicon interposer) and a passive silicon intermediaries (passive silicon interposer). The passive silicon interposer realizes electrical interconnection between the bare chips through the interconnection lines, and is a passive structure without control function, so that the passive interposer cannot autonomously process faults, and the reliability of the passive silicon interposer depends on the reliability of the package substrate and the bare chips. The active silicon intermediate layer comprises active devices such as transistors and the like, such as voltage regulators and networks, so that the active silicon intermediate layer can autonomously process faults and has high reliability. In addition to the electrical interconnection between the dies through interconnect lines, the active silicon interposer may also enable high performance interconnection (i.e., high bandwidth and low latency data transmission) with the dies through the network within it. The active silicon interposer may implement common circuit functions of common system chips, such as power supply, data interconnect network, and system input and output. In view of this, active silicon intermediaries are commonly used to achieve high performance interconnects between dies.

The interposer-on-silicon technology generally employs a through silicon via (Through Silicon Via, TSV) technology, which is a packaging technology for packaging different chips together, by making through-substrate vias filled with conductive material therein, and then stacking a plurality of chips or wafers together, with the vias being used to make electrical connections between the chips. The through silicon vias can maximize the density of the stacked chips in three dimensions, minimize the overall dimensions, and greatly improve the chip speed and low power consumption performance. Specifically, the through silicon vias are vertical through holes made on a chip (such as a silicon interposer) by etching, laser and other technologies, and then vertical electrical interconnection of the through silicon vias is realized by filling conductive substances such as copper, tungsten, polysilicon and the like, so that electrical interconnection between the bare chip and the packaging substrate is realized.

In a silicon interposer packaging system, a die is flip-chip packaged onto a silicon interposer, which is soldered to a package substrate by means of back-side C4 bumps (Controlled Collapse Chip Connection bump). The electrical interconnection between the bare chips is realized by the interconnection lines or the active devices on the silicon medium layer, and the external signals of the bare chips are connected to the packaging substrate through the silicon through holes and the C4 bumps on the silicon medium layer and then connected to the external interface through the packaging substrate.

When the active silicon interposer is used for chip packaging, the cost of the active silicon interposer is high, and multiple special active silicon intermediaries are often required to be designed for different bare chips, so that the total cost of a packaging system is increased. Conventional active silicon intermediaries need to realize vertical connection between an upper layer and a lower layer (such as a bare chip and a packaging substrate) through a through silicon via technology, however, the through silicon vias are difficult to manufacture and have high cost. In addition, process defects may be introduced in the manufacturing process of the through silicon vias, so that the failure risk of the packaging system is increased, and the reliability of the packaging system is reduced. In the process of manufacturing the through silicon via, stress is brought to an active silicon area close to the opening of the via hole, and normal operation of a circuit is interfered. Therefore, a "keep-out zone" (KOZ) is set in the area surrounding the through-silicon via, in which the active circuit cannot be inserted. The forbidden area is not negligible, and when a plurality of TSVs are placed on a chip, a large number of discontinuous unavailable areas are caused, the layout utilization rate of the chip is seriously affected, and difficulty is caused to the layout and wiring design of the chip.

In view of this, the present application provides a package structure based on an active silicon interposer and a method for manufacturing the same, wherein the package structure based on the active silicon interposer supports internal high speed and external low speed, that is, a high-speed interface is used to realize electrical interconnection between chips, and a low-speed interface is used to realize electrical interconnection between chips and the outside. Specifically, the active silicon intermediate layer is connected with the chip through the first bump, so that higher communication bandwidth is provided through the first bump, communication delay is reduced, and high-performance interconnection between the chips is ensured. The active silicon intermediate layer is connected with the packaging carrier through the first metal lead, the TSV process is avoided, the process defect caused by the manufacturing process of the through silicon vias is avoided, the failure risk of the chip packaging structure is reduced, the reliability of the chip packaging structure is improved, the manufacturing difficulty and cost of the active silicon intermediate layer are also reduced, and the packaging yield is improved. The problem of chip layout utilization rate caused by the fact that the forbidden area of the through silicon via occupies the active area of the active medium layer is avoided. Further, the active silicon intermediaries and the bonding pads of the chips can be planned and set according to the same bonding pad layout, so that the active silicon intermediaries can support electrical interconnection of a plurality of different chips, and can also realize electrical interconnection of a plurality of the same chips, multiplexing of the active silicon intermediaries is realized, special active silicon intermediaries for different chip designs are avoided, and cost of the active silicon intermediaries is reduced.

Fig. 1 schematically illustrates a package structure based on an active silicon interposer according to an embodiment of the present application.

As shown in fig. 1, the active silicon interposer-based package structure 100 includes a package carrier 10, an active silicon interposer 20, and a chip module 30. The active silicon interposer 20 is located above the package carrier 10, the chip module 30 is located above the active silicon interposer 20, that is, the active silicon interposer 20 is located between the package carrier 10 and the chip module 30, and the active silicon interposer 20 is used to connect the package carrier 10 and the chip module 30, so as to realize electrical connection between the package carrier 10 and the chip module 30, and also realize electrical connection of chips (such as the chip 1 and the chip 2 shown in fig. 1) in the chip module 30.

The package carrier 10 comprises a first array of pads 11, which first array of pads 11 is for connection with an active silicon interposer 20. A Wire Bonding Pad (Wire Bonding Pad) 111 is included on the first Pad array 11. Wire bond pad 111 is comprised of metal, and in some embodiments wire bond pad 111 may be comprised of multiple layers of metal, such as wire bond pad 111 being comprised of five layers of metal plated Au, ni, cu, ni, au sequentially on top of each other on the bottom, as embodiments of the application are not specifically limited in this regard.

Specifically, the first pad array 11 is disposed on the upper surface 12 of the package carrier 10, and the upper surface 12 corresponds to the active silicon interposer 20, that is, the active silicon interposer 20 is disposed on the upper surface 12.

In some embodiments, as shown in fig. 2A, package carrier 10 may further include a C4 bump array 14, C4 bump array 14 including C4 bumps 141. The C4 bump array 14 is disposed on the lower surface 13 opposite the upper surface 12, the C4 bump array 14 being for interfacing with an external interface.

In some embodiments, as shown in fig. 2B, the active silicon interposer-based package structure 100 may further include a cover plate 103, and the molding package is implemented by the cover plate 103 to protect the active silicon interposer-based package structure 100, such as the active silicon interposer 20, the chip module 30, and the first metal leads 40.

The package carrier 10 may be implemented as a package substrate, package case, printed circuit board (Printed Circuit Board, PCB), or the like, which is not particularly limited in the present application.

The following exemplary description is given of the application scenario in which the package carrier 10 in fig. 1 is a different carrier, respectively.

Fig. 2A differs from fig. 1 in that the package carrier 10 of fig. 1 is implemented as a package substrate 101 in fig. 2A. A C4 bump array 14 is provided on the lower surface 13 of the package substrate 101, a first pad array 11 is provided on the upper surface 12 of the package substrate 101, and C4 bumps 141 in the C4 bump array 14 are connected to wire bond pads 111 in the first pad array 11. Fig. 2B differs from fig. 1 in that fig. 2B illustrates the package carrier 10 as the package can 102. The first pad array 11 is disposed around the package case 102, and the active silicon interposer 20, the chip module 30, and the first metal lead 40 are all disposed in the cavity of the package case 102, and the cover plate 103 is hermetically connected to the package case 102 to protect the active silicon interposer, the chip module 30, and the first metal lead 40.

When the package carrier 10 is a circuit board or package 102, the first pad array 11 on the circuit board or package 102 is directly connected to the external interface, and the circuit board or package 102 may not need to be provided with the C4 bump array 14.

The active silicon interposer 20 includes opposite first and second surfaces 201, 202, the second surface 202 corresponding to the package carrier 10, i.e., the second surface 202 is adhered to the package carrier 10, and the second surface 202 is in contact with the upper surface 12 of the package carrier 10. The first surface 201 corresponds to the chip module 30, that is, the chip module 30 is adhered to the first surface 201.

The active silicon interposer 20 includes a second pad array 21 and a third pad array 22. The second pad array 21 and the third pad array 22 are disposed on the first surface 201. The second pad array 21 is for connection to the package carrier 10, and the second pad array 21 includes wire bond pads 211 thereon. The third pad array 22 is used for connection with the chip module 30, and the third pad array 22 includes bump pads 221 thereon.

For the relevant content of the wire bonding pads 211 in the second pad array 21, reference may be made to the wire bonding pads 111 described above, where the wire bonding pads 211 and the wire bonding pads 111 are used to implement wire bonding, and the difference is that the pads are disposed on different carriers, which is not described herein again.

The bump pad 221 is used for connecting a bump, and the bump may be any of the following: c4 bump (Controlled Collapse Chip Connection), C2 bump (Chip Connection), and bump-less copper-copper direct bonding (bump Cu-Cu hybrid bonding). The C4 bump is a controllable collapse chip connection process, and typical representative of the C4 bump is a solder ball bump, and the pitch range of the solder ball bump can be 150 μm or 50 μm. Wherein the C2 bumps may also be referred to as micro bumps. Typical examples of the C2 bump include copper stud bumps having a micro copper stud+solder cap (cu-ballast+holder cap), and the pitch of the copper stud bumps may be 50 μm or less and may be 25 μm or less. Wherein the bump-free copper-copper direct bonding is also called hybrid bonding, and the interval range between the bumps and the copper direct bonding can be 1-10 mu m.

Bump pads 221 may be divided into: c4 bump pads, C2 bump pads, and hybrid bond pads. Wherein the C4 bump pad is connected with the C4 bump, the C2 bump pad is connected with the C2 bump, and the hybrid bonding pad uses hybrid bonding.

The embodiment of the application does not limit the spacing, the material and the implementation process of the bumps connected with the bump pads in particular.

The active silicon interposer based package structure 100 further includes a first metal lead 40, the first metal lead 40 being used to connect the first pad array 11 and the second pad array 21. The first metal lead 40 is a metal lead for wire bonding (wire bonding). Specifically, the wire bonding pads 211 in the second pad array 21 and the wire bonding pads 111 in the first pad array 11 are electrically connected by the first metal wire 40, that is, by wire bonding, which is a method of tightly bonding the metal wire and the wire bonding pad using heat, pressure, and ultrasonic energy.

The chip module 30 includes at least one chip. The chip includes a fourth pad array 31, the fourth pad array 31 includes bump pads 311, and the bump pads 311 in the fourth pad array 31 may refer to the bump pads 221 described above, where the bump pads 311 are different from the bump pads 221 only in that the pads are disposed on different carriers, which will not be described herein. When the chip module 30 includes two or more chips, each chip includes its corresponding fourth pad array. As in fig. 1 and 2, taking the chip module 30 as an example, the chip 1 includes its corresponding fourth pad array 31a, the fourth pad array 31a includes bump pads 311a, the chip 2 includes its corresponding fourth pad array 31b, and the fourth pad array 31b includes bump pads 311b.

In some embodiments, the chips in the chip module 30 may be different types of chips that may be used to implement different functions, such as different types of chips including, but not limited to: logic chip, memory chip and dummy chip (dummy die). The plurality of chips in the chip module 30 may have different sizes, different bandwidth requirements, different power pin count requirements, etc. As in the chips 1 to 2 of fig. 1 and 2, which are logic chips of different functions or one of which is a logic chip and one of which is a memory chip, when the sizes of the chip 1 and the chip 2 are different, the sizes or the number of pads of the fourth pad array 31a and the fourth pad array 31b may be different, respectively.

It should be noted that the number of chips in fig. 1 and 2 is only an example, and the present application is not limited to the number of chips in the chip module 30, nor to the types of chips.

The bump pads 311 in the fourth pad array 31 are identical in size to the bumps connected to the bump pads 221 in the third pad array 22, the bump pads 311 in the fourth pad array 31 are micro bump pads, and correspondingly, the bump pads 221 in the third pad array 22 connected to the fourth pad array 31 are micro bump pads. The pitch of the bump pads 311 in the fourth pad array 31 is identical to the pitch of the bump pads 221 in the third pad array 22, for example, the pitch of the micro bump pads in the fourth pad array 31 is 50 μm, and correspondingly, the pitch of the micro bump pads in the third pad array 22 connected to the fourth pad array 31 is also 50 μm.

In the embodiment of the present application, the package structure 100 based on the active silicon interposer further includes a first bump 32, and the bump pad 221 of the third pad array 22 and the bump pad 311 of the fourth pad array 31 are connected through the first bump 32, specifically, one first bump 32 connects one bump pad 221 of the third pad array 22 with one bump pad 311 of the fourth pad array 31, thereby achieving electrical connection between the third pad array 22 and the fourth pad array 31. More specifically, one first bump 32 connects the third pad array 22 with a bump pad in the fourth pad array 31 that is consistent in function, that is, realizes a one-to-one correspondence between the pins of the third pad array 22 and the fourth pad array 31. In other words, the two bump pads connected by the first bump 32 are used to realize the same function, such as both for data transmission, and the function and arrangement of the respective pads in the third pad array 22 and the fourth pad array 31 will be described in detail below. The number of the first bumps 32 is not particularly limited in the embodiment of the present application. The content of the first bump 32 may refer to the content of the bump, which is not described herein.

Preferably, the first bump 32 is a micro bump, and then the bump pads 221 in the third pad array 22 and the bump pads 311 in the fourth pad array 31 are micro bump pads. The micro-bumps can be prepared on a large scale on the whole wafer by a photoetching electroplating method, so that the production efficiency is greatly improved, and the reduction of the batch packaging cost is realized.

In the embodiment of the application, the micro-bump can be any one of the following bumps: solder bumps, copper stud bumps (or micro copper studs) and bond copper bumps.

In some embodiments, the first bump 32 is integrally formed with the bump pad 311 in the fourth pad array 31. In other embodiments, the first bump 32 may also be integrally formed with the bump pad 221 in the third pad array 22. In order to ensure high-quality interconnection between chips, different bump structures, different bump preparation methods and corresponding interconnection modes are required to be selected for bumps of different sizes, and the application is not particularly limited to this.

The package structure 100 based on the active silicon interposer provided in the embodiment of the application at least includes the following technical effects:

in the embodiment of the present application, the fourth pad array 31 on the chip and the third pad array 22 on the active silicon interposer 20 are connected through the first bump 32, thereby realizing high-performance interconnection between each chip in the chip module 30 and high-performance interconnection between the chip in the chip module 30 and the active silicon interposer 20 through the first bump 32. The high performance interconnection between the chips in the chip module 30 is mainly realized by metal lines and interconnection circuits on the active silicon interposer 20. The second pad array 21 on the active silicon interposer 20 is connected with the first pad array 11 on the package carrier 10 through the first metal leads 40, the external signals of the chip are connected to the package carrier 10 through the first metal leads 40 by the active silicon interposer 20, and then the external signals of the chip are connected to the external interface through the package carrier 10, for example, the external signals are connected to the external interface through the C4 bump array 14 of the package carrier 10. That is, the leads adopting wire bonding are external connection of the chips, and the chips are connected with the outside by wire bonding, so that stacked packaging of the chips and chip-to-chip interconnection with low insertion loss are realized. In this way, in the package structure 100 based on the active silicon interposer, the chip external communication does not need to adopt a high-performance package form such as a flip ball array, so that the active silicon interposer 20 does not need to lead out contacts from both the upper surface and the lower surface, that is, the first surface 201 and the second surface 202 of the active silicon interposer 20 do not need to be provided with bump pads, that is, the TSV process is avoided to connect the external signal of the chip to the package carrier 10, and the TSV process is avoided, thereby avoiding the process defects caused by the through silicon via manufacturing process, reducing the failure risk of the package structure 100 based on the active silicon interposer, improving the reliability of the package structure 100 based on the active silicon interposer, reducing the manufacturing difficulty and the cost of the active silicon interposer 20, and improving the package yield. And the failure risk caused by TSV process defects is reduced. In addition, the active silicon interposer 20 and the chip are both silicon materials with uniform expansion coefficients, which is beneficial for stress reduction.

Particularly, in the application scene of the internet of things and intelligent perception, the input data bandwidth of the application is low, a large amount of intermediate values can be generated in the processing and perception calculation processes, so that the communication bandwidth requirement among the internal modules of the packaging system (structure) is large, the data volume of the final recognition result is very small, usually only a few bits, the storage capacity in the packaging system can be improved by utilizing the advanced packaging technology, and in conclusion, the bandwidth requirement for external interconnection is small, therefore, the packaging system chip in the packaging structure 100 based on the active silicon intermediate layer provided by the embodiment of the application can externally adopt a wire bonding packaging mode, and the requirement for external interconnection bandwidth can be met; the high bandwidth interconnect is internally implemented with active interposer.

Specifically, the package structure 100 based on the active silicon interposer provided by the embodiment of the application supports the internal high speed, and the external low speed can meet the requirements of products such as an intelligent sensing system and the like, and has higher market value. The high-performance interconnection between chips is realized through the first salient points 32, the chip external signals are connected to the packaging carrier 10 through the first metal lead wires 40, the bandwidth requirement of an external sensor signal interface is not high for an intelligent sensing system, the data volume of the extracted information such as characteristics, identification results and the like is generally greatly compressed after the analysis of the sensing function, and the external signals are transmitted through the first metal lead wires 40 to meet the low bandwidth requirement. For the more complex artificial intelligence algorithm inside the system, a higher internal communication bandwidth is often required, and for this purpose, the chip is connected with the active silicon interposer 20 through the first bump 32, and high-performance interconnection is realized through the first bump 32 and the network inside the active silicon interposer 20, so as to meet the requirement of the signal transmission inside the chip on high bandwidth.

The arrangement of the third pad array 22 and the fourth pad array 31 will be specifically described below.

In the embodiment of the present application, the arrangement of each pad in the third pad array 22 and the fourth pad array 31 is set according to the same pad layout plan, and the pad layout plan indicates that at least one standard pad array is included in the pad array, and the standard pad array includes two functional areas, and the first functional area may also be referred to as a common functional area (common), and the pads of the first functional area are used for implementing a system function so as to meet the necessary provision of the system function. The second functional area may also be referred to as a data path area (data line), and a pad of the second functional area is used to implement data transmission. The network built in the active silicon interposer 20 enables high-speed data interconnection between chips through the interface of the data path region (i.e., the pads of the second functional region).

In an embodiment of the present application, the pads of the first functional region include one or more of the following pads: a first power pad, a first ground pad, a system clock pad, a system reset pad, and a programmable direct connect (reconfigurable feedthrough) pad. Wherein the first power supply pad is used for providing power supply VDD to the chip by the active silicon interposer 20. The first ground pad is used to implement the active silicon interposer 20 to provide the common ground signal VSS to the chip. The system clock pad is used to enable the active silicon interposer 20 to provide the system clock signal sys_clk to the chip. The system reset pad is used to enable the active silicon interposer 20 to provide a system reset signal sys_rstn to the chip. The programmable direct bonding pad is used for realizing direct connection of the chip to the outside, the programmable direct bonding pad is directly connected with the wire bonding pad of the active silicon interposer 20, and the configurable signal reconfig of the programmable direct bonding pad can be configured as: the chip passes through the functions of direct connection signals of the active silicon interposer 20 and an external interface, power management control signals sent to the chip in the active silicon interposer 20, detection signals of the active silicon interposer 20 and the chip, and the like. Specifically, the internal control circuit of the active silicon interposer outputs a configurable signal reconfig, which is output to the configuration terminal of the programmable direct bonding pad, so as to configure the signal direction of the programmable direct bonding pad (for example, configure the signal direction of the programmable direct bonding pad as input or output), and the connection to the internal (for example, the direct bonding signal of the active silicon interposer 20 and the external interface).

The pads of the second functional region include one or more of the following pads: a data gate pad, a channel reset pad, a data transfer pad, a second power pad, and a second ground pad. Wherein the data strobe pad is used for transmitting a data strobe signal line_strb in the data path. The channel reset pad is used to transmit a channel reset signal line_rstn in the data path. The data transmission pad is used for transmitting a data transmission signal line_data in the data path. The second power supply pad is used to implement the interface voltage VDDIO of the second power supply pad provided to the chip by the active silicon interposer 20. The second ground pad is used to implement the active silicon interposer 20 to provide the interface common ground signal VSSIO to the chip.

Preferably, the pads of the second functional region include at least a data gate pad, a channel reset pad, and a data transfer pad.

Referring to fig. 3, fig. 3 is a schematic diagram illustrating a pad layout of a standard pad array according to an embodiment of the application.

Taking the example that the standard pad array 300 is disposed on the active silicon interposer 20, a standard pad array 300 disposed on the active silicon interposer 20 is a part or all of the third pad array 22, and taking bump pads in the third pad array 22 as micro bump pads, the example that the standard pad array 300 is 7 rows 11 columns, the standard pad array 300 on the third pad array 22 includes a first functional area 310 and a second functional area 320.

In some embodiments, taking the first functional area 310 as 3 columns and each data path in the second functional area 320 as 2 columns as an example, the standard pad array may be 3+2n columns, where N is an integer greater than or equal to 1.

The first functional area 310 mainly provides a chip power supply, a system clock and a system reset signal to the chip, specifically, the first functional area 310 includes a first power supply micro bump pad, a first ground micro bump pad, a system clock micro bump pad, a system reset micro bump pad and a programmable direct-connection micro bump pad, the first power supply micro bump pad is used for transmitting a system power supply signal VDD to the chip, the first ground micro bump pad is used for transmitting a common ground signal VSS to the chip, the system clock micro bump pad is used for transmitting a system clock signal sys_clk to the chip, the system reset micro bump pad is used for transmitting a system reset signal sys_rstn to the chip, and the programmable direct-connection micro bump pad is used for transmitting a configurable signal reconfig directly connected to the chip.

The second functional area 320 mainly provides power for the data path and the interface circuit to the chip, specifically, the second functional area 320 includes a data strobe micro bump pad, a channel reset micro bump pad, a data transmission micro bump pad, a second power micro bump pad, and a second ground micro bump pad, where the data strobe micro bump pad is used to transmit a data strobe signal line_strb to the chip, the channel reset micro bump pad is used to transmit a channel reset signal line_rstn, the data transmission micro bump pad is used to implement transmission of a data transmission signal line_data, the second power micro bump pad is used to provide an interface power signal VDDIO for the micro bump pad provided to the chip, and the second ground micro bump pad is used to provide an interface common ground signal VSSIO to the chip.

The second functional area 320 includes four data path areas, namely, a first data path area 301, a second data path area 302, a third data path area 303, and a fourth data path area 304. The four paths of data path areas are respectively and uniformly distributed with a data gating micro-bump pad, a channel resetting micro-bump pad, a data transmission micro-bump pad, a second power micro-bump pad and a second grounding micro-bump pad.

To reduce the power consumption of data communications, the data path interface supply voltage is typically less than the system supply voltage. In the embodiment of the application, the system power supply voltage may be 0.9V, the interface power supply voltage may be 0.8V, the system power supply voltage corresponds to a first power supply pad (a first power supply micro bump pad), and the interface power supply voltage corresponds to a second power supply pad (a second power supply micro bump pad).

In order to reduce the interference of digital circuits to analog cells in the data path, the active silicon interposer 20 isolates the common ground signal VSS and the interface common ground signal VSSIO during the design phase, and the present application is implemented by separately routing the two sets of ground signals and adding a dedicated isolation cell between the two sets of ground signals.

In ensuring that the pads for providing the functions of the first functional area 310 are disposed in the same consecutive area, and the pads for providing the functions of the second functional area are disposed under another consecutive area, for example, the pads of the first functional area 310 are all located on the left side of the active silicon interposer 20, the pads of the second functional area are all located on the right side of the active silicon interposer 20, and the types and the number of the pads included in each area can be set according to the actual situation, which is not particularly limited in the present application.

It should be noted that, the number of rows and columns corresponding to the standard pad array may be set according to the actual situation, and the number of rows and columns in each area may be set according to the actual situation.

Each of the four-way data path regions described above may operate independently and may be configured to Transmit (TX) or Receive (RX) data directions. For example, the first data path region 301 and the second data path region 302 are configured as transmit TX, the third data path region 303 and the fourth data path region 304 are configured as RX, and then the standard data operation mode is set. The first data path area 301 is configured as TX, the second data path area 302, the third data path area 303 and the fourth data path area 304 are configured as RX, and the operation mode is mainly the operation mode of receiving data. The first data path area 301, the second data path area 302, and the third data path area 303 are configured as TX, and the fourth data path area 304 is configured as RX, and the operation mode is mainly the data transmission mode. And, the third data path region 303 and the fourth data path region 304 are suspended, so that the pad array size of the chip may be smaller than a standard pad array size, for example, if the micro bump pad arrangement covered by the chip is not enough to have an array size of 7 rows and 11 columns, an array of 7 rows and 7 columns may be formed, and the chip may correspond to the first functional region 310, the first data path region 301 and the second data path region 302 on the third pad array 22, and may also implement a complete system function.

The number of the data path regions included in the second functional region is not particularly limited in the embodiment of the present application, for example, the second functional region 320 includes three data path regions and four data path regions.

Further, the package structure 100 based on the active silicon interposer provided by the embodiment of the present application may further include the following technical effects:

in the embodiment of the application, the bonding pads of the third bonding pad array 22 and the bonding pads of the fourth bonding pad array 31 of the chip are planned and set based on the same bonding pad layout, the third bonding pad array 22 can adapt to the chips with different array sizes, the multiplexing rate of the active silicon interposer 20 can be improved, the special active silicon interposer 20 is prevented from being set for the chips with different types, and the cost of the active silicon interposer 20 is reduced.

Referring to fig. 4, fig. 4 is a schematic diagram illustrating an interface function between a chip and an active silicon interposer according to an embodiment of the present application.

In the present embodiment, the active silicon interposer 20 is a chip that contains the basic logic of a common system chip, such as power management, clock reset signal generation, and communication functions. The active silicon interposer 20 is electrically connected to the chip by packaging and provides power and clock and reset signals to the chip to which it is connected. In addition, the active silicon interposer 20 also provides the data interconnect function of the chip. The active silicon interposer 20 performs data transfer functions via internal data links, thereby enabling data interaction between multiple chips in the chip module 30.

Illustratively, taking the example of the chip 1, the third pad array 22, and some of the pads in the fourth pad array 31a in fig. 1, the second functional area 310a in the fourth pad array 31a includes a data transmission micro bump pad 401a, the first functional area 320a includes a first power micro bump pad 402a, a first ground micro bump pad 403a, a system clock micro bump pad 404a, and a system reset micro bump pad 405a, and correspondingly, the second functional area 310b in the third pad array 22 includes a data transmission micro bump pad 401b, the first functional area 320b includes a first power micro bump pad 402b, a first ground micro bump pad 403b, a system clock micro bump pad 404b, and a system reset micro bump pad 405b. Specifically, the data transmission micro bump pad 401a of the fourth pad array 31a and the data transmission micro bump pad 401b of the third pad array 22 are connected through the first bump 32, so as to transmit data between the chip 1 and the active silicon interposer 20, correspondingly, the system clock micro bump pad 404 of the fourth pad array 31a and the system clock micro bump pad 404 of the third pad array 22 are connected through another first bump 32, so as to transmit a system clock signal sys_clk between the chip 1 and the active silicon interposer 20, and so on.

In the embodiment of the present application, a power management module, a clock management module, and a reset management module are disposed in the active silicon interposer 20, where the power management module is used to implement power supply. The clock management module is used for realizing system clock management, and the reset management module is used for realizing system reset management.

Referring to fig. 5, fig. 5 is a schematic diagram illustrating a pad layout of a chip according to an embodiment of the application.

As shown in fig. 5, a fourth pad array 31a is disposed on the surface 1a of the chip 1 corresponding to the active silicon interposer according to the pad layout plan described above, the fourth pad array 31a including one standard pad array, and the fourth pad array 31a including the first functional region 310 and the second functional region 320. The fourth pad array 31a of fig. 5 is only an example, and it is understood that the number of rows and columns of the fourth pad array 31a may be set according to circumstances, for example, the fourth pad array 31a may be set to 7 rows and 7 columns, etc., which is not particularly limited in the present application. The shape of each micro bump pad in the fourth pad array 31 is not particularly limited herein, and the disposition of the pads in each functional area in the fourth pad array may be set according to practical situations.

The pad placement on the active silicon interposer 20 will be described in detail below.

In the embodiment of the present application, the second pad array 21 and the third pad array 22 are disposed on the first surface 201 of the active silicon interposer 20, the second pad array 21 is located around the first surface 201, and the third pad array 22 is wrapped in the second pad array 21. In other embodiments, the second pad array 21 is located at the left half of the first surface 201, the third pad array 22 is located at the right half of the first surface 201, and the specific positional relationship between the second pad array 21 and the third pad array 22 is not specifically limited.

In the embodiment of the present application, a preset interval exists between a pad in the second pad array 21 and a pad in the third pad array 22, and the preset interval is set according to a first distance limitation and a second distance limitation, where the first distance limitation is a distance limitation between a chopper adopted when the second pad array 21 performs wire bonding and a corresponding chip, and the second distance limitation is a distance limitation between the third pad array 22 and an edge of the corresponding chip.

Specifically, after the chip is soldered to the third pad array 22 located at the center of the active silicon interposer 20, a distance limitation (i.e., a first distance limitation) exists between the chopper used when the second pad array 21 located around the active silicon interposer 20 performs the wire bonding process and the chip located inside, and a distance limitation (i.e., a second distance limitation) exists between the fourth pad array of the chip and the chip edge, and the distance limitations jointly determine the pitch limitation of the pads in the second pad array 21 and the pads in the third pad array 22.

In the embodiment of the present application, when the number of standard pad arrays in the third pad array 22 is greater than or equal to 2, the third pad array 22 further includes a fifth pad array arranged between the standard pad arrays, the fifth pad array including a power supply pad and a ground pad.

Referring to fig. 6, fig. 6 is a schematic diagram illustrating a pad layout of an active silicon interposer according to an embodiment of the present application.

As shown in fig. 6, the second pad array 21 is disposed around the first surface 201 of the active silicon interposer 20, and the third pad array 22 is disposed inside the first surface 201 of the active silicon interposer 20, and the third pad array 22 is surrounded by the second pad array 21. The third pad array 22 includes four standard pad arrays (601, 602, 603, and 604) and a fifth pad array 605.

The wire bond pads 211 in the second pad array 21 may have a shape of a broken square or a triangle. The bump pads 221 in the third pad array 22 may have a hexagonal shape, or may have a corner-missing square shape or a circular shape. The bump pad 221 may be a micro bump pad, and the shape of the wire bond pad 211 and the bump pad 221 is not particularly limited in the present application.

The fifth pad array 605 has a cross shape, and the fifth pad array 605 includes one row of pads and two columns of pads. The first power pads and the first ground pads in the fifth pad array 605 are uniformly distributed outside the standard pad array region.

In the embodiment of the present application, the active silicon interposer 20 includes a socket 23 thereon, and the socket 23 is an interface corresponding to each chip. Based on the sockets 23, a corresponding standard pad array may be divided, as shown in fig. 6, including four sockets 23, and accordingly, four standard pad arrays (601, 602, 603, and 604) are divided by the four sockets 23.

In some embodiments, the sockets 23 may also be disposed in the fifth pad array 605, for example, a row of sockets 23 may be disposed in two rows of pads of the fifth pad array 605, so that chips with different array sizes may be connected to the active silicon interposer 20 by flexibly positioning the sockets 23.

The side length of the wire bonding pads 211 may be 50um or the like, and the pitch of the wire bonding pads 211 may be 54um or the like. The bump pads 221 (e.g., micro bump pads) may have a side length of 72um or the like, and the bump pads 221 may have a pitch of 110um or the like. The predetermined spacing between the wire bond pads 211 in the second pad array 21 and the bump pads 221 in the third pad array 22 is approximately 300um. The specific size of the wire bond pad 211, the pitch of the wire bond pad 211, the specific size of the bump pad 221, the pitch of the bump pad 221, and the preset spacing between the bump pad 221 and the wire bond pad 211 are not particularly limited in the present application.

Fig. 6 includes four standard pad arrays in the third pad array 22, and each standard pad array is shown as the number of power pads and ground pads, which may be set according to practical situations, and the shape and size of the micro bump pads, the shape and size of the wire bonding pads, which may be set according to practical situations, which is not particularly limited in the present application.

In an embodiment of the present application, the number of bump pads in the third pad array 22 located in the active silicon interposer 20 is scalable, i.e., support scaling to multiple standard pad arrays and thus support multiple chips. Accordingly, the number of bump pads in the third pad array 22 is scalable, i.e., the size of the fourth pad array on the chip may be larger or smaller than a standard pad array size. For example, when the size of the fourth pad array on the chip is larger than one standard pad array size in the active silicon interposer 20, the chip may connect the bump pads in the fifth pad array, i.e., connect the first power pad and the first ground pad located between the standard pad arrays, thereby providing more sufficient power. When the size of the fourth pad array on the chip is smaller than a standard pad array size in the active silicon interposer 20, the chip can only connect to the bump pads for some of the necessary functions, as well as achieve full system functionality.

The standard pad arrays in the third pad array 22 of the active silicon interposer 20 are combinable, i.e., a plurality of standard pad arrays may be combined into one integral area, thereby supporting a large-sized chip occupying the plurality of standard pad arrays.

Referring to fig. 7, fig. 7 is a schematic diagram illustrating another pad layout of an active silicon interposer according to an embodiment of the present application.

As shown in fig. 7, a standard pad array on the active silicon interposer is provided in the pad layout shown in fig. 3. Four standard pad arrays (701, 702, 703, and 704) are included in fig. 7, and fig. 7 differs from fig. 6 in that the standard pad array in fig. 7 is 7 rows and 11 columns, and the fifth pad array 705 includes two rows of pads and two columns of pads. As shown in fig. 7, the first power pads and the first ground pads are uniformly distributed outside the standard pad array.

Taking the example of a standard pad array of 7 rows and 11 columns, when the fourth pad array of the chip is 8 rows and 12 columns, the bump pads in the chip-connectable active silicon interposer 20 include one bump pad of the standard pad array and the first power pad and the first ground pad from the fifth pad array adjacent to the standard pad array, providing a richer power electrical connection for the chip.

Illustratively, with the fourth land array 31b of the chip 2 being 9 rows and 13 columns, one standard land array of the third land array 22 being 7 rows and 11 columns, the fourth land array 31b of the chip 2 is soldered to the third land array 22 of the active silicon interposer 20, specifically, the bump pads in the standard land array 701 and the bump pads in the middle and the fifth land array 705 located near the standard land array 701, that is, the bump pads in the standard land array 701, and the two rows of the first power supply pads and the two columns of the bump pads near the standard land array 701, that is, the 9 rows and 13 columns occupying the third land array 22. The correct connection of the chip using the 9 row and 13 column bump array to the active silicon interposer is ensured by only ensuring that the chip functions consistently with the bump pads in the standard pad array in the active silicon interposer 20. At the same time, this does not affect the placement of the chips connected to standard pad arrays 702, 703 and 704. Thus, with such an active silicon interposer 20 with standardized pad layout, a richer bump array size option may be supported.

Referring to fig. 8, fig. 8 is a schematic diagram illustrating connection between the active silicon interposer and the chip shown in fig. 7.

As shown in fig. 8, a standard pad array on the active silicon interposer is provided in the pad layout shown in fig. 3. As shown in fig. 8, the fourth pad array 801 on the chip a connects part of the pads in the standard pad array 701, the fourth pad array 802 on the chip B connects all of the pads in the standard pad array 702 and part of the pads in the fifth pad array 705, the fourth pad array 803 on the chip C connects all of the pads in the standard pad array 703 and part of the pads in the fifth pad array 705, and the fourth pad array 804 on the chip D connects part of the pads in the standard pad array 704. Chip A and chip B are rotationally symmetrical, chip C and chip D are rotationally symmetrical, and standardized layout of micro bump pads in the chip can be well supported by adopting standardized pad layout planning. That is, the chip and the active silicon interposer 20 only need to use the same pad layout plan to deploy bump pads, so that the chip can be soldered to any standard array in the active silicon interposer 20 without mirroring the layout of the chip. A die with bump pads disposed using the same pad layout as the active silicon interposer 20 can be soldered to any of the standard pad array areas of fig. 7 by displacement and rotation.

Taking one complete first functional area 310 as 7 rows and 3 columns and any complete data path area in the second functional area 320 as 7 rows and 2 columns as an example, chips a through D shown in fig. 8 all cover the complete first functional area 310 and the complete data path area, for example, chip a covers 7 rows and 9 columns on the active silicon interposer, i.e., covers one complete first functional area and three complete data path areas (e.g., the first data path area 301, the second data path area 302, and the third data path area 303) on the active silicon interposer.

In other embodiments, the chip may not cover the complete first functional area and/or the complete data via area, e.g. chip a in fig. 8 may cover 6 rows 11 columns on the active silicon interposer, i.e. the incomplete first functional area and the incomplete four data via areas. For another example, the chip D in fig. 8 may cover 7 rows and 8 columns, i.e., one complete first functional area, two complete data via areas, and one incomplete data via area on the active silicon interposer.

It will be appreciated that, under the condition that the active silicon interposer and the bonding pads in the chip are both arranged according to the same bonding pad layout plan, the chip can be connected to the active silicon interposer according to practical situations, which is not particularly limited in the present application.

Referring to fig. 9, fig. 9 is another schematic diagram illustrating the connection between the active silicon interposer and the chip shown in fig. 7.

As shown in fig. 9, the fourth pad array 901 on the chip G connects all of the pads in the standard pad array 701, all of the pads in the standard pad array 703, and part of the pads in the fifth pad array 705, and the fourth pad array 902 on the chip H connects all of the pads in the standard pad array 702, all of the pads in the standard pad array 704, and part of the pads in the fifth pad array 705. While chip G and chip H are rotationally symmetrical.

When the chip is designed, the correct connection with the active silicon intermediary can be realized only by ensuring that the functions of the bump pads in the standard pad array area are consistent. The active silicon interposer 20 may support standard land array area integration to support a larger sized upper chip layout.

In some embodiments, all standard land array areas may be combined into one area, and a certain chip may be connected to the third land array 22 shown in fig. 7, that is, the third land array 22 may support a chip array size of 16 rows and 24 columns.

When the active silicon interposer is to be connected with two or more chips, the connection between the two or more chips and the active silicon interposer is adjusted according to the actual situation, and the rotational symmetry of the two or more chips is not limited, and the application is not particularly limited.

Referring to fig. 10, fig. 10 is a flow chart illustrating a method for manufacturing a package structure based on an active silicon interposer according to an embodiment of the application.

Step S101, providing a package carrier, and forming a first pad array on the package carrier.

The package carrier and the related content of the first pad array may be referred to above.

In the embodiment of the application, the first pad array can be deployed according to the specific type of the package carrier and further according to actual conditions. For example, when the package carrier is a package case, the first pad array may be disposed on the periphery of the package case. When the package carrier is a package substrate, the first pad array may be disposed around the upper surface of the package substrate. The arrangement manner and the arrangement position of the first pad array may be set according to practical situations, which is not particularly limited in the present application.

Step S102, providing an active silicon intermediate layer, forming a second pad array on the first surface of the active silicon intermediate layer, and forming a third pad array on the first surface according to the pad layout plan.

For the relevant content of the active silicon interposer, the second pad array and the third pad array, reference may be made to the above.

In the embodiment of the present application, the pads in the second pad array and the third pad array may be disposed according to a preset interval, and the positional relationship between the second pad array and the third pad array may be referred to above.

Step S103, providing a chip module, wherein the chip module comprises at least one chip, and a fourth bonding pad array is formed on the chip according to the bonding pad layout plan.

The related memories of the chip module, the chip and the third pad array may be referred to above.

In the embodiment of the present application, the pads in the third pad array and the fourth pad array are disposed according to the first functional area and the second functional area indicated by the same pad layout plan, and the specific content may refer to fig. 3 to fig. 9.

The execution sequence of the steps S101, S102, and S103 may be adjusted according to the actual situation.

Step S104, the fourth pad array and the third pad array are connected through the first bump.

The relevant memory of the first bump may refer to the above.

In the embodiment of the application, when the fourth pad array is generated on the chip, first bumps corresponding to the bump pads in the fourth pad array are generated, and then the chip is flip-chip bonded into the active silicon interposer so as to connect the fourth pad array and the third pad array through the first bumps.

In step S105, a second surface of the active silicon interposer is disposed on the package carrier, and the second pad array is connected to the first pad array through the first metal wire, and the second surface is opposite to the first surface.

The related memory of the first metal lead can be referred to above.

In the embodiment of the application, the second surface of the active silicon interposer is placed on the upper surface of the package carrier, and the second pad array of the active silicon interposer is electrically connected with the first pad array of the package carrier through wire bonding.

The above-described step S105 may be performed before step S104 is performed.

It will be appreciated by persons skilled in the art that the above embodiments have been provided for the purpose of illustrating the application and are not to be construed as limiting the application, and that suitable modifications and variations of the above embodiments are within the scope of the application as claimed.

Claims

1. An active silicon interposer-based package structure, comprising:

a package carrier including a first pad array;

an active silicon interposer over the package carrier, the active silicon interposer including a second pad array and a third pad array;

A first metal lead for connecting the second pad array and the first pad array;

the chip module is located above the active silicon intermediate layer, the chip module comprises at least one chip, the chip comprises a fourth pad array, pads in the fourth pad array and the third pad array are arranged according to the same pad layout plan, and the fourth pad array is connected with the third pad array through a first bump.

2. The active silicon interposer-based package structure of claim 1, wherein the active silicon interposer comprises opposing first and second surfaces, the first surface corresponding to the die set and the second surface corresponding to the package carrier;

the second pad array and the third pad array are positioned on the first surface, the second pad array is positioned on the periphery of the first surface, and the third pad array is wrapped in the second pad array.

3. The active silicon interposer-based package structure of claim 1 or 2, wherein the third pad array comprises at least one standard pad array set according to the pad layout plan, the fourth pad array comprises at least one standard pad array set according to the pad layout plan, the standard pad array comprises pads of a first functional region and pads of a second functional region, the pads of the first functional region comprise one or more of: the first power supply pad, the first grounding pad, the system clock pad, the system reset pad and the programmable direct connection pad, and the pads of the second functional area comprise one or more of the following pads: a data gate pad, a channel reset pad, a data transfer pad, a second power pad, and a second ground pad.

4. The active silicon interposer-based package structure of claim 3, wherein when the number of standard pad arrays in the third pad array is greater than or equal to 2, the third pad array has at least a pair of rotationally symmetrical standard pad arrays.

5. The active silicon interposer-based package structure of claim 3, wherein when the number of the standard pad arrays in the third pad array is greater than or equal to 2, the third pad array further comprises a fifth pad array arranged between the standard pad arrays, the fifth pad array comprising a first power pad and a first ground pad.

6. The active silicon interposer-based package structure of claim 1 or 2, wherein the first metal lead is a bonding lead, the first bump is a micro bump, and the micro bump is integrally formed with a pad in the fourth pad array.

7. The active silicon interposer-based package structure of claim 2, wherein there is a preset spacing between the pads in the second pad array and the pads in the third pad array.

8. The active silicon interposer-based package structure of claim 3, wherein a pitch of each pad in the third pad array is identical to a pitch of each pad in the fourth pad array, and functionally corresponding pads in the third pad array and the fourth pad array are connected by the first bump.

9. The active silicon interposer-based package structure of claim 1 or 2, wherein the package carrier comprises any one of a package substrate, a package case, or a wiring board.

10. A method for manufacturing a package structure based on an active silicon interposer, the method comprising:

providing a packaging carrier and forming a first pad array on the packaging carrier;

providing an active silicon interposer, forming a second pad array on a first surface of the active silicon interposer, and forming a third pad array on the first surface according to a pad layout plan;

providing a chip module, wherein the chip module comprises at least one chip, and a fourth pad array is formed on the chip according to the pad layout plan;

connecting the fourth pad array with the third pad array through a first bump;

a second surface of the active silicon interposer is placed on the package carrier and the second pad array is connected to the first pad array by a first metal lead, the second surface being opposite the first surface.