CN113299560B - Electroplating method of embedded packaging substrate with different pad apertures - Google Patents
Electroplating method of embedded packaging substrate with different pad apertures Download PDFInfo
- Publication number
- CN113299560B CN113299560B CN202110551590.7A CN202110551590A CN113299560B CN 113299560 B CN113299560 B CN 113299560B CN 202110551590 A CN202110551590 A CN 202110551590A CN 113299560 B CN113299560 B CN 113299560B
- Authority
- CN
- China
- Prior art keywords
- pad
- electroplating
- holes
- photoresist
- electroplated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000009713 electroplating Methods 0.000 title claims abstract description 132
- 239000000758 substrate Substances 0.000 title claims abstract description 99
- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 42
- 229920002120 photoresistant polymer Polymers 0.000 claims description 88
- 238000007747 plating Methods 0.000 claims description 27
- 239000011248 coating agent Substances 0.000 claims description 24
- 238000000576 coating method Methods 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 24
- 239000011148 porous material Substances 0.000 claims description 12
- 238000003825 pressing Methods 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 5
- 238000012163 sequencing technique Methods 0.000 claims description 3
- 238000003466 welding Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 230000000875 corresponding effect Effects 0.000 description 34
- 238000010030 laminating Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000004080 punching Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000002596 correlated effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The invention relates to an electroplating method of an embedded packaging substrate with different pad apertures, relates to the field of semiconductor packaging, and is used for solving the technical problem that when pads are electroplated on a pad hole of a substrate and a pad hole of an adapter plate, the thickness difference exists between the pad corresponding to the adapter plate and the pad corresponding to the substrate. The method comprises the following steps: determining the aperture of each welding pad hole; according to the aperture, grouping the pad holes with different pad apertures; and electroplating the pad holes in each group respectively. The technical scheme provided by the invention can eliminate the thickness difference between the bonding pad corresponding to the adapter plate and the bonding pad corresponding to the substrate.
Description
Technical Field
The invention relates to the field of semiconductor packaging, in particular to an electroplating method of an embedded packaging substrate with different pad apertures.
Background
In recent years, with the pursuit and urgent demand for smaller and lighter electronic devices, a substrate embedded package technology has been developed.
The embedded packaging technology is characterized in that passive elements such as resistors, capacitors and inductors or active devices such as chips are embedded into a packaging substrate, so that the advantages of shortening the length of interconnection lines among the devices, improving the electrical performance of transmission and improving the area utilization rate of the substrate are achieved, and meanwhile, a large number of plate surface bonding pads can be reduced, so that the packaging reliability is improved, the cost is reduced, and the embedded packaging technology is a highly ideal high-density packaging technology.
However, the pad aperture size of the interposer is usually much smaller than that of the substrate, which makes the thickness of the pad of the interposer inconsistent with that of the substrate when the pad is plated on the pad hole of the substrate and the pad hole of the interposer, thereby causing difficulty in subsequent processing.
Disclosure of Invention
In view of the above analysis, the present invention is directed to provide a method for electroplating an embedded package substrate with different pad aperture diameters, so as to solve the technical problem that when a pad is electroplated on a pad hole of a substrate and a pad hole of an interposer, the thickness difference exists between the pad corresponding to the interposer and the pad corresponding to the substrate.
The purpose of the invention is mainly realized by the following technical scheme:
the embodiment of the invention provides an electroplating method of an embedded packaging substrate with different bonding pad apertures, which comprises the following steps:
determining the aperture of each pad hole;
according to the aperture, grouping the bonding pad holes with different bonding pad apertures;
and electroplating the pad holes in each group respectively.
Further, the grouping of the pad holes of the different pad apertures according to the aperture includes:
and dividing the pad holes with the same and/or similar pore diameters into a group according to the pore diameters, wherein the pad holes with the similar pore diameters are the pad holes with the pore diameter difference within a preset value range.
Further, the electroplating the pad holes in each group respectively includes:
sequencing the aperture sizes corresponding to the groups to obtain the electroplating sequence of each group;
and respectively electroplating the pad holes of each group according to the electroplating sequence.
Further, the electroplating each of the groups of pad holes includes:
step 1, determining a pad hole to be electroplated;
and 4, removing the residual photoresist in the step 3.
Further, according to the electroplating sequence, when the group is the first electroplating sequence, the electroplating of the pad holes of the group of the first electroplating sequence comprises:
step 1, determining that the pad holes of the group of the first electroplating sequence are pad holes to be electroplated, namely first pad holes, and determining that the pad holes of the other groups are second pad holes;
and 4, removing the residual photoresist in the step 3.
Further, when the group is the last plating order according to the plating order, plating the pad holes of the group of the last plating order, including:
step 1, coating a bonding pad obtained by electroplating to obtain a packaging substrate coated with the photoresist;
and 3, removing the residual photoresist in the step 2.
Further, when the group is an intermediate plating order according to the plating order, plating the pad holes of the group of the intermediate plating order, including:
step 1, determining that the pad hole of the group of the middle electroplating sequence is a pad hole to be electroplated, namely a first pad hole, and determining that the pad hole which is not electroplated is a second pad hole;
and 4, removing the residual photoresist in the step 3.
Further, the step 3 comprises:
setting electroplating process parameters according to the aperture of the first pad hole, wherein the process parameters comprise: current density, plating time, and plating type.
Further, coating photoresist on the pad hole to be electroplated and the area outside the pad hole to be electroplated;
and photoetching the pad hole to be electroplated, and removing the photoresist in the pad hole to be electroplated.
Further, when the pad holes on the package substrate are to be provided with pad holes with different pad apertures, the electroplating of each group of pad holes includes:
s1, determining position information of a pad hole to be electroplated on the packaging substrate;
s2, arranging the pad hole to be electroplated on the packaging substrate according to the position information and the aperture of the pad hole;
s3, arranging a seed layer in the pad hole to be electroplated, and coating photoresist in the region outside the pad hole to be electroplated;
s4, electroplating the pad hole to be electroplated in the step S3;
and S5, removing the seed layer and the photoresist in the step S4.
Further, the determining the aperture of each pad hole includes:
and determining the preset aperture of each pad hole.
Compared with the prior art, the invention can realize the following beneficial effects:
the embodiment of the invention provides an electroplating method of an embedded package substrate with different pad apertures, which is characterized in that the aperture is taken as a reference, pad apertures are divided into a plurality of groups, and electroplating is carried out on the pad apertures in each group, so that electroplating parameters can be selected according to the pad apertures each time during electroplating, and the thickness of pads corresponding to each pad aperture is the same, thereby avoiding the problems that small-aperture pad apertures are fully electroplated and large-aperture pad apertures are not fully electroplated caused by simultaneous electroplating of the pad apertures with different apertures, and the problems that the small-aperture pad apertures and the large-aperture pad apertures are fully electroplated but the pads have height difference. In addition, the photoresist is arranged on the packaging substrate, the electroplated bonding pads are protected from being electroplated again, and technical support is provided for the method.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, wherein like reference numerals are used to designate like parts throughout.
FIG. 1 is a schematic structural diagram of a patch panel according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a package substrate obtained by an embedded package technology according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the device of FIG. 2 after punching;
FIG. 4 is a schematic diagram of the structure of the device of FIG. 3 after electroplating;
FIG. 5 is a schematic diagram of the structure of the device obtained in step 2 of example 1;
FIG. 6 is a schematic structural view of a device obtained in step 3 of example 1;
fig. 7 is a schematic structural diagram of a device obtained in step 6 of example 1.
Reference numerals are as follows:
1-connecting plate; 101-pads on the connection board; 2-a substrate; 201-pads on the substrate; 3-pressing the materials; 4-photoresist.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
The main structure of the device obtained by the buried package technology, as shown in fig. 1 and 2, mainly includes: a connecting plate 1, a substrate 2 and a laminating material 3. Wherein the press material 3 refers to the material used in the press process. The connecting plate 1 is provided with a bonding pad 101, the substrate 2 is provided with a bonding pad 201, and the diameter of the bonding pad 201 on the substrate is larger than that of the bonding pad 101 on the connecting plate. A portion of the connection plate 1 is embedded in the substrate 2, after which a bonding material 3 is provided on top of the connection plate 1 and the substrate 2. In actual processes, the lower half of the connection plate 1 is embedded in the substrate 2, but the lower half is not limited to this, and the connection plate 1 may be embedded in the substrate 2 entirely.
As can be seen from fig. 2, in the packaged device, the bonding pad 201 on the substrate and the bonding pad 101 on the connection board are both covered by the pressing material 3, and the circuit conduction cannot be achieved, so that a hole is punched in the surface of the pressing material 3, and the structure shown in fig. 3 is obtained, where D1 is the diameter of the bonding pad hole corresponding to the bonding pad 101 on the connection board, and D2 is the diameter of the bonding pad hole corresponding to the bonding pad 201 on the substrate. As can be seen from fig. 3, the size of D1 is positively correlated with the size of the pad 101 on the connection board, and the size of D2 is positively correlated with the size of the pad 201 on the substrate. As described above, the diameter of the pad 201 on the substrate is larger than that of the pad 101 on the connection board, and thus D2 is larger than D1.
After punching, new pads are respectively generated on each pad hole by electroplating, and each new pad corresponds to one on-board pad 101 or one on-substrate pad 201, that is, the on-board pad 101 and the on-substrate pad 201 covered under the laminating material 3 are "migrated" to the upper surface of the laminating material 3 by the above-mentioned method, so as to facilitate circuit connection, and the structure is shown in fig. 4.
In the prior art, the whole device shown in fig. 3 is usually placed in a plating bath for plating. Therefore, different electroplating process parameters cannot be selected according to different hole diameters of the pad hole, namely, two sets of process parameters such as current density, electroplating time and electroplating mode cannot be operated in one electroplating pool at the same time. Because D2 is greater than D1, and the plating speed in the plating bath is not substantially affected by the position, the pad hole corresponding to D1 needs to be plated before the pad hole corresponding to D2, and thus the thickness of the pad corresponding to D1 on the surface of the pressing material 3 needs to be greater than the thickness of the pad corresponding to D2. This is not conducive to subsequent processing of the device of fig. 4. Specifically, when flip chip interconnection is required subsequently, since the device in fig. 4 needs to be flipped, a high uniformity of the pads needs to be ensured as much as possible, otherwise, the bumps of the flip chip are broken or flip alignment accuracy is reduced.
In order to solve the above technical problem, an embodiment of the present invention provides a method for electroplating an embedded package substrate with different pad apertures, including the following steps:
step a, determining the aperture of each pad hole.
And b, grouping the pad holes with different pad apertures according to the aperture.
In the embodiment of the invention, the pad holes with the same and/or similar pore diameters are divided into a group according to the pore diameters, and the pad holes with the similar pore diameters are the pad holes with the pore diameter difference within a preset value range. And then sequencing the aperture sizes corresponding to the groups to obtain the electroplating sequence of each group, and respectively electroplating the pad holes of each group according to the electroplating sequence.
Specifically, when more than 3 kinds of apertures exist, the pad holes with smaller aperture difference can be simultaneously electroplated, that is, the pad holes with the aperture difference within the preset value range are divided into the same group. For example, there are three groups of pad holes, the aperture of which is divided into 30.1 μm, 30.2 μm and 60 μm, and the predetermined aperture difference is not larger than 1 μm. According to the value range of the preset aperture difference, the pad holes with the aperture of 30.1 μm and the pad holes with the aperture of 30.2 μm are divided into the same group, and then the pad holes with the aperture of 30.1 μm and the pad holes with the aperture of 30.2 μm can be simultaneously electroplated. It should be noted that the above examples are not to be construed as limiting the technical solutions of the present invention.
And c, respectively electroplating the pad holes corresponding to each group.
It should be noted that the foregoing scheme specifically includes two realizations: the first implementable manner is directed to a case where the pad holes of different pad apertures have been set on the package substrate, and the second implementable manner is directed to a case where the pad holes of different pad apertures are to be set, but the pad holes have not yet been set.
In the prior art, the manufacturing mode of the device is generally streamline, i.e. the confidentiality of the connection between the processes is emphasized, and all processing modes are completed in one process as much as possible. Specifically, punching on the surface of the laminating material is a processing mode, so in order to improve the processing efficiency, all the pad holes are punched in one process in the embodiment of the invention, namely, the first realizable mode corresponds to the situation. In addition, a seed layer is plated after the hole is punched, so that subsequent electroplating is facilitated.
For the first realization mode, the specific electroplating process comprises the following steps:
step 1, determining a pad hole to be electroplated.
And 2, coating photoresist on the region outside the pad hole to be electroplated to obtain the packaging substrate coated with the photoresist.
It should be noted that, in order to ensure uniform application and simplify the process of applying the photoresist, in the embodiment of the present invention, the photoresist is first applied to all the pad holes, and then the photoresist in the first pad hole is removed by photolithography. For example, a photoresist is applied to the device in fig. 3, and then the pad hole corresponding to D1 is subjected to photolithography, so as to obtain the structure shown in fig. 5. As can be seen from fig. 5, the above method can precisely cover the region other than the first pad hole with the photoresist 4.
And 3, electroplating the pad hole to be electroplated on the packaging substrate coated with the photoresist to obtain the pad.
And 4, removing the residual photoresist in the step 3.
For the first implementation, there are three application scenarios:
scene one
Electroplating the pad holes of the group in the first electroplating sequence according to the electroplating sequence, wherein the first electroplating is the first electroplating sequence, and the method comprises the following steps:
step 1, determining the group of the pad holes of the first electroplating sequence as the pad holes to be electroplated, namely the first pad holes, and determining the rest groups of the pad holes as the second pad holes.
And 2, coating photoresist to seal the second pad hole to obtain the packaging substrate coated with the photoresist.
and 4, removing the residual photoresist in the step 3.
Scene two
And electroplating the pad holes of the group in the final electroplating sequence according to the electroplating sequence, wherein the final electroplating is the final electroplating sequence, and the electroplating method comprises the following steps:
and step 1, coating the bonding pad obtained by electroplating to obtain the packaging substrate coated with the photoresist.
And 2, electroplating the pad holes of the group of the final electroplating sequence on the packaging substrate coated with the photoresist to obtain the pads.
And 3, removing the residual photoresist in the step 2.
In the embodiment of the invention, since other pad holes are completed, when the pad holes of the group of the final electroplating sequence are electroplated, the pad holes to be electroplated do not need to be determined.
Scene three
Plating pad holes of a group of intermediate plating orders in a plating order, an intermediate plating order referring to an order of the plating order between a first plating order and a last plating order, comprising the steps of:
step 1, determining the pad holes of the group of the middle electroplating sequence as pad holes to be electroplated, namely first pad holes, and determining the pad holes which are not electroplated as second pad holes.
In the embodiment of the invention, the smaller the diameter of the pad hole is, the less easily the residual photoresist in the pad hole is removed. It is necessary to preferentially plate the pad holes having the smallest aperture, that is, the first pad holes have a smaller aperture than the second pad holes.
And 2, coating photoresist to seal the second pad hole and coating the pad obtained by electroplating to obtain the packaging substrate coated with the photoresist.
In the embodiment of the invention, the second pad hole and the electroplated pad are not contacted with the electroplating solution in the electroplating process through the photoresist.
And 3, electroplating the first pad hole on the packaging substrate coated with the photoresist to obtain the pad.
And 4, removing the residual photoresist in the step 3.
In the embodiment of the invention, after electroplating, hardening of the residual photoresist can occur, which is not beneficial to photoetching of the next group of pad holes to be electroplated, so that the photoresist needs to be removed after electroplating, and the new photoresist is used for plugging the next group of pad holes which do not need to be electroplated and welded pads. The photoresist also needs to be removed when all the pad holes are completely plated, and thus, the removal of the remaining photoresist is terminated in scenarios one, two, and three.
Known from the above scenario, the pad holes with different apertures are separately electroplated, so that the electroplating process parameters can be set according to the current aperture of the pad hole to be electroplated, and the process parameters include: one or more of current density, electroplating time and electroplating type, thereby ensuring that the thicknesses of the bonding pads corresponding to the bonding pad holes with different apertures are consistent.
The embodiment of the invention provides another embedded package substrate electroplating method with different pad apertures, namely a second implementation mode, and the second implementation mode is that only one group of holes are drilled on a package substrate every time, then the drilled holes are electroplated, and then the process is repeated until all pad holes are electroplated.
The second implementation specifically includes the following steps:
s1, determining the position information of the pad hole to be electroplated on the packaging substrate.
And S2, arranging a pad hole to be electroplated on the packaging substrate according to the position information and the aperture of the pad hole.
In the embodiment of the present invention, the essence of the embedded package technology is to "migrate" the land upper pad 101 and the substrate upper pad 201 under the bonding material 3 to the upper surface of the bonding material 3, so that, in the second implementation, the aperture of the pad hole can be preset according to the size of the land upper pad 101 and the substrate upper pad 201. Similarly, the position information of the pad hole on the package substrate may be preset according to the position of the pad 101 on the connection board and the position of the pad 201 on the package base.
And S3, setting a seed layer in the pad hole to be electroplated, and coating photoresist in the region outside the pad hole to be electroplated.
In the embodiment of the invention, the seed layer is arranged in the pad hole to be electroplated, the surface of the area outside the pad hole to be electroplated is also covered by the seed layer, and the metal is deposited on the area covered by the seed layer during electroplating. In order to plate the upper pad only at the pad hole, it is necessary to coat a photoresist on the region outside the pad hole to be plated.
The aperture of the pad hole is small, and the area outside the pad hole to be electroplated are not easy to distinguish when coating the photoresist, so in order to improve the working efficiency, the embodiment of the invention firstly coats the photoresist on the whole surface of the pressing material 3, at the moment, the photoresist covers the area outside the pad hole to be electroplated and also covers the pad hole, at the moment, the pad hole needs to be subjected to photoetching, the photoresist in the pad hole is removed, and the photoresist is coated on the area outside the pad hole to be electroplated.
And S4, electroplating the pad hole to be electroplated in the step S3.
And S5, removing the seed layer and the photoresist in the step S3.
And performing the operation aiming at each group of the pad holes until all the pad holes are electroplated.
As can be seen from steps S1 to S5, the pad holes with different apertures are separately plated, so that the plating process parameters can be set according to the apertures of the pad holes to be plated, and the process parameters include: one or more of current density, electroplating time and electroplating type, thereby ensuring that the thicknesses of the corresponding welding pads of the welding pad holes with different apertures are consistent.
In the embodiment of the present invention, after the electroplating is completed, the seed layer exists on the upper surface of the bonding material 3, and the existence of the seed layer may affect the performance of the device, so the seed layer on the upper surface of the bonding material 3 is removed by an etching method. It should be noted that, both the first implementation manner and the second implementation manner need to perform the above operations.
To illustrate the feasibility of the above embodiment, the present invention takes the fabrication of the device in fig. 3 as an example, and the following embodiment is given, in which the specific structure is shown in fig. 1-7. Example 1 corresponds to a first possible embodiment, and example 2 corresponds to a second possible embodiment.
Example 1
Step 1, determining that a pad hole corresponding to a pad 101 on a connecting plate is a first pad hole, and a pad hole corresponding to a pad 201 on a substrate is a second pad hole.
In the embodiment of the invention, D1 is 30um, D2 is 60um, and the depth of the first pad hole is consistent with that of the second pad hole.
And 3, electroplating the first pad hole on the packaging substrate coated with the photoresist to obtain a pad on the connecting plate.
In the embodiment of the invention, the electroplating condition of the step 3 is that the electroplating current density is 0.8ASD, and the electroplating time is 60min. The structure of step 3 is shown in fig. 6.
And 4, removing the residual photoresist.
And 5, determining the pad hole corresponding to the pad 201 on the substrate as a second pad hole.
And 6, coating photoresist on the bonding pad on the connecting plate obtained in the step 3 and the bonding pad hole corresponding to the bonding pad 201 on the packaging substrate, and removing the photoresist on the bonding pad hole corresponding to the bonding pad 201 on the connecting plate in a photoetching mode.
In the embodiment of the present invention, the device structure obtained in step 6 is shown in fig. 7.
And 7, electroplating the second pad hole in the step 5 to obtain a pad on the package substrate.
In the embodiment of the invention, the electroplating condition of the step 7 is electroplating current density of 1.6ASD, and the electroplating time is 60min.
And 8, removing the photoresist coated on the bonding pad.
And 9, etching the device obtained in the step 8, and removing the seed layer on the surface of the laminating material 3.
In the embodiment of the present invention, the device structure obtained in step 9 is shown in fig. 4.
Example 2
And S1, determining the position information of a pad hole corresponding to the pad 101 on the connecting plate on the packaging substrate.
And S2, according to the position information and the aperture of the pad hole, forming a pad hole corresponding to the pad 101 on the connecting plate on the packaging substrate by using laser.
And S3, arranging a seed layer in a pad hole corresponding to the pad 101 on the connecting plate, and coating photoresist in a region except the pad hole to be electroplated.
And S4, electroplating the pad hole corresponding to the pad 101 on the connecting plate.
In the embodiment of the invention, the electroplating condition of the step 3 is that the electroplating current density is 0.8ASD, and the electroplating time is 60min.
And S5, removing the seed layer and the photoresist in the step S3.
And S6, determining the position information of the pad hole corresponding to the pad 201 on the substrate on the packaging substrate.
And S7, according to the position information and the aperture of the pad hole, forming a pad hole corresponding to the pad 201 on the substrate on the packaging substrate by using laser.
Step S8, a seed layer is disposed in the pad hole corresponding to the pad 201 on the substrate, and the region outside the pad hole corresponding to the pad 201 on the substrate is coated with a photoresist.
And S9, electroplating the pad holes corresponding to the pads 201 on the substrate.
In the embodiment of the present invention, the plating condition in step S9 is a plating current density of 0.8ASD and a plating time of 120min.
And S10, removing the photoresist covering the bonding pad.
And S11, etching the device obtained in the step S10, and removing the seed layer on the surface of the laminating material 3.
In the embodiment of the invention, the seed layer electroplating process cannot be controlled only for the pad hole, so that the seed layer is inevitably generated on the surface of the laminating material 3 while the seed layer is arranged for the pad hole.
In embodiment 2, D1 is 30um and D2 is 60um, and the depth of the pad hole corresponding to the pad 101 on the connection board is the same as the depth of the pad hole corresponding to the pad 201 on the second substrate.
As can be seen from the embodiments 1 and 2, the embodiment of the present invention can respectively perform electroplating on pad holes with different apertures, so as to ensure that the pad heights on the surface of the bonding material 3 are the same. In practical implementation, all pad holes can be drilled at one time, as in example 1. It is also possible to perforate in several portions, as in example 2.
While the invention has been described with reference to specific preferred embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.
Claims (10)
1. The electroplating method of the embedded packaging substrate with different pad apertures is characterized in that the packaging substrate comprises a connecting plate, a substrate and a pressing material, wherein pads are arranged on the connecting plate and the substrate, the pressing material is arranged on the connecting plate and the substrate, and pad holes are arranged on the pressing material to expose the pads on the connecting plate and the substrate; the electroplating method comprises the following steps:
determining the aperture of each pad hole;
according to the aperture, grouping the bonding pad holes with different bonding pad apertures;
electroplating the pad holes in each group respectively;
and forming new bonding pads on the bonding pad holes respectively through electroplating, wherein each new bonding pad corresponds to a bonding pad on the connecting plate or a bonding pad on the substrate.
2. The method of claim 1,
the grouping of the pad holes of the different pad apertures according to the aperture includes:
and dividing the pad holes with the same and/or similar pore diameters into a group according to the pore diameters, wherein the pad holes with the similar pore diameters are the pad holes with the pore diameter difference within a preset value range.
3. The method of claim 2,
the electroplating of the pad holes in each of the groups, respectively, includes:
sequencing the sizes of the apertures corresponding to the groups to obtain the electroplating sequence of each group;
and respectively electroplating the pad holes of each group according to the electroplating sequence.
4. The method according to any one of claims 1 to 3,
electroplating the pad holes of each group, including:
step 1, determining a pad hole to be electroplated;
step 2, coating photoresist on the region outside the pad hole to be electroplated to obtain a package substrate coated with the photoresist;
step 3, electroplating the pad hole to be electroplated on the packaging substrate coated with the photoresist to obtain a pad;
and 4, removing the residual photoresist in the step 3.
5. The method of claim 3,
and according to the electroplating sequence, when the group is the first electroplating sequence, electroplating the pad holes of the group of the first electroplating sequence, wherein the electroplating comprises the following steps:
step 1, determining that the pad holes of the group of the first electroplating sequence are to-be-electroplated pad holes, namely first pad holes, and the pad holes of the other groups are second pad holes;
step 2, coating photoresist to seal the second pad hole to obtain a package substrate coated with the photoresist;
step 3, electroplating the first pad hole on the packaging substrate coated with the photoresist to obtain a pad;
and 4, removing the residual photoresist in the step 3.
6. The method of claim 5,
and according to the electroplating sequence, when the group is the final electroplating sequence, electroplating the pad holes of the group of the final electroplating sequence, wherein the electroplating sequence comprises the following steps:
step 1, coating a bonding pad obtained by electroplating to obtain a packaging substrate coated with the photoresist;
step 2, electroplating the pad holes of the group of the final electroplating sequence on the packaging substrate coated with the photoresist to obtain pads;
and 3, removing the residual photoresist in the step 2.
7. The method of claim 6,
and according to the electroplating sequence, when the group is the middle electroplating sequence, electroplating the pad holes of the group in the middle electroplating sequence, wherein the electroplating comprises the following steps:
step 1, determining that the pad holes of the group of the middle electroplating sequence are pad holes to be electroplated, namely first pad holes, and determining that the pad holes which are not electroplated are second pad holes;
step 2, coating the photoresist to seal the second pad hole and coating the pad obtained by electroplating to obtain a package substrate coated with the photoresist;
step 3, electroplating a first pad hole on the packaging substrate coated with the photoresist to obtain a pad;
and 4, removing the residual photoresist in the step 3.
8. The method of claim 4,
the step 3 comprises the following steps:
setting electroplating process parameters according to the aperture of the pad hole to be electroplated, wherein the process parameters comprise: current density, plating time, and plating type.
9. The method of claim 4, wherein the step 2 comprises:
coating photoresist on the pad hole to be electroplated and the area outside the pad hole to be electroplated;
and photoetching the pad hole to be electroplated, and removing the photoresist in the pad hole to be electroplated.
10. The method of claim 3, wherein when the pad holes on the package substrate are to be set to different pad hole diameters, the electroplating each group of pad holes comprises:
s1, determining position information of a pad hole to be electroplated on the packaging substrate;
s2, arranging the pad hole to be electroplated on the packaging substrate according to the position information and the aperture of the pad hole;
s3, arranging a seed layer in the pad hole to be electroplated, and coating photoresist in the region outside the pad hole to be electroplated;
s4, electroplating the pad hole to be electroplated in the step S3;
and S5, removing the seed layer and the photoresist in the step S4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110551590.7A CN113299560B (en) | 2021-05-20 | 2021-05-20 | Electroplating method of embedded packaging substrate with different pad apertures |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110551590.7A CN113299560B (en) | 2021-05-20 | 2021-05-20 | Electroplating method of embedded packaging substrate with different pad apertures |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113299560A CN113299560A (en) | 2021-08-24 |
| CN113299560B true CN113299560B (en) | 2022-12-27 |
Family
ID=77323086
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110551590.7A Active CN113299560B (en) | 2021-05-20 | 2021-05-20 | Electroplating method of embedded packaging substrate with different pad apertures |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113299560B (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI225699B (en) * | 2003-07-22 | 2004-12-21 | Advanced Semiconductor Eng | Bumping process |
| TWI255158B (en) * | 2004-09-01 | 2006-05-11 | Phoenix Prec Technology Corp | Method for fabricating electrical connecting member of circuit board |
| TWI250834B (en) * | 2004-11-03 | 2006-03-01 | Phoenix Prec Technology Corp | Method for fabricating electrical connections of circuit board |
| US10797012B2 (en) * | 2017-08-25 | 2020-10-06 | Dialog Semiconductor (Uk) Limited | Multi-pin-wafer-level-chip-scale-packaging solution for high power semiconductor devices |
-
2021
- 2021-05-20 CN CN202110551590.7A patent/CN113299560B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN113299560A (en) | 2021-08-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106876356B (en) | Chip embedded silicon-based fan-out type packaging structure and manufacturing method thereof | |
| US10177011B2 (en) | Chip packaging method by using a temporary carrier for flattening a multi-layer structure | |
| US20020076855A1 (en) | Method, apparatus and system for building an interposer onto a semiconductor wafer using laser techniques | |
| US9281286B1 (en) | Microelectronic packages having texturized solder pads and methods for the fabrication thereof | |
| US20040099960A1 (en) | Economical high density chip carrier | |
| US20120020039A1 (en) | Surface-mounted shielded multicomponent assembly | |
| JP2008016855A (en) | Semiconductor device with laminated chip and method for manufacturing it | |
| CN110707075A (en) | Three-dimensional fan-out type packaging structure of ultrahigh-density multi-chip module and preparation method | |
| JP2011139064A (en) | Circuit board and method for manufacturing the same | |
| CN104769713A (en) | Semiconductor device including independent film layer for embedding and/or spacing semiconductor die | |
| CN102386104A (en) | Quadrilateral flat pin-free encapsulation method | |
| CN103904044A (en) | Fan-out wafer-level packaging structure and manufacturing technology | |
| CN109509727B (en) | Semiconductor chip packaging method and packaging structure | |
| US10959328B2 (en) | Wiring substrate, stacked wiring substrate, and manufacturing method of wiring substrate | |
| CN102386105A (en) | Packaging method with four flat sides and without pin and structure manufactured by packaging method | |
| US20200365492A1 (en) | Package with lead frame with improved lead design for discrete electrical components and manufacturing the same | |
| CN113299560B (en) | Electroplating method of embedded packaging substrate with different pad apertures | |
| US10770432B2 (en) | ASICS face to face self assembly | |
| CN103325692A (en) | Manufacturing method of semiconductor device fan-out flip chip packaging structure | |
| CN105575911A (en) | Semiconductor package and fabrication method thereof | |
| CN101211792A (en) | Semi-conductor package and its manufacture method and stacking structure | |
| US9576917B1 (en) | Embedded die in panel method and structure | |
| US7727861B2 (en) | Method and device for contacting semiconductor chips | |
| CN210073829U (en) | Structure for packaging FOSiP of ultrahigh-density chip | |
| CN210640243U (en) | Three-dimensional fan-out type packaging structure of ultrahigh-density multi-chip module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |