CN113299549A - Small signal tube core back gold process - Google Patents
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- CN113299549A CN113299549A CN202110555614.6A CN202110555614A CN113299549A CN 113299549 A CN113299549 A CN 113299549A CN 202110555614 A CN202110555614 A CN 202110555614A CN 113299549 A CN113299549 A CN 113299549A
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- 239000010931 gold Substances 0.000 title claims abstract description 61
- 238000000034 method Methods 0.000 title claims abstract description 47
- 230000008569 process Effects 0.000 title claims abstract description 42
- 229910052737 gold Inorganic materials 0.000 title claims abstract description 39
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 title claims abstract description 24
- 238000001704 evaporation Methods 0.000 claims abstract description 37
- 230000008020 evaporation Effects 0.000 claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 28
- 230000008021 deposition Effects 0.000 claims abstract description 26
- 239000000956 alloy Substances 0.000 claims abstract description 17
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 17
- 230000001681 protective effect Effects 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims description 30
- 229910008433 SnCU Inorganic materials 0.000 claims description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 238000005260 corrosion Methods 0.000 claims description 2
- 230000007797 corrosion Effects 0.000 claims description 2
- 238000004806 packaging method and process Methods 0.000 abstract description 18
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- 238000011161 development Methods 0.000 description 6
- 238000004880 explosion Methods 0.000 description 5
- 230000002159 abnormal effect Effects 0.000 description 4
- 239000010970 precious metal Substances 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910000510 noble metal Inorganic materials 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 241001133184 Colletotrichum agaves Species 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a small signal tube core back gold process, which specifically comprises the following steps: the front side of the wafer is pasted with a protective film, the back side of the wafer is thinned to a certain thickness, the thinned thickness is 3-10 mu m, the protective film layer on the front side of the wafer is removed, so that the subsequent process can be continued, a Ti/AL film layer is deposited through an evaporation table of special semiconductor equipment, the Ti deposition temperature is 180-260 ℃, the AL deposition temperature is 150-240 ℃, a furnace tube alloy after Ti/AL deposition on the back side of the wafer, N2 gas and H2 gas atmosphere alloy, the alloy temperature is 380-480 ℃, the Ti/AL film layer is deposited through the evaporation table of special semiconductor equipment, the thickness of a Ti metal film is 0.05-0.2 mu m, the AL deposition temperature is 1-8 mu m, the furnace tube alloy after Ti/AL deposition on the back side of the wafer, and the N2 gas and H2 atmosphere alloy. The back gold process of the small signal tube core reduces the manufacturing cost of the back gold process of a chip enterprise on the whole, improves the convenience of packaging and mounting chips, the reliability of chip bonding, improves the pulling force, reduces the quality cost of packaging and increases the competitiveness and profit of products.
Description
Technical Field
The invention relates to the field of back gold processes, in particular to a back gold process of a small-signal tube core.
Background
The small signal tube core back-gold process is a process for carrying out back-gold processing on a small signal tube core, the area size of the small signal tube core is smaller than 1mm x 1mm, the small tube core has a special and necessary application way, the market is wide, the small signal tube core is suitable for circuits of various miniature or medium-large portable equipment, the package is mostly in a small device package form such as SOT23, and the like, the small signal tube in the package form has irreplaceable functions in the circuit application, so the package reliability is very critical, the small-sized tube core is very difficult to be stuck on a package frame, the small-sized tube core back-gold process is a key factor for blocking the batch package of the small tube core, and the reason is that the slow development of the small signal tube core back-gold process lags behind the rapid development of the small signal tube core package sticking;
however, the traditional large die back-gold process is seriously not suitable for the use of small dies, most of the small die back-gold processes still use the traditional large die back-gold processes such as Cr/Ni/Au, Ti/Ni/Au or Ti// SnCu/Au, etc., are not beneficial to the die mounting and die bonding processes of the small die SOT23 packaging frame, the phenomenon of tube explosion (die cracking) caused by large back-gold metal layer stress can occur when the die mounting temperature is increased to increase the die bonding force in the packaging process, and the phenomenon of small back-gold metal layer tension or no tension occurs after the common batch packaging bonding, etc., which seriously obstruct the continuous requirements of batch packaging and market of small signal dies, bring greater quality cost to packaging enterprises, and obstruct the development and progress of small signal die packaging; another cost problem is that in order to increase the pulling force of the small tube core eutectic process, the common method in the back gold process is to increase the thickness of the precious metal gold film layer, while the precious metal gold is very expensive, and in the case of increasing the thickness of the gold film layer, the manufacturing cost of the chip enterprise is increased undoubtedly, and the gold film thickness of part of the small tube cores has reached the goal
It is already a significant cost of the small tube core manufacturing that has to be taken into account for the reduction.
Disclosure of Invention
The invention mainly aims to provide a small-signal tube core back gold process, which can effectively solve the problems in the background technology that: the problems of convenience in packaging chips, chip bonding garbage and material cost of chip manufacturing enterprises are solved, manufacturing and packaging pain points of small-size tube cores are thoroughly improved, development of the small-tube-core transistor market is promoted, and device cost of terminal application is reduced.
In order to achieve the purpose, the invention adopts the technical scheme that:
the small signal tube core back gold process specifically comprises the following steps:
the method comprises the following steps: thinning the wafer by pasting a film, pasting a protective film on the front side of the wafer, thinning the back side of the wafer by a certain thickness, and thinning the back side of the wafer by 3-10 um;
step two: removing the film layer, and removing the protective film layer on the front side of the wafer after the back side of the wafer is thinned;
step three: performing primary evaporation, and depositing a Ti/AL film layer through an evaporation table of special semiconductor equipment, wherein the Ti deposition temperature is 180-260 ℃, and the AL deposition temperature is 150-240 ℃;
step four: performing secondary evaporation, namely depositing a Ti/AL film layer through an evaporation table of special semiconductor equipment, wherein the thickness of a Ti metal film is 0.05-0.2um, and the deposition temperature of AL is 1-8 um;
step five: evaporating for the third time, and then, after depositing Ti/AL on the back surface of the wafer, performing furnace tube alloy, N2 gas and H2 gas atmosphere alloy, wherein the alloy temperature is 380-480 ℃;
step six: and (4) evaporating for four times, and then feeding the alloyed wafer into an evaporation table to deposit Ti/Ni/SnCu/Au, wherein the deposition temperatures are respectively Ti: 160 ℃ -240 ℃, Ni: 120-200 ℃, SnCu: 40-100 ℃, Au: 40-80 ℃; the deposition rate is based on the optimal condition of an actual evaporation table;
step seven: and (4) five times of evaporation, wherein the alloyed wafer enters an evaporation table again to deposit Ti/Ni/SnCu/Au, and the film thicknesses are respectively Ti: 0.05-0.2um, Ni: 0.1-0.5um, SnCu: 2-10um, Au: 0.05-1.0 um;
step eight: and finishing the deposition, and finishing the deposition of the back metal process on the wafer.
As a further scheme of the invention, in the first step, a protective film is firstly attached to the front surface of the wafer to protect the front surface of the wafer, and then the back surface of the wafer is etched and thinned through silicon etching.
As a further scheme of the invention, in the second step, the protective film layer on the front surface of the wafer is removed by the suction device, and the wafer is cleaned while the protective film on the front surface of the wafer is removed.
As a further aspect of the present invention, the third step, the fourth step and the fifth step are performed simultaneously, the sixth step and the seventh step are performed simultaneously, and the sixth step and the seventh step are arranged in the next step of the third step, the fourth step and the fifth step.
As a further scheme of the present invention, in the sixth step, SnCu is an alloy, and the SnCu needs a metal tungsten boat to contain the source material.
And as a further scheme of the invention, the thickness of the Ti/Ni/SnCu/Au film layer in the seventh step is the thickness of the middle film layer.
As a further scheme of the present invention, in the eighth step, six layers of metal structures are arranged below the silicon substrate after evaporation, and the silicon substrate, Ti, AL, Ti, Ni, SnCu, and Au are arranged in sequence.
Compared with the prior art, the invention has the following beneficial effects:
the thickness of the metal Au is biased to 3%, 5%, 10%, 20%, 50% and the like, even if the thickness of the metal Au is 3% thick, the tensile force is still unchanged, stable and reliable, the phenomenon of abnormal tube explosion basically disappears, and even if the number of the metal layer films is increased, the cost of the whole back gold process is reduced by about 30%, so that the problem of the chip manufacturing cost is solved, the tensile force and the phenomenon of abnormal tube explosion of a packaging enterprise are solved, the problems of packaging and sheet sticking of a small tube core are thoroughly solved, the market development of a small tube core device is promoted, the film thickness of the precious metal Au is reduced by increasing the metal layer structure, the manufacturing cost of the back gold process of the chip enterprise is reduced on the whole, the convenience of packaging and sheet sticking is improved, the reliability of the sheet sticking is improved, the tensile force is improved, the quality cost of packaging is reduced, and the competitiveness and the profit of products are increased.
Drawings
FIG. 1 is a flow chart of the steps of a small signal die back-gold process of the present invention;
FIG. 2 is a diagram of a backside metal layer process and design for a small signal die backside gold process according to the present invention.
Detailed Description
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further described with the specific embodiments.
As shown in fig. 1-2, the small signal die back gold process specifically includes the following steps:
the method comprises the following steps: thinning the wafer by pasting a film, pasting a protective film on the front side of the wafer, thinning the back side of the wafer by a certain thickness, and thinning the back side of the wafer by 3-10 um;
step two: removing the film layer, and removing the protective film layer on the front side of the wafer after the back side of the wafer is thinned;
step three: performing primary evaporation, and depositing a Ti/AL film layer through an evaporation table of special semiconductor equipment, wherein the Ti deposition temperature is 180-260 ℃, and the AL deposition temperature is 150-240 ℃;
step four: performing secondary evaporation, namely depositing a Ti/AL film layer through an evaporation table of special semiconductor equipment, wherein the thickness of a Ti metal film is 0.05-0.2um, and the deposition temperature of AL is 1-8 um;
step five: evaporating for the third time, and then, after depositing Ti/AL on the back surface of the wafer, performing furnace tube alloy, N2 gas and H2 gas atmosphere alloy, wherein the alloy temperature is 380-480 ℃;
step six: and (4) evaporating for four times, and then feeding the alloyed wafer into an evaporation table to deposit Ti/Ni/SnCu/Au, wherein the deposition temperatures are respectively Ti: 160 ℃ -240 ℃, Ni: 120-200 ℃, SnCu: 40-100 ℃, Au: 40-80 ℃; the deposition rate is based on the optimal condition of an actual evaporation table;
step seven: and (4) five times of evaporation, wherein the alloyed wafer enters an evaporation table again to deposit Ti/Ni/SnCu/Au, and the film thicknesses are respectively Ti: 0.05-0.2um, Ni: 0.1-0.5um, SnCu: 2-10um, Au: 0.05-1.0 um;
step eight: after the deposition is finished, the wafer finishes the deposition of the back metal process;
in the first step, firstly, a protective film is pasted on the front surface of the wafer to protect the front surface of the wafer, and then the back surface of the wafer is corroded and thinned through silicon corrosion.
And in the second step, the protective film layer on the front surface of the wafer is removed through the suction equipment, and the wafer is cleaned while the protective film on the front surface of the wafer is removed.
And step three, step four and step five are used for synchronously evaporating, step six and step seven are used for synchronously evaporating, and step six and step seven are arranged in the next step of step three, step four and step five.
And in the sixth step, the SnCu is an alloy, and the SnCu needs a metal tungsten boat to contain source materials.
And in the seventh step, the thickness of the Ti/Ni/SnCu/Au film layer is the thickness of the middle film layer.
And eighthly, forming a six-layer metal structure below the evaporated silicon substrate, wherein the silicon substrate, the Ti, the AL, the Ti, the Ni, the SnCu and the Au are sequentially arranged.
The process of the invention changes the front back gold process from 3 layers of metal to 6 layers of metal, but the cost for processing materials is doubled, and the price of each metal layer is researched to overcome the problem, only the noble metal gold accounts for about 60% of the material cost, if the film thickness of the noble metal gold is reduced, although the metal film layer is increased, the manufacturing cost of the back process is not increased, the invention draws the thickness of the metal Au to 3%, 5%, 10%, 20%, 50% and the like according to the thought, even if the film thickness of the metal Au is 3%, the pulling force is still unchanged, stable and reliable, the abnormal tube explosion phenomenon basically disappears, even if the number of the layers of the metal film is increased, the cost of the whole back gold process is reduced by about 30%, thus not only solving the cost problem of chip manufacturing, but also solving the pulling force and the abnormal tube explosion phenomenon of packaging enterprises, the packaging and chip mounting method thoroughly solves the problems of packaging and chip mounting of the small tube core, promotes market development of small tube core devices, thins the thickness of a film layer of the precious metal Au by increasing the metal layer structure, generally reduces the manufacturing cost of a back gold process of a chip enterprise, improves the convenience of packaging and chip mounting, improves the reliability of the chip mounting, promotes the pulling force, reduces the quality cost of packaging, and increases the competitiveness and profit of products.
The foregoing shows and describes the general principles and broad features of the present invention and advantages thereof. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (7)
1. The small signal tube core back gold process is characterized in that: the process specifically comprises the following steps:
the method comprises the following steps: thinning the wafer film, pasting a protective film on the front surface of the wafer, thinning the back surface of the wafer, and enabling the thinning thickness to be 3-10 um;
step two: removing the film layer, and removing the protective film layer on the front side of the wafer after the back side of the wafer is thinned;
step three: performing primary evaporation, and depositing a Ti/AL film layer through an evaporation table of special semiconductor equipment, wherein the Ti deposition temperature is 180-260 ℃, and the AL deposition temperature is 150-240 ℃;
step four: performing secondary evaporation, namely depositing a Ti/AL film layer through an evaporation table of special semiconductor equipment, wherein the thickness of a Ti metal film is 0.05-0.2um, and the deposition temperature of AL is 1-8 um;
step five: evaporating for the third time, and then, after depositing Ti/AL on the back surface of the wafer, performing furnace tube alloy, N2 gas and H2 gas atmosphere alloy, wherein the alloy temperature is 380-480 ℃;
step six: and (4) evaporating for four times, and then feeding the alloyed wafer into an evaporation table to deposit Ti/Ni/SnCu/Au, wherein the deposition temperatures are respectively Ti: 160 ℃ -240 ℃, Ni: 120-200 ℃, SnCu: 40-100 ℃, Au: 40-80 ℃; the deposition rate is based on the optimal condition of an actual evaporation table;
step seven: and (4) five times of evaporation, wherein the alloyed wafer enters an evaporation table again to deposit Ti/Ni/SnCu/Au, and the film thicknesses are respectively Ti: 0.05-0.2um, Ni: 0.1-0.5um, SnCu: 2-10um, Au: 0.05-1.0 um;
step eight: and finishing the deposition, and finishing the deposition of the back metal process on the wafer.
2. The small signal die gold-backed process of claim 1, wherein: in the first step, firstly, a protective film is pasted on the front surface of the wafer to protect the front surface of the wafer, and then the back surface of the wafer is corroded and thinned through silicon corrosion.
3. The small signal die gold-backed process of claim 1, wherein: and in the second step, the protective film layer on the front surface of the wafer is removed through the suction equipment, and the wafer is cleaned while the protective film on the front surface of the wafer is removed.
4. The small signal die gold-backed process of claim 1, wherein: and the third step, the fourth step and the fifth step are synchronously performed with evaporation, the sixth step and the seventh step are synchronously performed with evaporation, and the sixth step and the seventh step are arranged in the next step of the third step, the fourth step and the fifth step.
5. The small signal die gold-backed process of claim 1, wherein: and in the sixth step, SnCu is an alloy, and needs a metal tungsten boat to contain source materials.
6. The small signal die gold-backed process of claim 1, wherein: and in the seventh step, the thickness of the Ti/Ni/SnCu/Au film layer is the thickness of the middle film layer.
7. The small signal die gold-backed process of claim 6, wherein: and eighthly, arranging six layers of metal structures below the evaporated silicon substrate in sequence of the silicon substrate, Ti, AL, Ti, Ni, SnCu and Au.
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| CN202110555614.6A CN113299549A (en) | 2021-05-21 | 2021-05-21 | Small signal tube core back gold process |
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| CN202110555614.6A CN113299549A (en) | 2021-05-21 | 2021-05-21 | Small signal tube core back gold process |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102254843A (en) * | 2011-06-27 | 2011-11-23 | 江阴新顺微电子有限公司 | Method for metalizing back of semiconductor chip applied to eutectic packaging |
| CN102522326A (en) * | 2011-12-14 | 2012-06-27 | 杭州立昂微电子股份有限公司 | Production method of semiconductor discrete device back side metal suitable for screen printing |
| US20140151866A1 (en) * | 2012-11-30 | 2014-06-05 | Infineon Technologies Ag | Packaged Semiconductor Device with Tensile Stress and Method of Making a Packaged Semiconductor Device with Tensile Stress |
| CN109037175A (en) * | 2018-07-17 | 2018-12-18 | 盛世瑶兰（深圳）科技有限公司 | power device and its packaging method |
| JP2019012756A (en) * | 2017-06-29 | 2019-01-24 | 株式会社テンシックス | Manufacturing method of semiconductor element substrate |
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2021
- 2021-05-21 CN CN202110555614.6A patent/CN113299549A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102254843A (en) * | 2011-06-27 | 2011-11-23 | 江阴新顺微电子有限公司 | Method for metalizing back of semiconductor chip applied to eutectic packaging |
| CN102522326A (en) * | 2011-12-14 | 2012-06-27 | 杭州立昂微电子股份有限公司 | Production method of semiconductor discrete device back side metal suitable for screen printing |
| US20140151866A1 (en) * | 2012-11-30 | 2014-06-05 | Infineon Technologies Ag | Packaged Semiconductor Device with Tensile Stress and Method of Making a Packaged Semiconductor Device with Tensile Stress |
| JP2019012756A (en) * | 2017-06-29 | 2019-01-24 | 株式会社テンシックス | Manufacturing method of semiconductor element substrate |
| CN109037175A (en) * | 2018-07-17 | 2018-12-18 | 盛世瑶兰（深圳）科技有限公司 | power device and its packaging method |
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