CN113296734A - Multi-position storage device - Google Patents
Multi-position storage device Download PDFInfo
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- CN113296734A CN113296734A CN202110853570.5A CN202110853570A CN113296734A CN 113296734 A CN113296734 A CN 113296734A CN 202110853570 A CN202110853570 A CN 202110853570A CN 113296734 A CN113296734 A CN 113296734A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
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- G06N3/045—Combinations of networks
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
Abstract
The present invention relates to a multi-bit storage apparatus. The device comprises a memory cell array module, an input driver, a read-write bit line driving module, a row decoder and a voltage-sharing module, wherein the memory cell array module is connected with the input driver, the read-write bit line driving module, the row decoder and the voltage-sharing module; the voltage equalizing module is connected with the multiply-accumulate read-out control module; the input driver is used for inputting data, controlling the data on the input bit line and enabling the data on the input bit line and the weight stored in the storage array to be calculated; the row decoder is used for controlling the storage of the weight and the selection of the weight through the output word line WL; the read-write bit line driving module is used for realizing weight storage and reading through the output bit lines BL and BLB; the storage and calculation unit array module is used for storing and calculating according to the weight to obtain the output result; the voltage equalizing module is used for carrying out charge sharing on the output result; and the multiply-accumulate read-out control module is used for outputting a calculation result after charge sharing. The invention can reduce the number of transistors, realize the reduction of area and improve the calculation efficiency.
Description
Technical Field
The invention relates to the field of memory computing, in particular to a multi-bit memory computing device.
Background
Deep Convolutional Neural Networks (DCNNs) are rapidly developed in the fields of artificial intelligence and the like, and along with the gradual development of the DCNNs, more and more problems in the aspects of size, efficiency, energy consumption and the like need to be considered. In the conventional calculation process, the weights are moved between the memory and the arithmetic unit, which is not in accordance with the requirement of low power consumption. Memory Computing (IMC) is increasingly attractive for DCNN acceleration. The traditional 8T SRAM structure has more transistors, larger area and smaller input data bit width, which is not in line with the current requirement.
Therefore, there is a need for a memory computing device that changes the conventional computing operation, reduces the number of transistors, achieves a reduction in area, and improves computing efficiency.
Disclosure of Invention
The invention provides a multi-bit memory device which can reduce the number of transistors, realize the reduction of area and improve the calculation efficiency.
In order to achieve the purpose, the invention provides the following scheme:
a multi-bit memory device, comprising: the device comprises a storage unit array module, an input driver, a read-write bit line driving module, a row decoder, a voltage equalizing module and a multiply-accumulate read-out control module;
the storage unit array module is respectively connected with the input driver, the read-write bit line driving module, the row decoder and the voltage-sharing module; the voltage equalizing module is connected with the multiply-accumulate read-out control module;
the input driver is used for inputting data, controlling the data on the input bit line and enabling the data on the input bit line and the weight stored in the storage array to be calculated; the input bit line includes: RWLL-L, RWLL-H, RWLH-L and RWLH-H;
the row decoder is used for controlling the storage of the weight and the selection of the weight through the output word line WL;
the read-write bit line driving module is used for realizing weight storage and reading through the output bit lines BL and BLB;
the storage and calculation unit array module is used for storing and calculating according to the weight to obtain the output result;
the voltage equalizing module is used for carrying out charge sharing on the output result;
and the multiply-accumulate readout control module is used for outputting a calculation result after charge sharing.
Optionally, the storage unit array module includes: 16 × 4 multiply-accumulate units;
and the multiply-accumulate unit is used for storing and calculating according to the weight to obtain the output result.
Optionally, the multiply-accumulate unit comprises: a storage subunit and a calculation subunit;
the storage subunit is used for storing the weight;
the computing subunit is connected with the storage subunit; the calculating subunit is configured to calculate according to the weight.
Optionally, the storage subunit includes: tube M1, tube M2, tube M3, tube M4, inverter, and high;
the source of the transistor M1 and the source of the transistor M2 are both connected to a high level, the drain of the transistor M1 is connected to the drain of the transistor M3, the input of the inverter, and the gate of the transistor M2, the drain of the transistor M2 is connected to the drain of the transistor M4 and the gate of the transistor M1, the gate of the transistor M3 and the gate of the transistor M4 are both connected to a word line WL, the source of the transistor M4 is connected to a bit line BL, and the source of the transistor M3 is connected to a bit line BLB.
Optionally, the calculation subunit includes: tube M5, tube M6, tube M7, tube M8, tube M9, tube M10, tube M11, and tube M12;
the gates of the tube M5 and the tube M6 are both connected with the output end of the inverter, the drains of the tube M5 and the tube M6 are both grounded, the source of the tube M5 is connected with the source of the tube M7, the source of the tube M6 is connected with the source of the tube M8, the gate of the tube M7 is connected with RWL-L, the drain of the tube M7 is connected with ROBL, the gate of the tube M8 is connected with RWL-H, the drain of the tube M8 is connected with ROBH,
the gates of the tubes M9 and M10 are connected with the drain of the tube M2, the drains of the tubes M9 and M10 are grounded, the source of the tube M9 is connected with the source of the tube M11, the source of the tube M10 is connected with the source of the tube M12, the gate of the tube M11 is connected with RWLH-L, the drain of the tube M11 is connected with ROL, the gate of the tube M12 is connected with RWLH-H, and the drain of the tube M12 is connected with ROH.
Optionally, the pressure equalizing module includes: and each voltage-sharing subunit is positioned between one row of multiply-accumulate units and the multiply-accumulate reading control module.
Optionally, the voltage equalizing subunit includes a first voltage equalizing structure, a second voltage equalizing structure, a third voltage equalizing structure, a fourth voltage equalizing structure, a fifth voltage equalizing structure, a sixth voltage equalizing structure, a seventh voltage equalizing structure, and an eighth voltage equalizing structure;
first voltage-sharing structure and second voltage-sharing structure establish ties on ROBH, and third voltage-sharing structure establishes ties on ROBL with fourth voltage-sharing structure, and fifth voltage-sharing structure and sixth voltage-sharing structure establish ties on ROL, and seventh voltage-sharing structure and eighth voltage-sharing structure establish ties on ROH.
Optionally, the first pressure equalizing structure includes: a capacitor C0, a switch S0, and a switch S1; one end of the capacitor C0 is connected with the switch S0, the other end of the capacitor C0 is grounded, and the other end of the switch S0 is connected with ROBH; the switch S1 is respectively connected with the other end of the switch S0 and the second voltage-sharing structure; the second voltage equalizing structure includes: a capacitor C1, a switch S2, and a switch S3; one end of a capacitor C1 is connected with a switch S2, the other end of a capacitor C1 is grounded, the other end of the switch S2 is connected with the other end of the switch S1, and the S3 is respectively connected with the other end of a switch S2 and the multiply-accumulate read control module;
the third pressure equalizing structure includes: a capacitor C2, a switch S00, and a switch S10; one end of the capacitor C2 is connected with the switch S00, the other end of the capacitor C2 is grounded, and the other end of the switch S00 is connected with ROBL; the switch S10 is respectively connected with the other end of the switch S00 and the fourth voltage-sharing structure;
the fourth voltage equalizing structure includes: a capacitor C3, a switch S20, and a switch S30; one end of a capacitor C3 is connected with a switch S20, the other end of a capacitor C3 is grounded, the other end of the switch S20 is connected with the other end of the switch S10, and the S30 is respectively connected with the other end of a switch S20 and the multiply-accumulate read control module;
the fifth pressure equalizing structure includes: a capacitor C4, a switch S01, and a switch S11; one end of the capacitor C4 is connected with the switch S01, the other end of the capacitor C4 is grounded, and the other end of the switch S01 is connected with the ROL; the switch S11 is respectively connected with the other end of the switch S01 and the sixth voltage-sharing structure;
the sixth pressure equalizing structure includes: a capacitor C5, a switch S21, and a switch S31; one end of a capacitor C5 is connected with a switch S21, the other end of a capacitor C5 is grounded, the other end of the switch S21 is connected with the other end of the switch S11, and the S31 is respectively connected with the other end of a switch S21 and the multiply-accumulate read control module;
the seventh voltage equalizing structure includes: a capacitor C6, a switch S02, and a switch S12; one end of the capacitor C6 is connected with the switch S02, the other end of the capacitor C6 is grounded, and the other end of the switch S02 is connected with ROH; the switch S12 is respectively connected with the other end of the switch S02 and the eighth voltage-sharing structure;
the eighth voltage equalizing structure includes: a capacitor C7, a switch S22, and a switch S32; one end of the capacitor C7 is connected to the switch S22, the other end of the capacitor C7 is grounded, the other end of the switch S22 is connected to the switch S12, and the S32 is connected to the other end of the switch S22 and the multiply-accumulate read control module, respectively.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
according to the multi-bit storage device provided by the invention, multiplication and accumulation operations of multi-bit input data and weights are realized in the multiplication and accumulation read control module and the voltage equalizing module, compared with the traditional calculation, the bit width of the data is increased, and the application range is enlarged. Compared with the structure with the same calculation condition, the adopted storage and calculation unit array module structure reduces the number of transistors, realizes the reduction of area and improves efficiency. And, the use of the multi-bit input mode realizes the increase of the data bit width, and achieves the effect of expanding the use range.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a schematic diagram of a multi-bit memory device according to the present invention;
FIG. 2 is a schematic diagram of a storage unit array module;
fig. 3 is a schematic view of a voltage equalizing module.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a multi-bit memory device which can reduce the number of transistors, realize the reduction of area and improve the calculation efficiency.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Fig. 1 is a schematic structural diagram of a multi-bit computing device according to the present invention, as shown in fig. 1, the multi-bit computing device according to the present invention includes: the device comprises a storage unit array module, an input driver, a read-write bit line driving module, a row decoder, a voltage equalizing module and a multiply-accumulate read-out control module;
the storage unit array module is respectively connected with the input driver, the read-write bit line driving module, the row decoder and the voltage-sharing module; the voltage equalizing module is connected with the multiply-accumulate read-out control module;
the input driver is used for inputting data, controlling the data on the input bit line and enabling the data on the input bit line and the weight stored in the storage array to be calculated; the input bit line includes: RWLL-L, RWLL-H, RWLH-L and RWLH-H; the data generation means that data is input into the structure from the four lines and is used as input and weight to realize the operation of multiplication and addition.
The row decoder is used for controlling the storage of the weight and the selection of the weight through the output word line WL; the WL may control the weight storage, and the weight storage may be performed only when WL = 1. WL may control the output of the weight, which can only be output if WL = 1.
The read-write bit line driving module is used for realizing weight storage and reading through the output bit lines BL and BLB;
the storage and calculation unit array module is used for storing and calculating according to the weight to obtain the output result;
the voltage equalizing module is used for carrying out charge sharing on the output result;
and the multiply-accumulate readout control module is used for outputting a calculation result after charge sharing.
The storage cell array module includes: 16 × 4 multiply-accumulate units (MACB); each column consists of 16 rows.
And the multiply-accumulate unit is used for storing and calculating according to the weight to obtain the output result.
The multiply-accumulate unit includes: a storage subunit and a calculation subunit;
as a specific example, the memory subcells include 2 PMOS (M1-M2) and 2 NMOS (M3-M4). The calculating subunit comprises 8 NMOS (M5-M12)
The storage subunit is used for storing the weight;
the computing subunit is connected with the storage subunit; the calculating subunit is configured to calculate according to the weight.
The memory sub-unit includes: tube M1, tube M2, tube M3, tube M4, inverter, and high;
the source of the transistor M1 and the source of the transistor M2 are both connected to a high level, the drain of the transistor M1 is connected to the drain of the transistor M3, the input of the inverter, and the gate of the transistor M2, the drain of the transistor M2 is connected to the drain of the transistor M4 and the gate of the transistor M1, the gate of the transistor M3 and the gate of the transistor M4 are both connected to a word line WL, the source of the transistor M4 is connected to a bit line BL, and the source of the transistor M3 is connected to a bit line BLB.
That is, the memory sub-unit is a 4T memory unit, and the tubes M1-M4 in FIG. 2 are memory sub-units.
The calculation subunit includes: tube M5, tube M6, tube M7, tube M8, tube M9, tube M10, tube M11, and tube M12;
the gates of the tube M5 and the tube M6 are both connected with the output end of the inverter, the drains of the tube M5 and the tube M6 are both grounded, the source of the tube M5 is connected with the source of the tube M7, the source of the tube M6 is connected with the source of the tube M8, the gate of the tube M7 is connected with RWL-L, the drain of the tube M7 is connected with ROBL, the gate of the tube M8 is connected with RWL-H, the drain of the tube M8 is connected with ROBH,
the gates of the tubes M9 and M10 are connected with the drain of the tube M2, the drains of the tubes M9 and M10 are grounded, the source of the tube M9 is connected with the source of the tube M11, the source of the tube M10 is connected with the source of the tube M12, the gate of the tube M11 is connected with RWLH-L, the drain of the tube M11 is connected with ROL, the gate of the tube M12 is connected with RWLH-H, and the drain of the tube M12 is connected with ROH.
WL, BL, BLB, RWLL-L, RWLL-H, RWLH-L, RWLH-H, ROH, ROL, ROBH, ROBL are all shared as a shared part, where BL, BLB, ROH, ROL, ROBH, ROBL are shared as a column, and WL, RWLL-L, RWLL-H, RWLH-L, RWLH-H are shared as a row.
That is, as can be seen from fig. 2, the transistors M5-M8 and M9-M12 have a symmetrical structure, and actually M5 and M7 are repeated four times, but the gates of M5 and M6 are connected to Q' through an inverter, and the gates of M9 and M10 are directly connected to Q.
RWL-L, RWL-H, RWL-L, RWL-H respectively represent I [0], I [1], I [2], I [3] of a 4-bit input I [0:3], when the weight is 1, i.e. Q =1, Q' =0, M5, M6, M9, M10 are all turned on, ROH, ROL, ROBH, ROBL respectively represent the calculation results of I [3 ]. about.1, I [2 ]. about.1, I [1 ]. about.1, I [0 ]. about.1 (RWL-L is connected to the gate of M7 as the input of the calculation result ROBL, RWL-H is connected to the gate of M8 as the input of the calculation result ROBH, RWL-L is connected to the gate of M11 as the input of the calculation result ROLH, RWL-H is connected to the gates of M12 as the input of the calculation result ROH, RWL 3, ROBL respectively, i1 x 1, I0 x 1, which causes the lower C0-C7 capacitor to generate voltage, and the voltage is output through voltage equalization) (the calculation result refers to the result of multiplying the multiplier and multiplicand, which is expressed in the form of current on ROH, ROL, ROBH, ROBL, and which causes the lower C0-C7 capacitor to generate voltage); when the weight is 0, i.e. Q =0, Q' =1, the tubes M5, M6, M9, M10 are all closed, and ROH, ROL, ROBH, ROBL represent the calculation results of I [3] × 0, I [2] × 0, I [1] × 0, I [0] × 0, respectively.
As shown in fig. 3, the voltage equalizing module includes: and each voltage-sharing subunit is positioned between one row of multiply-accumulate units and the multiply-accumulate reading control module.
The voltage-sharing subunit comprises a first voltage-sharing structure, a second voltage-sharing structure, a third voltage-sharing structure, a fourth voltage-sharing structure, a fifth voltage-sharing structure, a sixth voltage-sharing structure, a seventh voltage-sharing structure and an eighth voltage-sharing structure;
first voltage-sharing structure and second voltage-sharing structure establish ties on ROBH, and third voltage-sharing structure establishes ties on ROBL with fourth voltage-sharing structure, and fifth voltage-sharing structure and sixth voltage-sharing structure establish ties on ROL, and seventh voltage-sharing structure and eighth voltage-sharing structure establish ties on ROH.
The first pressure equalizing structure includes: a capacitor C0, a switch S0, and a switch S1; one end of the capacitor C0 is connected with the switch S0, the other end of the capacitor C0 is grounded, and the other end of the switch S0 is connected with ROBH; the switch S1 is respectively connected with the other end of the switch S0 and the second voltage-sharing structure; the second voltage equalizing structure includes: a capacitor C1, a switch S2, and a switch S3; one end of a capacitor C1 is connected with a switch S2, the other end of a capacitor C1 is grounded, the other end of the switch S2 is connected with the other end of the switch S1, and the S3 is respectively connected with the other end of a switch S2 and the multiply-accumulate read control module;
the third pressure equalizing structure includes: a capacitor C2, a switch S00, and a switch S10; one end of the capacitor C2 is connected with the switch S00, the other end of the capacitor C2 is grounded, and the other end of the switch S00 is connected with ROBL; the switch S10 is respectively connected with the other end of the switch S00 and the fourth voltage-sharing structure;
the fourth voltage equalizing structure includes: a capacitor C3, a switch S20, and a switch S30; one end of a capacitor C3 is connected with a switch S20, the other end of a capacitor C3 is grounded, the other end of the switch S20 is connected with the other end of the switch S10, and the S30 is respectively connected with the other end of a switch S20 and the multiply-accumulate read control module;
the fifth pressure equalizing structure includes: a capacitor C4, a switch S01, and a switch S11; one end of the capacitor C4 is connected with the switch S01, the other end of the capacitor C4 is grounded, and the other end of the switch S01 is connected with the ROL; the switch S11 is respectively connected with the other end of the switch S01 and the sixth voltage-sharing structure;
the sixth pressure equalizing structure includes: a capacitor C5, a switch S21, and a switch S31; one end of a capacitor C5 is connected with a switch S21, the other end of a capacitor C5 is grounded, the other end of the switch S21 is connected with the other end of the switch S11, and the S31 is respectively connected with the other end of a switch S21 and the multiply-accumulate read control module;
the seventh voltage equalizing structure includes: a capacitor C6, a switch S02, and a switch S12; one end of the capacitor C6 is connected with the switch S02, the other end of the capacitor C6 is grounded, and the other end of the switch S02 is connected with ROH; the switch S12 is respectively connected with the other end of the switch S02 and the eighth voltage-sharing structure;
the eighth voltage equalizing structure includes: a capacitor C7, a switch S22, and a switch S32; one end of the capacitor C7 is connected to the switch S22, the other end of the capacitor C7 is grounded, the other end of the switch S22 is connected to the switch S12, and the S32 is connected to the other end of the switch S22 and the multiply-accumulate read control module, respectively.
The voltage-sharing module has the main function of enabling a calculation result to meet the carry relation from a high bit to a low bit of data. The switch is mainly used for controlling the opening and closing of the circuit; C0-C7 are capacitors, and the size relationship of the capacitors satisfies a certain relationship, and assuming that the size of the capacitor of C1 is m, C3=2m, C5=4m, C7=8m, C0=8m, C2=7m, C4=5m, and C6= m. By means of charge sharing, the outputs have multiple relations (C1 =1m, C3=2m, C5=4m, C7=8m, the size satisfies the relation of 1:2:4:8, the calculation results are added according to the bit number relation of 4 bits), and the carry relation of the two-level system number of 4 bits is satisfied. The output voltage subjected to charge sharing is input to the multiply-accumulate read control module, analog-to-digital conversion is realized, and the output voltage is output (input to the multiply-accumulate read control module as shown in fig. 1).
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (8)
1. A multi-bit storage apparatus, comprising: the device comprises a storage unit array module, an input driver, a read-write bit line driving module, a row decoder, a voltage equalizing module and a multiply-accumulate read-out control module;
the storage unit array module is respectively connected with the input driver, the read-write bit line driving module, the row decoder and the voltage-sharing module; the voltage equalizing module is connected with the multiply-accumulate read-out control module;
the input driver is used for inputting data, controlling the data on the input bit line and enabling the data on the input bit line and the weight stored in the storage array to be calculated; the input bit line includes: RWLL-L, RWLL-H, RWLH-L and RWLH-H;
the row decoder is used for controlling the storage of the weight and the selection of the weight through the output word line WL;
the read-write bit line driving module is used for realizing weight storage and reading through the output bit lines BL and BLB;
the storage and calculation unit array module is used for storing and calculating according to the weight to obtain the output result;
the voltage equalizing module is used for carrying out charge sharing on the output result;
and the multiply-accumulate readout control module is used for outputting a calculation result after charge sharing.
2. A multi-bit memory device according to claim 1, wherein said memory cell array module comprises: 16 × 4 multiply-accumulate units;
and the multiply-accumulate unit is used for storing and calculating according to the weight to obtain the output result.
3. A multi-bit storage apparatus according to claim 2, wherein said multiply-accumulate unit comprises: a storage subunit and a calculation subunit;
the storage subunit is used for storing the weight;
the computing subunit is connected with the storage subunit; the calculating subunit is configured to calculate according to the weight.
4. A multi-bit memory device according to claim 3, wherein said memory sub-unit comprises: tube M1, tube M2, tube M3, tube M4, inverter, and high;
the source of the transistor M1 and the source of the transistor M2 are both connected to a high level, the drain of the transistor M1 is connected to the drain of the transistor M3, the input of the inverter, and the gate of the transistor M2, the drain of the transistor M2 is connected to the drain of the transistor M4 and the gate of the transistor M1, the gate of the transistor M3 and the gate of the transistor M4 are both connected to a word line WL, the source of the transistor M4 is connected to a bit line BL, and the source of the transistor M3 is connected to a bit line BLB.
5. A multi-bit storage arrangement according to claim 4, wherein said computing sub-unit comprises: tube M5, tube M6, tube M7, tube M8, tube M9, tube M10, tube M11, and tube M12;
the gates of the tube M5 and the tube M6 are both connected with the output end of the inverter, the drains of the tube M5 and the tube M6 are both grounded, the source of the tube M5 is connected with the source of the tube M7, the source of the tube M6 is connected with the source of the tube M8, the gate of the tube M7 is connected with RWL-L, the drain of the tube M7 is connected with ROBL, the gate of the tube M8 is connected with RWL-H, the drain of the tube M8 is connected with ROBH,
the gates of the tubes M9 and M10 are connected with the drain of the tube M2, the drains of the tubes M9 and M10 are grounded, the source of the tube M9 is connected with the source of the tube M11, the source of the tube M10 is connected with the source of the tube M12, the gate of the tube M11 is connected with RWLH-L, the drain of the tube M11 is connected with ROL, the gate of the tube M12 is connected with RWLH-H, and the drain of the tube M12 is connected with ROH.
6. A multi-bit storage apparatus according to claim 2, wherein said voltage equalizing module comprises: and each voltage-sharing subunit is positioned between one row of multiply-accumulate units and the multiply-accumulate reading control module.
7. The multiposition storage device according to claim 6, wherein the pressure equalizing sub-unit comprises a first pressure equalizing structure, a second pressure equalizing structure, a third pressure equalizing structure, a fourth pressure equalizing structure, a fifth pressure equalizing structure, a sixth pressure equalizing structure, a seventh pressure equalizing structure, and an eighth pressure equalizing structure;
first voltage-sharing structure and second voltage-sharing structure establish ties on ROBH, and third voltage-sharing structure establishes ties on ROBL with fourth voltage-sharing structure, and fifth voltage-sharing structure and sixth voltage-sharing structure establish ties on ROL, and seventh voltage-sharing structure and eighth voltage-sharing structure establish ties on ROH.
8. A multi-bit storage apparatus according to claim 7, wherein said first voltage equalizing structure comprises: a capacitor C0, a switch S0, and a switch S1; one end of the capacitor C0 is connected with the switch S0, the other end of the capacitor C0 is grounded, and the other end of the switch S0 is connected with ROBH; the switch S1 is respectively connected with the other end of the switch S0 and the second voltage-sharing structure; the second voltage equalizing structure includes: a capacitor C1, a switch S2, and a switch S3; one end of a capacitor C1 is connected with a switch S2, the other end of a capacitor C1 is grounded, the other end of the switch S2 is connected with the other end of the switch S1, and the S3 is respectively connected with the other end of a switch S2 and the multiply-accumulate read control module;
the third pressure equalizing structure includes: a capacitor C2, a switch S00, and a switch S10; one end of the capacitor C2 is connected with the switch S00, the other end of the capacitor C2 is grounded, and the other end of the switch S00 is connected with ROBL; the switch S10 is respectively connected with the other end of the switch S00 and the fourth voltage-sharing structure;
the fourth voltage equalizing structure includes: a capacitor C3, a switch S20, and a switch S30; one end of a capacitor C3 is connected with a switch S20, the other end of a capacitor C3 is grounded, the other end of the switch S20 is connected with the other end of the switch S10, and the S30 is respectively connected with the other end of a switch S20 and the multiply-accumulate read control module;
the fifth pressure equalizing structure includes: a capacitor C4, a switch S01, and a switch S11; one end of the capacitor C4 is connected with the switch S01, the other end of the capacitor C4 is grounded, and the other end of the switch S01 is connected with the ROL; the switch S11 is respectively connected with the other end of the switch S01 and the sixth voltage-sharing structure;
the sixth pressure equalizing structure includes: a capacitor C5, a switch S21, and a switch S31; one end of a capacitor C5 is connected with a switch S21, the other end of a capacitor C5 is grounded, the other end of the switch S21 is connected with the other end of the switch S11, and the S31 is respectively connected with the other end of a switch S21 and the multiply-accumulate read control module;
the seventh voltage equalizing structure includes: a capacitor C6, a switch S02, and a switch S12; one end of the capacitor C6 is connected with the switch S02, the other end of the capacitor C6 is grounded, and the other end of the switch S02 is connected with ROH; the switch S12 is respectively connected with the other end of the switch S02 and the eighth voltage-sharing structure;
the eighth voltage equalizing structure includes: a capacitor C7, a switch S22, and a switch S32; one end of the capacitor C7 is connected to the switch S22, the other end of the capacitor C7 is grounded, the other end of the switch S22 is connected to the switch S12, and the S32 is connected to the other end of the switch S22 and the multiply-accumulate read control module, respectively.
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