CN113703718B - Multi-bit memory computing device with variable weight - Google Patents
Multi-bit memory computing device with variable weight Download PDFInfo
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- CN113703718B CN113703718B CN202111194830.9A CN202111194830A CN113703718B CN 113703718 B CN113703718 B CN 113703718B CN 202111194830 A CN202111194830 A CN 202111194830A CN 113703718 B CN113703718 B CN 113703718B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
- G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
Abstract
The invention discloses a multi-bit memory computing device with variable weight, which utilizes a row driving module to input a word line signal WL to each memory module; 8N bit line signals BL and 8N bit bar line signals BLB are input to each storage module by using the column driving module; generating a plurality of pulse waves by using a multi-input selection module according to input data, and sending the plurality of pulse waves and a switch control instruction to each voltage-sharing module; each storage module carries out storage weight and calculation weight according to the word line signal WL, the bit line signal BL and the bit bar line signal BLB; each voltage-sharing module utilizes charge sharing to carry out voltage sharing according to input data and a switch control instruction and output a multi-bit weight; and performing analog-to-digital conversion on the output multi-bit weight by using an accumulation module and then accumulating. The invention realizes multiplication calculation by means of voltage control of bit lines, realizes voltage sharing by means of charge sharing, realizes multi-bit memory calculation with variable weight, and is suitable for calculation with different requirements.
Description
Technical Field
The present invention relates to the field of memory computing technologies, and in particular, to a multi-bit memory computing device with variable weights.
Background
Deep Convolutional Neural Networks (DCNNs) are rapidly developed in the fields of artificial intelligence and the like, and along with the gradual development of the DCNNs, more and more problems in the aspects of size, efficiency, energy consumption and the like need to be considered. In conventional calculation processes, weights are moved between the memory and the arithmetic unit, which is not in accordance with the requirement of low power consumption. In-memory computing (IMC) is increasingly attractive for DCNN acceleration. The traditional memory computing chip mostly adopts voltage or level to calculate, and has the defects of more single bit calculation and larger area.
Disclosure of Invention
The invention aims to provide a multi-bit memory computing device with variable weight, so as to realize multi-bit memory computing with variable weight.
To achieve the above object, the present invention provides a variable weight multi-bit memory computing apparatus, comprising:
the device comprises a row driving module, a column driving module, a multi-input selection module, an accumulation module, N accumulation modules and N voltage-sharing modules, wherein N is a positive integer greater than or equal to 1; the row driving module and the column driving module are connected with the storage modules, the storage modules and the voltage-sharing modules are arranged and connected in a one-to-one correspondence mode, the multi-input selection module is sequentially connected with N voltage-sharing modules, and the N voltage-sharing modules are connected with the accumulation module;
the row driving module is used for inputting word line signals WL to each storage module;
the column driving module is used for inputting 8N bit line signals BL and 8N bit line inversion signals BLB to each storage module;
the multi-input selection module is used for generating a plurality of pulse waves according to input data and sending the pulse waves and the switch control instructions to the voltage-sharing modules;
each storage module carries out storage weight and calculation weight according to the word line signal WL, the bit line signal BL and the bit bar line signal BLB; the storage module comprises 8 6T-SRAM memory cells arranged in an array;
each voltage-sharing module is used for sharing voltage and outputting multi-bit weight according to the input data and the switch control instruction by using charge;
and the accumulation module is used for accumulating the output multi-bit weight after analog-to-digital conversion to obtain a final result.
Optionally, each 6T-SRAM memory cell includes:
transistor T1Transistor T2Transistor T3Transistor T4Transistor T5And a transistor T6；
Transistor T1And a transistor T2Are all connected with a power supply VDD, and a transistor T1Gate of (2), transistor T3Gate of (2), transistor T2And a transistor T4Are all connected with the point Q, and a transistor T2Gate of (2), transistor T4Gate of (2), transistor T1And a transistor T3Are all connected with QB point, transistor T3And a transistor T4Are all connected with a common terminal VSS, a transistor T5Gate of (2) and transistor T6The grid electrodes of the transistors T are all connected with the row driving module5Is connected to point QB, transistor T5Is connected to the column driver module, a transistor T6Is connected to point Q, transistor T6Is connected to the column driver module.
Optionally, the voltage equalizing module comprises 8 voltage equalizing units; the ith voltage equalizing unit is connected with the ith 6T-SRAM storage unit, wherein i is a positive integer which is greater than or equal to 1 and less than or equal to 8.
Optionally, the ith pressure equalizing unit includes: switch tube Mi-1Capacitor C2i-2Capacitor C2i-1Switch tube S0Switch tube S1Switch tube S2And a switching tube S3(ii) a Switch tube Mi-1Is connected with the column driving module for inputting a bit line signal BL [ i-1 ]](ii) a Switch tube Mi-1The other end of the first and second switch tubes are respectively connected with a switch tube S0And a switching tube S1Is connected with one end of a switching tube S0Another terminal of (1) and a capacitor C2i-2Is connected to a capacitor C2i-2The other end of the switch tube S is grounded1The other end of the first and second switch tubes are respectively connected with a switch tube S2And a switching tube S3Is connected with one end of a switching tube S2Another terminal of (1) and a capacitor C2i-1Is connected to a capacitor C2i-1The other end of the switch tube S is grounded3The other end of the second connecting line is connected with the accumulation module; switch tube Mi-1Switch tube S0Switch tubeS1Switch tube S2And a switching tube S3Are all connected with the multi-input selection module.
Optionally, a capacitor C0: capacitor C1: capacitor C2: capacitor C3: capacitor C4: capacitor C5: capacitor C6: capacitor C7: capacitor C8: capacitor C9: capacitor C10: capacitor C11: capacitor C12: capacitor C13: capacitor C14: capacitor C15=128:1:127:2:125:4:121:8:113:16:97:32:65:64:1:128。
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
1. the invention adopts 8 6T-SRAM memory cells to construct the memory computation module, further constructs the memory computation device, has the advantages of high maturity and good stability, and reduces the area compared with the traditional memory computation device.
2. The invention uses a plurality of 6T-SRAM memory units to store the weight, realizes multiplication calculation by means of voltage control of bit lines, realizes voltage sharing by charge sharing, realizes multi-bit memory calculation with variable weight, and is suitable for calculation with different requirements.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a block diagram of a variable weight multi-bit memory computing device according to the present invention;
FIG. 2 is a block diagram of a memory module according to the present invention;
FIG. 3 is a view of the construction of the pressure equalizing module of the present invention;
description of the symbols:
1. the device comprises a row driving module, a column driving.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a multi-bit memory computing device with variable weight, so as to realize multi-bit memory computing with variable weight.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Example 1
The invention discloses a variable weight multi-bit memory computing device, comprising: the device comprises a row driving module, a column driving module, a multi-input selection module, an accumulation module, N accumulation modules and N voltage-sharing modules, wherein N is a positive integer greater than or equal to 1; the row driving module and the column driving module are connected with the storage modules, the storage modules and the voltage-sharing modules are arranged and connected in a one-to-one correspondence mode, the multi-input selection module is sequentially connected with N voltage-sharing modules, and the N voltage-sharing modules are connected with the accumulation module; the row driving module is used for inputting word line signals WL to each storage module; the column driving module is used for inputting 8N bit line signals BL and 8N bit line inversion signals BLB to each storage module; the multi-input selection module is used for generating a plurality of pulse waves according to input data and sending the pulse waves and the switch control instructions to the voltage-sharing modules; each storage module carries out storage weight and calculation weight according to the word line signal WL, the bit line signal BL and the bit bar line signal BLB; each voltage-sharing module is used for sharing voltage and outputting multi-bit weight according to the input data and the switch control instruction by using charge; and the accumulation module is used for accumulating the output multi-bit weight after analog-to-digital conversion to obtain a final result. The memory module comprises 8 array-arranged 6T-SRAM memory cells.
As an optional embodiment, the voltage equalizing module of the present invention includes 8 voltage equalizing units; the ith voltage equalizing unit is connected with the ith 6T-SRAM storage unit, wherein i is a positive integer which is greater than or equal to 1 and less than or equal to 8. The ith voltage equalizing unit comprises: switch tube Mi-1Capacitor C2i-2Capacitor C2i-1Switch tube S0Switch tube S1Switch tube S2And a switching tube S3(ii) a Switch tube Mi-1Is connected with the ith 6T-SRAM memory cell for inputting a bit line signal BL [ i-1 [ ]](ii) a Switch tube Mi-1The other end of the first and second switch tubes are respectively connected with a switch tube S0And a switching tube S1Is connected with one end of a switching tube S0Another terminal of (1) and a capacitor C2i-2Is connected to a capacitor C2i-2The other end of the switch tube S is grounded1The other end of the first and second switch tubes are respectively connected with a switch tube S2And a switching tube S3Is connected with one end of a switching tube S2Another terminal of (1) and a capacitor C2i-1Is connected to a capacitor C2i-1The other end of the switch tube S is grounded3The other end of the second connecting line is connected with the accumulation module; switch tube Mi-1Switch tube S0Switch tube S1Switch tube S2And a switching tube S3Are all connected with the multi-input selection module.
Example 2
As shown in fig. 1, the present invention takes N equal to 4 as an example, circles in fig. 1 indicate ellipses, and only a first storage module 4, a fourth storage module 4, a first voltage equalizing module 5 connected to the first storage module 4, and a fourth voltage equalizing module 5 connected to the fourth storage module 4 are shown. The row driving module 1 is used for sending a bit line signal WL to 4 storage modules 4, the column driving module 2 is used for outputting a bit line signal BL [0] -BL [31] and a bit bar line signal BLB [0] -BLB [31], inputting the bit line signal BL [0] -BL [7] and the bit bar line signal BLB [0] -BLB [7] into a first storage module 4, and inputting the bit line signal BL [24] -BL [31] and the bit bar line signal BLB [24] -BLB [31] into a fourth storage module 4 in the same way. The multi-input selection module 3 generates a plurality of pulse waves according to input data and sends the pulse waves and switch control instructions to the 4 voltage-sharing modules 5; the 1 st storage module 4 stores and calculates the weight according to the word line signal WL, the bit line signals BL [0] -BL [7] and the bit bar line signals BLB [0] -BLB [7 ]; by analogy, the 4 th storage module 4 stores and calculates weights according to the word line signal WL, the bit line signals BL [24] -BL [31] and the bit bar line signals BLB [24] -BLB [31 ]; the 4 voltage equalizing modules 5 equalize voltage and output multi-bit weights according to the input data and the switch control instructions; and the accumulation module 6 is used for accumulating the output multi-bit weights OUT [1] -OUT [3] after analog-to-digital conversion to obtain a final result.
When the input data is 1 data with 4 bits, pulse waves with different pulse numbers are generated in the multi-input selection module 3, and different inputs are distinguished through the number of the pulse waves. For example, when the input data is 0, the number of generated pulse waves is 0, when the input data is 1, 1 pulse wave is generated, and when the input data is 15, 15 pulse waves are generated. The number of pulse waves corresponds to a plurality of discharges with equal duration.
As shown in FIG. 2, the circles in FIG. 2 indicate ellipses, and the memory module 4 includes 8 6T-SRAM memory cells arranged in an array. The structures of a plurality of 6T-SRAM memory cells are the same, and the 1 st 6T-SRAM memory cell is taken as an example for discussion:
the 1 st 6T-SRAM memory cell comprises: transistor T1Transistor T2Transistor T3Transistor T4Transistor T5And a transistor T6(ii) a Transistor T1And a transistor T2Are all connected with a power supply VDD, and a transistor T1Gate of (2), transistor T3Gate of (2), transistor T2And a transistor T4Are all connected with the point Q, and a transistor T2Gate of (2), transistor T4Gate of (2), transistor T1And a transistor T3Are all connected with QB point, and a transistorT3And a transistor T4Are all connected with a common terminal VSS, a transistor T5Gate of (2) and transistor T6The grid electrodes of the transistors T are all connected with the row driving module5Is connected to point QB, transistor T5Is connected to the column driver module, a transistor T6Is connected to point Q, transistor T6Is connected to the column driver module. Transistor T5Source input bit line signal BL [0]]Transistor T6Drain of the transistor is inputted with a bit line bar signal BL [0]]. And so on, the transistor T in the 8 th 6T-SRAM memory cell5Source input bit line signal BL [7]]Transistor T6Drain of the transistor is inputted with a bit line bar signal BL [7]]。
Switching tube T in fig. 21-T6For storing the weight, taking the 1 st 6T-SRAM memory cell as an example for analysis: the method mainly comprises a weight storage stage and a weight calculation stage; when storing the weight, let WL =1, when BL [0]]=0，BLB[0]When =1, weight 0 is written; when BL [0]]=1，BLB[0]If =0, the weight 1 is written. When the weight calculation is performed, when WL =1, BL [0]]=1, if the weight stored at this time is 0, then the current follows BL [ 0%]Through T5，T3Flow to GSS, when BL [0]]The voltage of (2) is decreased to 0, and the result of the calculation is 0; if the weight stored at this time is 1, there is no voltage difference, BL [0]]The voltage remains unchanged, and the result of the calculation is 1; BL [0] when WL =0]=0, when the transistor T is in operation5Off, BL [0] whether weight is 0 or 1]The voltage is kept low, and the calculation result is 0 at this time. These calculation results are inputted to the voltage equalizing block 5 to be calculated next.
As shown in fig. 3, the voltage equalizing module 5 comprises 8 voltage equalizing units; the ith voltage equalizing unit is connected with the ith 6T-SRAM storage unit, wherein i is a positive integer which is greater than or equal to 1 and less than or equal to 8. The 1 st voltage equalizing unit includes: switch tube M0Capacitor C0Capacitor C1Switch tube S0Switch tube S1Switch tube S2And a switching tube S3(ii) a The 2 nd voltage-sharing unit includes: switch tube M1Capacitor C2Electricity, electricityContainer C3Switch tube S0Switch tube S1Switch tube S2And a switching tube S3(ii) a By analogy, the 8 th voltage equalizing unit comprises: switch tube M7Capacitor C14Capacitor C15Switch tube S0Switch tube S1Switch tube S2And a switching tube S3。
Switching tube M in FIG. 30-M7For controlling the number of bits calculated. The method mainly comprises a weight storage stage and a weight calculation stage; when weight storage is carried out, no data is input at the moment, so the switch tube M in the voltage equalizing module 50-M7All in the off state. When weight calculation is carried out, if input data is 8-bit data, a plurality of pulse waves can be generated, and the switch tube M in the voltage-sharing module 50-M7All are opened, if the data is 7 bits, the switch tube M is controlled7Closed, switch tube M0-M6Closing, if the data is 6bit, controlling the switch tube M6And M7Closed, switch tube M0-M5Closing, and so on, if the data is 1bit, controlling the switch tube M1-M7Closed, switch tube M0And (5) closing.
Switch tube S in each voltage-sharing unit0-S3Voltage sharing is carried out according to a switch control instruction generated by the multi-input selection module 3, and multi-bit weight is output; the switch control instruction specifically comprises: first control switch tube S3Opening and closing switch tube S0-S2Voltage sharing of two adjacent capacitors is realized; then controlling the switch tube S1Opening and closing switch tube S0、S2And S3And realizing multi-bit weight output.
By means of charge sharing, the output satisfies 1: 2: 4: 8: 16: 32: 64: 128, since this is determined by the characteristics of the binary numbers, the first digit of the binary numbers representing a decimal 1, the second digit representing a decimal 2, the third digit representing a decimal 4, and so on, the output voltage subjected to charge sharing being input to the accumulatorAnd the adding module is used for realizing accumulation output after analog-to-digital conversion. Thus 16 capacitors C in each voltage-sharing module 50-C15Satisfy the relationship in table 1, see table 1 for details:
TABLE 1 capacitance proportional relationship
| C0=128 | C2=127 | C4=125 | C6=121 | C8=113 | C10=97 | C12=65 | C14=1 |
| C1=1 | C3=2 | C5=4 | C7=8 | C9=16 | C11=32 | C13=64 | C15=128 |
In summary, the scheme disclosed by the invention has the following advantages:
1. the invention adopts a plurality of 6T-SRAM memory cells to construct the memory computation module, further constructs the memory computation device, has the advantages of high maturity and good stability, and reduces the area compared with the traditional memory computation device.
2. The invention uses a plurality of 6T-SRAM memory units to store the weight, realizes multiplication calculation by means of voltage control of bit lines, realizes voltage sharing by charge sharing, realizes multi-bit memory calculation with variable weight, and is suitable for calculation with different requirements. When 4 bits of data are input, the weights are optional 1-8 bit weights.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to assist in understanding the core concepts of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (5)
1. An apparatus for variable weight multi-bit memory computation, the apparatus comprising:
the device comprises a row driving module, a column driving module, a multi-input selection module, an accumulation module, N accumulation modules and N voltage-sharing modules, wherein N is a positive integer greater than or equal to 1; the row driving module and the column driving module are connected with the storage modules, the storage modules and the voltage-sharing modules are arranged and connected in a one-to-one correspondence mode, the multi-input selection module is sequentially connected with N voltage-sharing modules, and the N voltage-sharing modules are connected with the accumulation module;
the row driving module is used for inputting word line signals WL to each storage module;
the column driving module is used for inputting 8N bit line signals BL and 8N bit line inversion signals BLB to each storage module;
the multi-input selection module is used for generating a plurality of pulse waves according to input data and sending the pulse waves and the switch control instructions to the voltage-sharing modules;
each storage module carries out storage weight and calculation weight according to the word line signal WL, the bit line signal BL and the bit bar line signal BLB; the storage module comprises 8 6T-SRAM memory cells arranged in an array;
each voltage-sharing module is used for sharing voltage and outputting multi-bit weight according to the input data and the switch control instruction by using charge;
and the accumulation module is used for accumulating the output multi-bit weight after analog-to-digital conversion to obtain a final result.
2. The variable weight multi-bit memory computing device of claim 1, wherein each of the 6T-SRAM memory cells comprises:
transistor T1Transistor T2Transistor T3Transistor T4Transistor T5And a transistor T6；
Transistor T1And a transistor T2Are all connected with a power supply VDD, and a transistor T1Gate of (2), transistor T3Gate of (2), transistor T2And a transistor T4Is connected to the drain of the transistor T, the connection point being referred to as point Q2Gate of (2), transistor T4Gate of (2), transistor T1And a transistor T3Is connected, the connection point being called point QB, transistor T3And a transistor T4Are all connected with a common terminal VSS, a transistor T5Gate of (2) and transistor T6The grid electrodes of the transistors T are all connected with the row driving module5Is connected to point QB, transistor T5Is connected to the column driver module, a transistor T6OfElectrode connected to point Q, transistor T6Is connected to the column driver module.
3. The variable weight multi-bit memory computing device of claim 2, wherein the voltage-sharing module comprises 8 voltage-sharing units; the ith voltage equalizing unit is connected with the ith 6T-SRAM storage unit, wherein i is a positive integer which is greater than or equal to 1 and less than or equal to 8.
4. The apparatus according to claim 3, wherein the ith voltage-sharing unit comprises: switch tube Mi-1Capacitor C2i-2Capacitor C2i-1Switch tube S0Switch tube S1Switch tube S2And a switching tube S3(ii) a Switch tube Mi-1Is connected with the ith 6T-SRAM memory cell for inputting a bit line signal BL [ i-1 [ ]](ii) a Switch tube Mi-1The other end of the first and second switch tubes are respectively connected with a switch tube S0And a switching tube S1Is connected with one end of a switching tube S0Another terminal of (1) and a capacitor C2i-2Is connected to a capacitor C2i-2The other end of the switch tube S is grounded1The other end of the first and second switch tubes are respectively connected with a switch tube S2And a switching tube S3Is connected with one end of a switching tube S2Another terminal of (1) and a capacitor C2i-1Is connected to a capacitor C2i-1The other end of the switch tube S is grounded3The other end of the second connecting line is connected with the accumulation module; switch tube Mi-1Switch tube S0Switch tube S1Switch tube S2And a switching tube S3Are all connected with the multi-input selection module.
5. The apparatus of claim 4, wherein the capacitance C is a capacitance of one of a plurality of capacitors0: capacitor C1: capacitor C2: capacitor C3: capacitor C4: capacitor C5: capacitor C6: capacitor C7: capacitor C8: capacitor C9: capacitor C10: capacitor C11: capacitor C12: capacitor C13: capacitor C14: capacitor C15=128:1:127:2:125:4:121:8:113:16:97:32:65:64:1:128。
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6049535A (en) * | 1996-06-27 | 2000-04-11 | Interdigital Technology Corporation | Code division multiple access (CDMA) communication system |
| CN112154506A (en) * | 2018-05-22 | 2020-12-29 | 密歇根大学董事会 | Memory processing unit |
| CN112567350A (en) * | 2018-06-18 | 2021-03-26 | 普林斯顿大学 | Configurable in-memory compute engine, platform, bitcell, and layout thereof |
| CN112580774A (en) * | 2020-09-01 | 2021-03-30 | 浙江大学 | Neural network layout method for reconfigurable neural network processor |
| CN112580793A (en) * | 2020-12-24 | 2021-03-30 | 清华大学 | Neural network accelerator based on time domain memory computing and acceleration method |
| CN113296734A (en) * | 2021-07-28 | 2021-08-24 | 中科南京智能技术研究院 | Multi-position storage device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10776690B2 (en) * | 2015-10-08 | 2020-09-15 | Via Alliance Semiconductor Co., Ltd. | Neural network unit with plurality of selectable output functions |
-
2021
- 2021-10-14 CN CN202111194830.9A patent/CN113703718B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6049535A (en) * | 1996-06-27 | 2000-04-11 | Interdigital Technology Corporation | Code division multiple access (CDMA) communication system |
| CN112154506A (en) * | 2018-05-22 | 2020-12-29 | 密歇根大学董事会 | Memory processing unit |
| CN112567350A (en) * | 2018-06-18 | 2021-03-26 | 普林斯顿大学 | Configurable in-memory compute engine, platform, bitcell, and layout thereof |
| CN112580774A (en) * | 2020-09-01 | 2021-03-30 | 浙江大学 | Neural network layout method for reconfigurable neural network processor |
| CN112580793A (en) * | 2020-12-24 | 2021-03-30 | 清华大学 | Neural network accelerator based on time domain memory computing and acceleration method |
| CN113296734A (en) * | 2021-07-28 | 2021-08-24 | 中科南京智能技术研究院 | Multi-position storage device |
Non-Patent Citations (2)
| Title |
|---|
| 基于忆阻器的PIM结构实现深度卷积神经网络近似计算;李楚曦，樊晓桠等;《计算机研究与发展》;20171231;第54卷(第6期);全文 * |
| 应用可变增益放大器的存内计算电路研究与设计;刘晨曦;《中国优秀硕士学位论文全文数据库（电子期刊）》;20200701;全文 * |
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