CN113281968B - Test method - Google Patents
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- CN113281968B CN113281968B CN202110535466.1A CN202110535466A CN113281968B CN 113281968 B CN113281968 B CN 113281968B CN 202110535466 A CN202110535466 A CN 202110535466A CN 113281968 B CN113281968 B CN 113281968B
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70691—Handling of masks or workpieces
- G03F7/70775—Position control, e.g. interferometers or encoders for determining the stage position
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/708—Construction of apparatus, e.g. environment aspects, hygiene aspects or materials
- G03F7/7085—Detection arrangement, e.g. detectors of apparatus alignment possibly mounted on wafers, exposure dose, photo-cleaning flux, stray light, thermal load
Abstract
The application provides a test method, comprising: acquiring graph information of a test structure, wherein the test structure at least comprises a first graph part and a second graph part which are symmetrical to each other; covering partial area of the test structure by a mask plate; doping the test structure which is not covered by the mask plate or doping the test structure covered by the mask plate; acquiring the resistance of the first graph part and the resistance of the second graph part; and obtaining the offset of the mask for covering the test structure according to the difference value of the resistance of the first graph part and the resistance of the second graph part. The testing method provided by the embodiment of the application can determine the offset of the mask by testing the resistance difference value, the testing time is short, the structure of a semiconductor device is not required to be damaged, and a large amount of tests can be carried out.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a test method.
Background
Currently, in the manufacture of semiconductor devices, a mask is used to expose and etch a layer of the semiconductor device to obtain a desired patterned semiconductor device.
Therefore, when a semiconductor device is manufactured, it is important that the mask covers the position of the semiconductor device, and if the mask is not aligned with the position of the semiconductor device to be exposed and etched, the process for manufacturing the semiconductor device may be deviated, which may decrease the yield of the semiconductor device and increase the manufacturing cost.
In the prior art, in the semiconductor device manufacturing process, the offset of the mask plate relative to the semiconductor device when the mask plate covers the semiconductor device is detected mainly by detecting the relative position of a formed etching pattern by using a production line measuring machine in the manufactured semiconductor device, and the offset of the mask plate is determined by obtaining the difference between the position of the actual etching pattern and the position of a theoretical etching pattern.
However, if the relative position of the formed etching pattern is detected by using the production line machine, the semiconductor devices may need to be damaged for testing, and the testing time is long, so that a large number of tests cannot be performed on each batch of semiconductor devices, and only a small number of sampling tests can be performed.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a testing method, which can save testing time and perform a large number of tests on each batch of semiconductor devices.
The embodiment of the application provides a test method, which comprises the following steps:
acquiring graph information of a test structure, wherein the test structure at least comprises a first graph part and a second graph part which are symmetrical to each other; covering partial area of the test structure by a mask plate;
doping the test structure to obtain the resistance of the first graph part and the resistance of the second graph part;
and obtaining the offset Delta S of the mask for covering the test structure according to the difference value Delta R of the resistance of the first graph part and the resistance of the second graph part.
Optionally, the doping the test structure includes:
and carrying out an ion doping process or a metal silicification process on the test structure which is not covered by the mask.
Optionally, obtaining an offset Δ S of the mask for covering the test structure according to the difference Δ R between the resistance of the first pattern portion and the resistance of the second pattern portion includes:
and if the difference value delta R between the resistance of the first pattern part and the resistance of the second pattern part is larger than 0, the mask plate deviates towards the direction of larger resistance.
Optionally, the doping the test structure includes:
and carrying out an ion doping process or a metal silicification process on the test structure covered by the mask.
Optionally, obtaining an offset Δ S of the mask for covering the test structure according to the difference Δ R between the resistance of the first pattern portion and the resistance of the second pattern portion includes:
and if the difference value delta R between the resistance of the first pattern part and the resistance of the second pattern part is larger than 0, the mask plate deviates towards the direction of smaller resistance.
Optionally, the symmetry axis of the first graph part and the second graph part is a first direction;
the obtaining of the offset Δ S of the mask for covering the test structure according to the difference Δ R between the resistance of the first pattern portion and the resistance of the second pattern portion includes:
and obtaining the difference value of the areas of the mask plate covering the first graph part and the second graph part in the second direction and the offset Delta S of the mask plate covering the test structure in the second direction according to the difference value Delta R of the resistance of the first graph part and the resistance of the second graph part, wherein the second direction is perpendicular to the first direction and is parallel to the test structure.
Optionally, obtaining an offset Δ S of the mask covering the test structure according to a difference Δ R between the resistance of the first pattern portion and the resistance of the second pattern portion includes:
when the first direction is the X-axis direction and the second direction is the Y-axis direction, obtaining an offset Delta S of the mask plate covering the test structure in the Y-axis direction according to a difference Delta R between the resistance of the first graph part and the resistance of the second graph part;
and when the first direction is the Y-axis direction and the second direction is the X-axis direction, obtaining the offset Delta S of the mask plate covering the test structure in the X-axis direction according to the difference Delta R of the resistance of the first graph part and the resistance of the second graph part.
Optionally, the offset of the mask for covering the test structure in the second direction is obtained by a difference between the resistance of the first pattern portion and the resistance of the second pattern portion and a correspondence Δ R ═ f (Δ S).
Optionally, the corresponding relationship is established according to a difference between the resistance of the first pattern portion and the resistance of the second pattern portion and an actual offset of the mask covering the test structure.
Optionally, the actual offset is obtained by detecting a production line measuring machine.
Optionally, the material of the test structure is polysilicon.
Optionally, the end of the test structure has a contact hole, the contact hole is made of a metal material, and the first pattern portion and the second pattern portion are formed on the shallow trench isolation layer.
The test method provided by the embodiment of the application comprises the following steps: acquiring graph information of a test structure, wherein the test structure at least comprises a first graph part and a second graph part which are symmetrical to each other; covering partial area of the test structure by a mask plate; doping the test structure; acquiring the resistance of the first graph part and the resistance of the second graph part; and obtaining the offset of the mask for covering the test structure according to the difference value of the resistance of the first graph part and the resistance of the second graph part.
Therefore, after the test structure which is not covered by the mask is doped, the resistance of the doped test structure can be changed, because the first graph part and the second graph part are mutually symmetrical, if the mask covers the test structure, deviation occurs, the areas covering the first graph part and the second graph part are different, the resistance change of the first graph part and the second graph part after doping is different, the difference exists, and the offset of the mask covering the test structure can be obtained according to the difference of the resistance. The testing method provided by the embodiment of the application can determine the offset of the mask by testing the resistance difference value, the testing time is short, the structure of a semiconductor device is not required to be damaged, and a large amount of tests can be carried out.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following descriptions are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart illustrating a testing method according to an embodiment of the present application;
FIG. 2 shows a schematic diagram of a test structure provided by an embodiment of the present application;
FIG. 3 shows a cross-sectional view of a test structure provided by an embodiment of the present application;
fig. 4-5 are schematic diagrams illustrating a reticle coverage test structure provided by an embodiment of the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited by the specific embodiments disclosed below.
Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration, and the drawings are only examples, which should not limit the scope of the protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
As described in the background, when manufacturing a semiconductor device, a layer of the semiconductor device needs to be exposed and etched by using a mask to obtain a desired patterned semiconductor device.
Therefore, when the semiconductor device is manufactured, it is important that the mask covers the position of the semiconductor device, and if the mask is not aligned with the position of the semiconductor device to be exposed and etched, the process for manufacturing the semiconductor device may be deviated, which may decrease the yield of the semiconductor device and increase the manufacturing cost.
Currently, in a semiconductor device manufacturing process, a production line measuring machine, such as a Transmission Electron Microscope (TEM) measuring machine, is used to detect a relative position of a formed actual etching pattern in a manufactured semiconductor device, so as to obtain a difference between a position of the actual etching pattern and a position of a theoretical etching pattern to determine an offset of a mask plate with respect to a detection of the offset of the mask plate with respect to the semiconductor device when the mask plate covers the semiconductor device.
However, if the TEM metrology tool is used to detect the relative position of the formed etched pattern, the semiconductor devices need to be destroyed for testing, and the testing time is long, so that a large number of tests cannot be performed on each batch of semiconductor devices, and only a small number of sampling tests can be performed.
Based on this, the embodiment of the present application provides a test method, including: acquiring graph information of a test structure, wherein the test structure at least comprises a first graph part and a second graph part which are symmetrical to each other; covering partial area of the test structure by a mask plate; doping the test structure; acquiring the resistance of the first graph part and the resistance of the second graph part; and obtaining the offset of the mask for covering the test structure according to the difference value of the resistance of the first graph part and the resistance of the second graph part.
Therefore, after the test structure is doped, the resistance of the doped test structure can change, and because the first graph part and the second graph part are mutually symmetrical, if the mask covers the test structure, no deviation exists, namely the areas covering the first graph part and the second graph part are the same, the resistance change of the first graph part and the second graph part is the same after doping, and the resistance of the first graph part and the second graph part is the same; if the mask covers the test structure, deviation occurs, so that the areas covering the first graph part and the second graph part are different, the resistance changes of the first graph part and the second graph part are different after doping, differences exist, and the offset of the mask covering the test structure can be obtained according to the difference of the resistance. The testing method provided by the embodiment of the application can determine the offset of the mask by testing the resistance difference value, the testing time is short, the structure of a semiconductor device is not required to be damaged, and a large amount of tests can be carried out.
For better understanding of the technical solutions and effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a flowchart of a testing method provided in an embodiment of the present application is shown, where the method may include:
s101, obtaining graph information of a test structure 100, wherein the test structure 100 at least comprises a first graph part 110 and a second graph part 120 which are symmetrical to each other; the mask 130 covers a part of the area of the test structure 100.
In the embodiment of the present application, referring to fig. 2, the test structure 100 is a semiconductor structure to be tested, and the test structure 100 may be a multi-layer structure or a single-layer structure. The material of one layer in the test structure 100 is a semiconductor material, such as polysilicon, or other semiconductor materials. The pattern information of the test structure 100 may be a pattern of a patterned film layer, such as a pattern information of a metal interconnection line. The test structure 100 includes at least two patterns that are symmetrical to each other: a first graphic component 110 and a second graphic component 120. As can be seen in fig. 2, the first graphic part 110 and the second graphic part 120 are arranged in central symmetry.
In the embodiment of the present application, when the test structure is subjected to the next manufacturing process, the mask plate 130 covers a part of the area of the test structure 100, that is, the mask plate 130 covers a part of the test structure, so as to expose and etch the test structure 100 by using the mask plate 130. When the mask plate 130 covers the test structure 100, the test structure 100 needs to be aligned in order to obtain a desired semiconductor device, for example, the areas of the mask plate 130 covering the first pattern portion 110 and the second pattern portion 120 are the same, so that the same process is performed on the remaining first pattern portion 110 and the second pattern portion 120 which are not covered by the mask plate 130.
In practical applications, referring to fig. 3, the material of the test structure 100 may be polysilicon, the end portion may have a contact hole, for example, the contact hole may be located on the first pattern part 110 and the second pattern part 120, the material of the contact hole may be a metal material, and the first pattern part 110 and the second pattern part 120 may be formed on the shallow trench isolation layer.
S102, doping the test structure 100.
In the embodiment of the present application, when the mask plate 130 covers a part of the area of the test structure 100, the test structure 100 not covered by the mask plate 130 may be doped, or the test structure covered by the mask plate 130 may be doped. Specifically, the doping may be performed by an ion doping process, a metal silicidation process, or other doping processes.
As an example, the test structure 100 that is not covered by the mask 130 may be doped by an ion doping process of ion implantation, and the doped ions may be metal ions such as Ni, Ti, or Co.
As another example, a metal silicidation process may be used to dope test structures 100 that are not masked by reticle 130. The metal silicification process is to form a metal layer on the semiconductor structure after the semiconductor structure is formed, and the metal layer and the semiconductor material in contact with the metal layer are reacted through a heat treatment process to form metal silicide, so that the Schottky barrier between the metal and the semiconductor material is favorably reduced. The material of the metal layer may be, for example, Ni, Ti, Co, or the like. After a silicidation process with Ni, Ti, Co, etc. on the exposed silicon of the semiconductor material, a layer of a metal silicide is formed, respectively NiSi x 、TiSi x 、CoSi x (ii) a After a silicidation process with Ni, Ti, Co, etc. on the exposed silicon germanium of the semiconductor material, a metal silicide layer is formed, respectively NiSi x Ge y 、TiSi x Ge y 、CoSi x Ge y . The metal layer and the metal silicide layer are merely examples, and may be any other metal silicide layer that can be formed of a metal material that can undergo a metal silicidation reaction.
In the embodiment of the present application, after doping the test structure 100 by using the mask 130, the resistance of the doped test structure 100 changes.
As an example, after doping the test structure 100 that is not covered by the mask 130, the resistance of the test structure 100 that is not covered by the mask 130 changes, for example, the resistance of the test structure 100 after performing the metal silicidation process becomes smaller. At this time, if the areas of the first pattern part 110 and the second pattern part 120 covered by the mask 130 are the same, after the silicidation process is performed on the remaining first pattern part 110 and second pattern part 120 which are not covered by the mask 130, the values of the resistances of the first pattern part 110 and the second pattern part 120 which become smaller are the same, that is, the resistance of the first pattern part 110 and the resistance of the second pattern part 120 are the same.
As another example, after doping the test structure 100 covered by the mask 130, the resistance of the test structure 100 covered by the mask 130 changes, for example, the resistance of the test structure 100 after performing the metal silicidation process becomes smaller. At this time, if the areas of the first pattern part 110 and the second pattern part 120 covered by the mask 130 are the same, after the metal silicidation is performed on the remaining first pattern part 110 and the second pattern part 120 covered by the mask 130, the values of the resistances of the first pattern part 110 and the second pattern part 120 which become smaller are the same, that is, the resistance of the first pattern part 110 and the resistance of the second pattern part 120 are the same.
S103, obtaining the resistance of the first graph portion 110 and the resistance of the second graph portion 120.
In an embodiment of the present application, the resistance of the first pattern part 110 and the resistance of the second pattern part 120 may be obtained after the doping process is performed. For example, a test voltage may be electrically connected using a contact hole located on the first pattern part 110 or the second pattern part 120, and a test current may flow through the first pattern part 110 or the second pattern part 120, resulting in the resistance of the first pattern part 110 and the resistance of the second pattern part 120.
S104, obtaining the offset Delta S of the mask for covering the test structure according to the difference Delta R between the resistance of the first graph part 110 and the resistance of the second graph part 120.
In the embodiment of the present application, the offset Δ S of the mask 130 covering the test structure 100, that is, the difference between the areas of the mask 130 covering the first pattern portion 110 and the second pattern portion 120, is obtained according to the obtained difference Δ R between the resistance of the first pattern portion 110 and the resistance of the second pattern portion 120.
In practical applications, the resistance of the test structure 100 after the metal silicidation process is performed becomes small. If the areas of the mask 130 covering the first pattern portion 110 and the second pattern portion 120 are different, there are two possible implementations:
in the first implementation manner, after the first pattern part 110 and the second pattern part 120 that are not covered by the mask 130 are subjected to the metal silicidation, the smaller values of the resistances of the first pattern part 110 and the second pattern part 120 are different, that is, the resistance of the first pattern part 110 is different from the resistance of the second pattern part 120. When the resistance of the first pattern portion 110 is different from the resistance of the second pattern portion 120, the mask 130 may be shifted in a direction in which the resistance is greater when a difference Δ R between the resistance of the first pattern portion 110 and the resistance of the second pattern portion 120 is greater than 0. That is, when the mask 130 covers the test structure 100, if the mask is more biased toward the first pattern portion 110, that is, the covered area of the first pattern portion 110 is larger than the covered area of the second pattern portion 120, and the area of the exposed first pattern portion 110 is smaller than the area of the exposed second pattern portion 120, the area of the first pattern portion 110 subjected to the metal silicidation process is smaller than the area of the second pattern portion 120 subjected to the metal silicidation process, and finally the resistance of the first pattern portion 110 is smaller than the resistance of the second pattern portion 120, and the resistance of the first pattern portion 110 is larger than the resistance of the second pattern portion 120.
In a second implementation manner, after the first pattern portion 110 and the second pattern portion 120 covered by the mask 130 are subjected to the metal silicidation, the smaller values of the resistances of the first pattern portion 110 and the second pattern portion 120 are different, that is, the resistance of the first pattern portion 110 is different from the resistance of the second pattern portion 120. When the resistance of the first pattern portion 110 is different from the resistance of the second pattern portion 120, the mask 130 may be shifted in a direction in which the resistance is smaller if a difference Δ R between the resistance of the first pattern portion 110 and the resistance of the second pattern portion 120 is greater than 0. That is, when the mask 130 covers the test structure 100, if the mask is more biased toward the first pattern portion 110, that is, the covered area of the first pattern portion 110 is larger than the covered area of the second pattern portion 120, the area of the first pattern portion 110 subjected to the metal silicidation process is larger than the area of the second pattern portion 120 subjected to the metal silicidation process, and finally the resistance of the first pattern portion 110 is smaller than the resistance of the second pattern portion 120, and the resistance of the first pattern portion 110 is smaller than the resistance of the second pattern portion 120.
In practical applications, referring to fig. 4, the first pattern portion 110 and the second pattern portion 120 are symmetrical to each other, so that when the mask 130 covers the test structure 100, an offset of the mask 130 cannot be obtained in a direction parallel to the symmetry axes of the first pattern portion 110 and the second pattern portion 120, at this time, the symmetry axes of the first pattern portion 110 and the second pattern portion 120 are set to be the first direction, and a direction perpendicular to the first direction and parallel to the test structure 100 is set to be the second direction, so that a difference Δ R between areas of the mask 130 covering the first pattern portion 110 and the second pattern portion 120 in the second direction and an offset Δ S of the mask 130 covering the test structure 100 in the second direction can be obtained according to a difference Δ R between the resistance of the first pattern portion 110 and the resistance of the second pattern portion 120 obtained by the test.
In practical applications, the offset of the mask 130 in the masking test structure 100 may be a two-dimensional vector, i.e., the mask 130 may be offset from left to right or from top to bottom. Referring to fig. 4, when the first direction, i.e. the direction of the symmetry axis, is the X-axis direction, and the second direction is the Y-axis direction, the offset Δ S of the mask 130 covering the test structure 100 in the Y-axis direction can be obtained according to the difference Δ R between the resistance of the first pattern part 110 and the resistance of the second pattern part 120; referring to fig. 4, when the first direction, i.e., the direction of the symmetry axis, is the Y-axis direction, and the second direction is the X-axis direction, the offset Δ S of the mask 130 covering the test structure in the X-axis direction is obtained according to the difference Δ R between the resistance of the first pattern part 110 and the resistance of the second pattern part 120. This results in two-dimensional offsets of reticle 130 in the X-axis direction and the Y-axis direction.
In the embodiment of the present application, the offset of the mask 130 covering the test structure 100 is obtained by a difference between the resistance of the first pattern portion 110 and the resistance of the second pattern portion 120 and a correspondence relationship Δ R ═ f (Δ S), where the correspondence relationship is a correspondence relationship between the difference Δ R between the resistance of the first pattern portion 110 and the resistance of the second pattern portion 120 and the offset Δ S of the mask 130 covering the test structure 100, and the correspondence relationship Δ R ═ f (Δ S) may be a linear relationship. The correspondence Δ R ═ f (Δ S) can be established by the difference between the resistance of the first pattern portion 110 and the resistance of the second pattern portion 120 and the actual offset by which the mask 130 covers the test structure 100, for example, a linear relationship can be established between the difference between the resistance of the first pattern portion 110 and the resistance of the second pattern portion 120 and the actual offset by which the mask 130 covers the test structure 100. Specifically, the actual offset of the mask 130 covering the test structure 100 may be detected by a production line measuring machine, which may be a TEM measuring machine of a transmission electron microscope.
Therefore, according to the embodiment of the application, the actual offset of the mask 130 covering the test structure 100 can be obtained only by detecting the difference of the resistance after doping by using the mask 130 through establishing the corresponding relationship between the actual offset of the mask 130 covering the test structure 100 and the difference of the resistance after doping by using the mask 130 in the test structure.
The test method provided by the embodiment of the application comprises the following steps: acquiring graph information of a test structure, wherein the test structure at least comprises a first graph part and a second graph part which are symmetrical to each other; covering partial area of the test structure by a mask plate; doping the test structure; acquiring the resistance of the first graph part and the resistance of the second graph part; and obtaining the offset of the mask for covering the test structure according to the difference value of the resistance of the first graph part and the resistance of the second graph part.
After the test structure is doped, the resistance of the doped test structure can change, because the first graph part and the second graph part are mutually symmetrical, if the mask covers the test structure, no deviation exists, namely the areas covering the first graph part and the second graph part are the same, the resistance change of the first graph part and the second graph part is the same after doping, and the resistance of the first graph part and the resistance of the second graph part are the same; if the mask covers the test structure, deviation occurs, so that the areas covering the first graph part and the second graph part are different, the resistance changes of the first graph part and the second graph part are different after doping, differences exist, and the offset of the mask covering the test structure can be obtained according to the difference of the resistance. The testing method provided by the embodiment of the application can determine the offset of the mask by testing the resistance difference value, the testing time is short, the structure of a semiconductor device is not required to be damaged, and a large amount of tests can be carried out.
The foregoing is merely a preferred embodiment of the present application and, although the present application discloses the foregoing preferred embodiments, the present application is not limited thereto. Those skilled in the art can now make numerous possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the claimed embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still fall within the protection scope of the technical solution of the present application without departing from the content of the technical solution of the present application.
Claims (6)
1. A method of testing, comprising:
acquiring graph information of a test structure, wherein the test structure at least comprises a first graph part and a second graph part which are symmetrical to each other; the mask plate covers part of the area of the test structure;
doping the test structure which is not covered by the mask plate or doping the test structure which is covered by the mask plate;
acquiring the resistance of the first graph part and the resistance of the second graph part;
obtaining the offset deltaS of the mask for covering the test structure in the direction of larger resistance or in the direction of smaller resistance according to the difference deltaR between the resistance of the first graph part and the resistance of the second graph part and the linear corresponding relation deltaR-f (deltaS);
the linear corresponding relation is established according to the difference value of the resistance of the first graph part and the resistance of the second graph part and the actual offset of the mask plate covering the test structure;
the doping the test structure which is not covered by the mask or the doping the test structure which is covered by the mask comprises:
carrying out an ion doping process or a metal silicification process on the test structure which is not covered by the mask;
the obtaining, according to the difference Δ R between the resistance of the first pattern portion and the resistance of the second pattern portion and the linear correspondence Δ R ═ f (Δ S), the offset Δ S of the mask plate in a direction in which the resistance is larger or in a direction in which the resistance is smaller when the mask plate covers the test structure, includes:
if the difference value delta R between the resistance of the first graph part and the resistance of the second graph part is larger than 0, the mask plate deviates towards the direction with larger resistance;
or the like, or, alternatively,
the doping the test structure which is not covered by the mask or the doping the test structure which is covered by the mask comprises:
carrying out an ion doping process or a metal silicification process on the test structure covered by the mask plate;
obtaining, according to a difference Δ R between the resistance of the first pattern portion and the resistance of the second pattern portion and a linear correspondence Δ R ═ f (Δ S), an offset Δ S of the mask masking covering the test structure in a direction in which the resistance is larger or in a direction in which the resistance is smaller, includes:
and if the difference value delta R between the resistance of the first graph part and the resistance of the second graph part is larger than 0, the mask plate deviates to the direction with smaller resistance.
2. The test method according to claim 1, wherein the symmetry axis of the first pattern part and the second pattern part is a first direction;
the obtaining of the offset Δ S of the mask for covering the test structure according to the difference Δ R between the resistance of the first pattern portion and the resistance of the second pattern portion includes:
and obtaining the difference value of the areas of the mask plate covering the first graph part and the second graph part in the second direction and the offset Delta S of the mask plate covering the test structure in the second direction according to the difference value Delta R of the resistance of the first graph part and the resistance of the second graph part, wherein the second direction is perpendicular to the first direction and is parallel to the test structure.
3. The method according to claim 2, wherein obtaining an offset Δ S of the mask covering the test structure according to a difference Δ R between the resistance of the first pattern portion and the resistance of the second pattern portion comprises:
when the first direction is the X-axis direction and the second direction is the Y-axis direction, obtaining an offset Delta S of the mask plate covering the test structure in the Y-axis direction according to a difference Delta R between the resistance of the first graph part and the resistance of the second graph part;
and when the first direction is the Y-axis direction, the second direction is the X-axis direction, and the offset delta S of the mask plate for covering the test structure in the X-axis direction is obtained according to the difference delta R between the resistance of the first graph part and the resistance of the second graph part.
4. The testing method of claim 1, wherein the actual offset is detected by a production line metrology tool.
5. The method of claim 1, wherein the material of the test structure is polysilicon.
6. The test method as claimed in claim 5, wherein the end of the test structure has a contact hole, the material of the contact hole is a metal material, and the first pattern portion and the second pattern portion are formed over a shallow trench isolation layer.
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| TW564512B (en) * | 2002-10-09 | 2003-12-01 | Nanya Technology Corp | Test key of detecting whether the overlay of gate structure and deep trench capacitor of DRAM with vertical transistors is normal and test method of the same |
| CN105742349B (en) * | 2014-12-08 | 2019-12-27 | 中芯国际集成电路制造(上海)有限公司 | Method for improving MOS device performance and MOS device structure |
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