CN105742349B - Method for improving MOS device performance and MOS device structure - Google Patents
Method for improving MOS device performance and MOS device structure Download PDFInfo
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- CN105742349B CN105742349B CN201410747645.1A CN201410747645A CN105742349B CN 105742349 B CN105742349 B CN 105742349B CN 201410747645 A CN201410747645 A CN 201410747645A CN 105742349 B CN105742349 B CN 105742349B
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Abstract
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for improving the performance of an MOS device and an MOS device structure.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for improving the performance of an MOS device and an MOS device structure.
Background
With the continuous reduction of the size of semiconductor devices, when manufacturing transistors, it is more and more difficult to obtain channels with sufficient effective lengths, and Short Channel Effects (SCE) are serious due to too short channel lengths; because the ultra-shallow junction process (USJ for short) can effectively improve the short channel effect of the core device, it is widely applied in the preparation process of MOS devices.
However, as the size of the device is smaller and smaller, the difficulty in balancing the performance of the device and controlling the SCE is greater and greater when the MOS device is manufactured by using the ultra shallow junction process (the trade off of performance and short channel control of the device a big change of surface and more); at present, the performance of the device is improved by optimizing a Low Doped Drain (LDD) process and a Pocket Implantation/halo Implantation (Pocket Implantation) process mainly through processes such as a Pre-amorphization Implantation (PAI), a Co-ion Implantation (Co-Implantation), a stress layer (stress), and the like.
For example, when manufacturing a MOS device, a light doping process (LDD), Pocket implantation (Halo IMP or Pocket IMP), and a rapid thermal annealing process (RTP) are generally performed on a MOS structure having a gate stack structure, and then a source/drain ion implantation process (S/dimply) and a rapid thermal annealing process (RTP) are performed, and a metal silicidation process (silicide process) is performed on a source/drain region; however, the MOS device structure manufactured by the prior art has a large surface resistance, and further enhances a Drain induced barrier lowering effect (DIBL) and a Short Channel Effect (SCE), thereby affecting the performance of the finally manufactured MOS device.
Disclosure of Invention
In view of the above technical problems, the present application provides a method for improving performance of a MOS device, which can be applied to a technology node process of 22nm and below, the method including:
providing a semiconductor substrate, and preparing a gate stack structure comprising a side wall on the semiconductor substrate, wherein the side wall has a first thickness;
after the light doping process, widening the side wall to increase the thickness of the side wall to a second thickness;
performing a first metal silicide process to form a first metal silicide region extending to the lower part of the side wall;
and continuing the preparation process of the source/drain region.
The method for improving the performance of the MOS device, wherein the method further comprises:
after the light doping process, a first bag-shaped injection process and a rapid thermal annealing process are firstly carried out to form a light doped region in a region of the semiconductor substrate close to the gate stack structure, and then the widening operation is carried out on the side wall.
In the method for improving the performance of the MOS device, the first metal silicidation process is performed at a temperature of 250 to 450 ℃ by using nickel or platinum.
The method for improving the performance of the MOS device is described above, wherein the semiconductor substrate is a silicon substrate or a silicon-on-insulator.
The method for improving the performance of the MOS device is described above, wherein the crystal orientation of the silicon substrate is <110> or <100 >.
In the method for improving performance of the MOS device, when the semiconductor substrate is a silicon substrate, the source/drain region preparation process includes:
performing source/drain ion implantation in a region of the silicon substrate adjacent to the gate stack structure to form a source region and a drain region;
after a second metal silicification process is carried out on the source region and the drain region, a through hole etching stop layer is prepared;
etching the through hole etching stop layer positioned on the source region and the silicon substrate positioned in the source region, and reserving the first metal silicide region positioned below the side wall to form a source region groove;
and preparing a metal layer to fill the source region groove.
In the method for improving the performance of the MOS device, the silicon substrate located in the source region is etched by using an isotropic etching process.
In the method for improving the performance of the MOS device, the second metal silicidation process is performed at a temperature of 250 to 450 ℃ by using nickel or platinum.
In the method for improving performance of the MOS device, when the semiconductor substrate is a silicon-on-insulator, the source/drain region preparation process includes:
etching the silicon on the insulator, and reserving the first metal silicide region positioned below the side wall so as to form a source region groove and a drain region groove in a region of the silicon on the insulator, which is adjacent to the gate stack structure;
preparing an epitaxial layer to fill the source region groove and the drain region groove so as to form a source region and a drain region;
and carrying out a third metal silicidation process on the epitaxial layer so as to convert the epitaxial layer in the source region and the drain region into a third metal silicide region.
In the method for improving the performance of the MOS device, the third metal silicidation process is performed at a temperature of 250 to 450 ℃ by using nickel or platinum.
The method for improving the performance of the MOS device is characterized in that the thickness of the epitaxial layer is 10 nm-80 nm.
The method for improving the performance of the MOS device, wherein the method further comprises:
and after the epitaxial layer is prepared, carrying out a second bag-shaped injection process on the epitaxial layer to form the source region and the drain region.
The method for improving the performance of the MOS device is described above, wherein the ion implantation dosage of the second pocket implantation process is 5e12/cm2～2e13/cm2。
The present application further recites a MOS device structure, wherein the MOS device structure comprises:
a semiconductor substrate formed with a lightly doped region;
the grid stacking structure is arranged on the semiconductor substrate and comprises a side wall;
and forming a metal silicide region in the semiconductor substrate below the side wall in the lightly doped region.
In the MOS device structure, the semiconductor substrate is a silicon substrate or a silicon-on-insulator.
In the above MOS device structure, the crystal orientation of the silicon substrate is <110> or <100 >.
In the above MOS device structure, a source region and a drain region are further disposed in the semiconductor substrate.
In the above MOS device structure, when the semiconductor substrate is a silicon substrate, a metal layer is disposed in the source region.
In the MOS device structure, when the semiconductor substrate is a silicon-on-insulator, the source region and the drain region are both made of metal silicide.
In summary, according to the above technical solution, the method for improving performance of the MOS device and the MOS device structure provided in the present application form the metal silicide region extending to the lower side of the gate sidewall through a metal silicide process, so as to reduce the distance between the metal silicide region and the gate, so as to achieve the purpose of reducing the surface resistance of the device channel, and the drain induced barrier lowering effect (DIBL) and the Short Channel Effect (SCE) of the device can be further reduced by embedding a metal layer in the substrate of the source region or forming the fully metal silicided source region and drain region, so as to improve the performance and yield of the MOS device.
Drawings
FIGS. 1-10 are schematic views of flow structures of a method for improving the performance of a MOS device according to an embodiment of the present invention;
FIGS. 11 to 16 are schematic diagrams illustrating a flow chart of a method for improving the performance of a MOS device according to a second embodiment of the present application;
fig. 17 is a schematic structural diagram of a trimos device structure according to an embodiment of the present application;
fig. 18 is a schematic structural diagram of a structure of a four-MOS device according to an embodiment of the present application.
Detailed Description
The method for improving the performance of the MOS device can be applied to technical nodes of 22nm and below, and can be used in the process of preparing the MOS device (such as a PMOS device, an NMOS device and the like) On a substrate of Silicon or Silicon On Insulator (SOI for short) and the like.
The following further describes embodiments of the present invention with reference to the drawings:
example one
FIGS. 1-10 are schematic views of flow structures of a method for improving the performance of a MOS device according to an embodiment of the present invention; as shown in fig. 1 to 10, the present embodiment is a process for manufacturing a MOS device based on a silicon substrate, specifically:
as shown in fig. 1, after the gate stack structure 12 is fabricated on the silicon substrate 11 (the crystal orientation of the silicon substrate 11 may be <110>, <100> or other crystal orientation), a light doping process (LDD) is used to continue the ion implantation into the region of the silicon substrate 11 adjacent to the gate stack structure 12, and a Pocket implantation (Pocket IMP) and a Rapid Thermal Annealing (RTA) process are continued to form a Lightly doped region 13 in the region of the silicon substrate 11 adjacent to the gate stack structure.
Preferably, the gate stack structure 12 includes a gate oxide layer 121, a gate electrode 122, a gate low-resistance layer 123 and a sidewall 124, where the gate oxide layer 121 covers part of the upper surface of the silicon substrate 11, the gate electrode 122 covers the upper surface of the gate oxide layer 121, the gate low-resistance layer 123 covers the upper surface of the gate electrode 122, and the sidewall 124 covers sidewalls of the gate oxide layer 121, the gate electrode 122 and the gate low-resistance layer 123; the lightly doped region 13 extends into the silicon substrate under the sidewall and a portion of the gate oxide layer 121, and the sidewall 124 has a first thickness parallel to the extending direction of the upper surface of the silicon substrate 11, i.e. H1 shown in fig. 1.
As shown in fig. 2, based on the structure shown in fig. 1, a widening operation (i.e., a sidewall film 125 is prepared on the exposed sidewall of the sidewall 124, and the material, preparation process, and physical and chemical properties of the sidewall film 125 are the same as those of the sidewall 124, so that the sidewall 124 and the sidewall film 125 jointly form a sidewall of the gate 122, and the sidewall has a second thickness H2(H2 > H1); specifically, the sidewall film 125 may be fabricated by a conventional method in the art, such that the fabricated sidewall film 125 is located on the lightly doped region 13 and covers the exposed sidewall of the sidewall 124.
As shown in fig. 3, based on the structure shown in fig. 2, a first metal silicide process is performed on the lightly doped region 13 to reduce the sheet resistance (LDD silicide for lower Rs) of the lightly doped region 13, that is, a first metal silicide region 14 is formed in the lightly doped region 13, the first metal silicide region 14 extends to below the sidewall formed by the sidewall 124 and the sidewall film 125, but the sidewall has a thicker thickness H2, so that the first metal silicide region 14 cannot extend to a too long length (cannot extend to the right under the gate oxide layer 121), and can only be formed in the lightly doped region 13, i.e., the channel region under the first metal silicide region 14 and the gate 122 is separated by the portion of the lightly doped region 13.
Preferably, the lightly doped region 13 may be subjected to the first metal silicidation process by using a metal (nickel or Pt) such as nickel or platinum at a temperature (reaction temperature) of 250 to 450 ℃ (e.g., 250 ℃, 300 ℃, 400 ℃ or 450 ℃).
Since the first metal silicide region 14 is partially extended to the lower portion of the sidewall of the gate 122, the spatial distance between the first metal silicide region 14 and the gate 122 is shortened, and the surface resistance of the channel region of the MOS device can be effectively reduced; for example, When the spatial distance between the first metal silicide region 14 and the gate 122 is reduced from18nm to 12nm, the surface resistance of the channel region thereof can be reduced by about 20ohm (When silicide to poly space change from18 to 18nm to 12nm, R-external will reduce about 20 ohm).
As shown in fig. 4, a source/drain ion implantation process (SD implant) and an annealing process are performed on the structure shown in fig. 3 to form a source region 151 and a drain region 152 in the silicon substrate 11, and a portion of the lightly doped region 13 and the first metal silicide region 14 under the sidewall is remained; the structure shown in fig. 4 is continuously subjected to a second metal silicide process to form a second metal silicide layer 16 in the top regions of the source region 151 and the drain region 152, and the second metal silicide layer 16 is surrounded by the remaining portions of the source region 151 and the drain region 152 to reduce the surface resistance of the source region 151 and the drain region 152, thereby forming the structure shown in fig. 5.
Preferably, the second metal silicidation process (silicide) may be performed using a metal such as nickel or platinum (nickel or Pt) at a temperature (reaction temperature) of 250 to 450 ℃ (e.g., 250 ℃, 350 ℃, 420 ℃ or 450 ℃).
As shown in fig. 6, after preparing a Contact Etch Stop Layer (CESL) 17 based on the structure shown in fig. 5, a mask Layer 18 having a source region recess pattern is formed, that is, as shown in fig. 7, the mask Layer 18 covers the upper surfaces of the gate stack structure 12 and the sidewall film 125, and covers the upper surface of the Contact Etch Stop Layer 17 above the drain region 152, so as to expose the Contact Etch Stop Layer 17 (i.e., the via Etch Stop Layer) above the source region 151.
Further, using the mask layer 18 as a mask, an anisotropic etching process is used to etch the exposed contact hole etching stop layer 17 (i.e. the contact hole etching stop layer 17 located above the source region 151) and stop in the silicon substrate 11, so as to form a source region recess (not shown in the figure, i.e. a gap portion above the remaining portion of the source region 151), i.e. the structure shown in fig. 8.
Preferably, an isotropic etching process may also be used, and the exposed contact hole etching stop layer 17 (i.e., the contact hole etching stop layer 17 located above the source region 151) is etched by using the mask layer 18 as a mask and stopped in the silicon substrate 11 to form the structure shown in fig. 9 (this embodiment is described in detail by an anisotropic etching process, and a MOS device manufacturing process by using the isotropic etching process can be realized by combining a conventional technical means on the basis of this embodiment.
After the etching process using the mask layer 18 as a mask, the lightly doped region 13 and the first metal silicide region 14 under the sidewall of the gate 122 remain.
As shown in fig. 10, based on the structure shown in fig. 8, the recess is filled with metal (e.g., tungsten, copper, etc.), and a metal layer 19 is formed after planarization.
In the first embodiment, the first metal silicide layer 14 extending to the lower side of the gate stack structure 12 is disposed in the prepared MOS device structure, so that the spatial distance between the metal silicide layer 14 and the gate 122 is shortened, the surface resistance of the MOS device structure channel can be effectively reduced, and the drain induced barrier lowering effect (DIBL) and the Short Channel Effect (SCE) are further reduced by preparing the metal layer in the source region of the MOS device structure, thereby improving the performance and yield of the MOS device.
Example two
FIGS. 11 to 16 are schematic diagrams illustrating a flow chart of a method for improving the performance of a MOS device according to a second embodiment of the present application; as shown in fig. 11 to 16, based on the first embodiment, the process for manufacturing a MOS device based on silicon-on-insulator (SOI) in this embodiment specifically includes:
as shown in fig. 11, the SOI substrate 21 includes a back substrate 211, a buried oxide layer 212 and a top silicon layer 213, the buried oxide layer 212 covering the upper surface of the back substrate 211, the top silicon layer 213 covering the upper surface of the buried oxide layer 212; after the gate stack structure 22 is formed on the top silicon 213, a Light Doped Dopant (LDD) process is performed to continue ion implantation in a region of the top silicon 213 adjacent to the gate stack structure 12, and a Pocket implant (Pocket IMP or Halo IMP) and a Rapid Thermal Annealing (RTA) process are performed to form a Lightly Doped region 23 in a region of the top silicon 213 adjacent to the gate stack structure.
Preferably, the gate stack structure 22 includes a gate oxide layer 221, a gate electrode 222 and a sidewall 223, the gate oxide layer 221 covers a part of the upper surface of the top silicon 213, the gate electrode 222 covers the upper surface of the gate oxide layer 221, and the sidewall 223 covers the sidewalls of the gate oxide layer 221 and the gate electrode 222; the lightly doped region 23 extends into the sidewall 223 and a portion of the top silicon 213 under the gate oxide layer 221, and the sidewall 223 has a third thickness parallel to the extending direction of the upper surface of the top silicon 213, i.e. H3 shown in fig. 11.
As shown in fig. 12, based on the structure shown in fig. 11, a widening operation (i.e., a sidewall film 224 is prepared on the exposed sidewall of the sidewall 223, and the material, preparation process, and physicochemical properties of the sidewall film 224 are the same as those of the sidewall 223, so that the sidewall 223 and the sidewall film 224 jointly form a sidewall of the gate 222, and the sidewall has a fourth thickness H4(H4 > H3); specifically, the sidewall film 224 may be fabricated by a conventional technique in the industry, such that the fabricated sidewall film 224 is located on the lightly doped region 23 and covers the exposed sidewall of the sidewall 223.
As shown in fig. 13, based on the structure shown in fig. 12, a third metal silicide process is performed on the lightly doped region 23 to form a third metal silicide region 24 in the lightly doped region 23, where the third metal silicide region 24 extends to a position below a sidewall formed by the sidewall 223 and the sidewall film 224, but the sidewall has a relatively thick thickness H4, so that the third metal silicide region cannot extend to a long length (i.e., cannot extend to a position right below the gate oxide layer 221), and can only be formed in the lightly doped region 23, i.e., the third metal silicide region 24 is separated from the channel region below the gate 222 by a portion of the lightly doped region 13.
Preferably, the lightly doped region 23 may be subjected to a third metal silicidation process using a metal (nickel or Pt) such as nickel or platinum at a temperature (reaction temperature) of 250 to 450 ℃ (e.g., 250 ℃, 330 ℃, 430 ℃ or 450 ℃).
Since the part of the third metal silicide region 24 is extended to the lower portion of the sidewall of the gate 222, the space distance between the third metal silicide region 24 and the gate 222 is shortened, and the surface resistance of the channel region of the MOS device can be effectively reduced.
As shown in fig. 14, based on the structure shown in fig. 13, the top silicon 213 may be partially etched by using various anisotropic etching processes such as dry etching, and the like, and the etching process is stopped in the top silicon 213 to leave the lightly doped region 23 and the third metal silicide region 24 under the gate stack 22 and the sidewall spacers 224 (i.e., the remaining lightly doped region 23 and the remaining third metal silicide region 24 are removed), so as to form a source region recess and a drain region recess (not shown in the figure, i.e., the gap portions of the top silicon 213 at two sides of the gate stack 22) in the top silicon 213.
As shown in fig. 15, based on the structure shown in fig. 14, an epitaxial layer 26 (which may be SiGe or the like) is epitaxially grown in the source region recess and the drain region recess, and source and drain regions (Epi SDprocess) are formed in the epitaxial layer 26, while the upper surface of the epitaxial layer 26 and the upper surface of the remaining portion of the top silicon 213 (i.e., the top silicon located below the gate stack 22) are at the same level.
Preferably, the space occupied by the source region recess and the drain region recess is 3% to 15% (e.g., 3%, 8%, 13%, or 15%) of the entire top silicon volume, and the thickness of the epitaxial layer 26 is 10nm to 80 nm.
Further, a fourth metallization process is performed on the epitaxial layer 26 to form a source/drain region 27(SD full silicide) made of metal silicide, thereby forming the structure shown in fig. 17.
Preferably, the source/drain region 27 is made of metal silicide, and the fourth metal silicidation process may be performed on the source/drain region 27 by using metal (nickel or Pt) such as nickel or platinum under a temperature (reaction temperature) condition of 250 to 450 ℃ (e.g., 250 ℃, 380 ℃, 480 ℃ or 450 ℃).
Preferably, after the preparation of the epitaxial layer 26 described above5e12/cm can be used2～2e13/cm2A second pocket implant process is performed on the epitaxial layer 26 to form the source and drain regions.
In the second embodiment, the third metal silicide layer 24 extending to the lower side of the gate stack structure 22 is arranged in the prepared MOS device structure, so that the spatial distance between the metal silicide layer 24 and the gate 222 is shortened, the surface resistance of the MOS device structure channel can be effectively reduced, and the source/drain region 27 made of metal silicide is arranged, so that the surface resistance is greatly reduced (compared with the surface resistance of the conventional source/drain electrode of 200ohm/sq, the source/drain electrode surface resistance of the MOS device in the second embodiment can be reduced to about 20 ohm/sq), and further the performance of the device is greatly improved; meanwhile, compared with the conventional process, the present embodiment also omits a source/drain ion implantation process and a subsequent annealing process (blanking S/D implant & RTA process), thereby greatly reducing the difficulty and cost of the process, and can also improve a window (LDD window improved by improved doping) of the lightly doped process, thereby effectively controlling a drain induced barrier lowering effect (DIBL) and a Short Channel Effect (SCE) of the device structure, so as to improve the performance and yield of the MOS device.
EXAMPLE III
Fig. 17 is a schematic structural diagram of a trimos device structure according to an embodiment of the present application; as shown in fig. 17, the method described in the first embodiment can be used to prepare a MOS device structure in this embodiment, where the MOS device structure includes:
a silicon substrate 31, the crystal orientation of the silicon substrate 31 may be <110>, <100>, or other crystal orientations. The gate stack structure 39 is disposed on the silicon substrate 31, and the gate stack structure 39 includes a gate oxide layer 391, a gate 392, a low resistance layer 393 and a sidewall 394, where the gate oxide layer 391 covers a part of an upper surface of the silicon substrate 31, the gate 392 covers the upper surface of the gate oxide layer 391, the gate low resistance layer 123 covers the upper surface of the gate 392, and the sidewall 124 is located on the upper surface of the silicon substrate 31 and covers sidewalls of the gate oxide layer 391, the gate 392 and the low resistance layer 393.
Further, a lightly doped region 34, a metal silicide region 35, a source region 32, a drain region 33, and a channel region (not shown) between the source region 32 and the drain region 33 are disposed in a top region (i.e., a region adjacent to the upper surface) of the silicon substrate 31; the source region 32 and the drain region 33 are disposed adjacent to the gate stack structure 39 and partially extend below the sidewall 394; the lightly doped region 34 is adjacent to the source region 32 and the drain region 33, is disposed below the sidewall 394, extends to the lower side of the gate oxide 391, and is isolated by the channel region; the metal silicide region 35 is embedded in the lightly doped region 34 and surrounded by the lightly doped region 34 and the source region 35 or the drain region 36, and the metal silicide region 35 is located right under the sidewall 394, and the lightly doped region 34 isolates the metal silicide region 35 from the channel region.
Further, the gate oxide 391 is located right above the channel region (i.e., the metal silicide region 35 is located in the silicon substrate 31 adjacent to the gate 392), and since the metal silicide region 35 is located below the sidewall 394, compared with the conventional MOS structure, the distance between the metal silicide region 35 and the gate 392 is greatly shortened, and thus the surface resistance of the channel region can be effectively reduced.
Further, a contact hole etch stop layer 38 is disposed above the silicon substrate 31 above the drain region 33, and a source metal silicide region 36 is also disposed in the silicon substrate 31 above the drain region 33 for reducing the surface resistance of the source region.
Further, a metal layer 37 is disposed above the source region 32, and the metal layer 37 is partially embedded in the silicon substrate 31, so that the surface resistance of the source region 32 of the MOS device structure can be greatly reduced.
Example four
Fig. 18 is a schematic structural diagram of a structure of a four-MOS device according to an embodiment of the present application; as shown in fig. 18, the method described in the second embodiment can be used to prepare a MOS device structure in this embodiment, where the MOS device structure includes:
an SOI (silicon on insulator) substrate 41 comprising a back substrate 411, a buried oxide layer 412 and a top layer silicon 413, the buried oxide layer 412 overlying the upper surface of the back substrate 411 and the top layer silicon 413 overlying the upper surface of the buried oxide layer 412. A gate stack structure 45 disposed on the top silicon 413, wherein the gate stack structure 45 includes a gate oxide layer 451, a gate electrode 452, a gate metal layer 453 and a sidewall 454, the gate oxide layer 451 covers a portion of the upper surface of the top silicon 413, and the gate electrode 452 covers the upper surface of the gate oxide layer 451; the sidewalls 453 are formed on the top surface of the top silicon 413 to cover the sidewalls of the gate oxide 451 and the gate electrode 452.
Further, the top region (i.e., the region adjacent to the upper surface) of the top layer silicon 413 is further provided with a lightly doped region 42 and a metal silicide region 43; the lightly doped region 42 is disposed adjacent to the gate stack structure 45 under the sidewall 394, extends to a position under the gate oxide 451, and is isolated by a channel region (not shown in the figure, i.e., a region between the lightly doped regions 42 and under the gate oxide 451) of the MOS device; the metal silicide region 43 is embedded in the lightly doped region 42, and the metal silicide region 43 is located right under the sidewall 453, and the lightly doped region 42 isolates the metal silicide region 43 from the channel region.
Further, the gate oxide layer 451 is located right above the channel region (i.e., the metal silicide region 43 is located adjacent to the gate 452 and disposed in the top silicon 413), and since the metal silicide region 43 is located below the sidewall 453, a distance between the metal silicide region 43 and the gate 452 is greatly shortened compared to a conventional MOS structure, so as to effectively reduce a surface resistance of the channel region.
Further, source/drain regions 44 are also disposed in the top silicon layer 44 at two sides of the gate stack structure 45, and the material in the source/drain regions 44 is metal silicide; in addition, an epitaxial layer (not shown, the material may be SiGe, etc.) with a thickness of 10nm to 80nm is formed in the source/drain region 44.
In summary, according to the above technical solution, the method for improving performance of the MOS device and the MOS device structure provided in the present application form the metal silicide region extending to the lower side of the gate sidewall through a metal silicide process, so as to reduce the distance between the metal silicide region and the gate, so as to achieve the purpose of reducing the surface resistance of the device channel, and the drain induced barrier lowering effect (DIBL) and the Short Channel Effect (SCE) of the device can be further reduced by embedding the metal layer in the substrate of the source region or forming the fully metal silicided source region and drain region, so as to improve the performance and yield of the MOS device.
While the specification concludes with claims defining exemplary embodiments of particular structures for practicing the invention, it is believed that other modifications will be made in the spirit of the invention. While the above invention sets forth presently preferred embodiments, these are not intended as limitations.
Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. Therefore, the appended claims should be construed to cover all such variations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims should be considered to be within the intent and scope of the present invention.
Claims (19)
1. A method for improving performance of a MOS device, the method comprising:
step S1, providing a semiconductor substrate, and preparing a gate stack structure on the semiconductor substrate, wherein the gate stack structure comprises a gate oxide layer, a gate electrode positioned on the gate oxide layer and a side wall covering the gate oxide layer and the side wall of the gate electrode, and the side wall has a first thickness;
step S2, performing a light doping process to form light doped regions in the semiconductor substrate on both sides of the gate stack structure, wherein the light doped regions also extend to a partial region at the bottom of the gate; after the light doping process is carried out, carrying out broadening operation on the side wall, wherein the broadening operation comprises the following steps: forming a side wall film on the surface of the side wall, wherein the total thickness of the side wall and the side wall film is a second thickness, and the second thickness is greater than the first thickness;
step S3, after the broadening operation is performed, performing a first metal silicide process to form a first metal silicide region in the lightly doped region, where the first metal silicide region extends to the lower portions of the sidewall and the sidewall film, and the first metal silicide region is isolated from the channel region located below the gate by a portion of the lightly doped region;
after the first metal silicide region is formed in step S4, the source/drain region preparation process is continued.
2. The method of improving performance of a MOS device of claim 1, further comprising:
after the light doping process, a first bag-shaped injection process and a rapid thermal annealing process are firstly carried out to form a light doped region in a region of the semiconductor substrate close to the gate stack structure, and then the widening operation is carried out on the side wall.
3. The method of claim 1, wherein the first metal silicidation process is performed at a temperature of 250 ℃ to 450 ℃ using nickel or platinum.
4. The method of claim 1, wherein the semiconductor substrate is a silicon substrate or a silicon-on-insulator.
5. The method of claim 4, wherein the silicon substrate has a crystal orientation of <110> or <100 >.
6. The method for improving the performance of the MOS device according to claim 4, wherein when the semiconductor substrate is a silicon substrate, the source/drain region preparation process comprises:
performing source/drain ion implantation to form a source region and a drain region in the semiconductor substrate on the two sides of the grid, the side wall and the side wall film respectively;
performing a second metal silicification process to form a second metal silicide layer surrounded by the source region and the drain region in the top regions of the source region and the drain region respectively;
after the second metal silicification process is carried out, a through hole etching stop layer is prepared;
etching the through hole etching stop layer positioned on the source region and the silicon substrate positioned in the source region, reserving a first metal silicide region positioned below the side wall and the side wall film, and forming a source region groove in the source region on one side of the gate, the side wall and the side wall film and in the through hole etching stop layer;
and preparing a metal layer to fill the source region groove.
7. The method of claim 6, wherein the silicon substrate in the source region is etched using an isotropic etching process.
8. The method of claim 6, wherein the second metal silicidation process is performed at a temperature of 250 ℃ to 450 ℃ using nickel or platinum.
9. The method of claim 4, wherein when the semiconductor substrate is silicon-on-insulator, the source/drain region preparation process comprises:
etching the silicon on the insulator, and reserving the first metal silicide regions positioned below the side wall and the side wall film so as to respectively form a source region groove and a drain region groove in the semiconductor substrate at two sides of the grid electrode, the side wall and the side wall film;
preparing an epitaxial layer to fill the source region groove and the drain region groove so as to form a source region and a drain region;
and carrying out a third metal silicidation process on the epitaxial layer so as to convert the epitaxial layer in the source region and the drain region into a third metal silicide region.
10. The method of claim 9, wherein the third metal silicidation process is performed at a temperature of 250 ℃ to 450 ℃ using nickel or platinum.
11. The method of claim 9, wherein the epitaxial layer has a thickness of 10nm to 80 nm.
12. The method of improving performance of a MOS device of claim 9, further comprising:
and after the epitaxial layer is prepared, carrying out a second bag-shaped injection process on the epitaxial layer to form the source region and the drain region.
13. The method of claim 12 wherein the second pocket implant process has an ion implant dose of 5e12/cm2～2e13/cm2。
14. A MOS device structure prepared by the method of any of claims 1-13, the MOS device structure comprising:
a semiconductor substrate;
the gate stack structure is positioned on the semiconductor substrate and comprises a gate oxide layer, a gate positioned on the gate oxide layer and a side wall covering the side walls of the gate oxide layer and the gate;
the lightly doped regions are respectively positioned in the semiconductor substrate at two sides of the gate stack structure and also extend to partial regions at the bottom of the gate;
the side wall film is positioned on the surface of the side wall;
and the first metal silicide region is positioned at the bottom of the side wall and the side wall film, and the first metal silicide region is isolated from the channel region positioned below the grid electrode by a part of lightly doped region.
15. The MOS device structure of claim 14, wherein the semiconductor substrate is a silicon substrate or a silicon-on-insulator.
16. The MOS device structure of claim 15, wherein the silicon substrate has a crystal orientation of <110> or <100 >.
17. The MOS device structure of claim 15, wherein the source region and the drain region are located in the semiconductor substrate on two sides of the gate, the sidewall, and the sidewall film, respectively.
18. The MOS device structure of claim 17, wherein when the semiconductor substrate is a silicon substrate, the MOS device structure further comprises: the metal layer is arranged in the source region and on the source region, and a first metal silicide region is arranged between the metal layer and the channel below the grid and is positioned below the side wall and the side wall film; and a second metal silicide layer located in a top region of the drain region and surrounded by the drain region.
19. The MOS device structure of claim 17, wherein when the semiconductor substrate is silicon-on-insulator, the source region and the drain region are both made of metal silicide.
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