CN113271064A - Three-dimensional integrated low-phase-noise voltage-controlled oscillator - Google Patents
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Abstract
The invention discloses a three-dimensional integrated low-phase-noise voltage-controlled oscillator, which comprises a power supply, wherein the power supply is connected with sources and substrates of M1 and M1, a gate of the M1 is connected with an output end of Lv1 and an input end of C1, a gate of the M1 is connected with an output end of the Lv1 and an input end of the C1, Vbias is connected with input ends of the Lv1 and the Lv1, a drain of the M1 is connected with input ends of the L1 and the R1, an output end of the L1 is connected with an output end of the R1, output ends of the R1 are connected with output ends of the C1 and the Cv1, an input end of the Lv1 and Vout1, Vctr1 is connected with the input ends of the Cv1 and the Cv1, and an output end of the Lv1 are connected with a ground end of the Lv1 and the output end of the Lv 1. The invention has the advantages of small chip area, low phase noise and the like.
Description
Technical Field
The invention belongs to the technical field of three-dimensional integrated circuits, and relates to a three-dimensional integrated low-phase-noise voltage-controlled oscillator.
Background
Voltage Controlled Oscillators (VCOs) are important in radio frequency circuits, especially in phase locked loop circuits, clock recovery circuits, frequency synthesizer circuits, etc., where the oscillation frequency can be adjusted by a control voltage. The phase noise directly affects the stability of the output frequency, and the inductance and capacitance frequency modulation oscillator are the only reliable implementation method, but the inductance and the capacitance occupy larger chip area.
As microelectronic technology develops, microelectronic devices continue to decrease in size according to moore's law, and the integration level of integrated circuits also gradually increases. The current voltage-controlled oscillator is difficult to meet the requirements of high integration level and excellent performance in the future.
Disclosure of Invention
The invention aims to provide a three-dimensional integrated low-phase-noise voltage-controlled oscillator, which solves the problem of high-phase noise in a voltage-controlled oscillator circuit in the prior art.
The invention adopts the technical scheme that the three-dimensional integrated low-phase-noise voltage-controlled oscillator comprises a power supply VDD, wherein the power supply VDD is connected with a source electrode and a substrate of a TSV vertical switch M1 and a source electrode and a substrate of a TSV vertical switch M2, a grid electrode of the TSV vertical switch M1 is connected with an output end of a Wheatstone inductance bridge Lv1 and an input end of a TSV capacitor tube C2, a grid electrode of a TSV vertical switch M2 is connected with an output end of the Wheatstone inductance bridge Lv2 and an input end of a TSV capacitor tube C1, a reference voltage Vbias is connected with an input end of the Wheatstone inductance bridge Lv1 and an input end of the Wheatstone inductance bridge Lv2, a drain electrode of the TSV vertical switch M1 is connected with an input end of a TSV inductance L1, an output end of the inductance TSV L1 is connected with an input end of a resistor R1, an output end of a resistor R1 is connected with an output end of the TSV capacitor tube C1, an output end of a TSV capacitor tube C1, an output end of a TSV varactor Cv1, an output end of a Wheatstone capacitor Cv 3, the drain electrode of the TSV vertical switch M2 is connected with the input end of a TSV inductor L2, the output end of a TSV inductor L2 is connected with the input end of a resistor R2, the output end of the resistor R2 is connected with the output end of a TSV capacitor C2, the output end of a TSV varactor Cv2, the input end of a Wheatstone inductor bridge Lv4 and the output end of a circuit Vout2, a varactor control power supply Vctr1 is connected with the input end of the TSV varactor Cv1 and the input end of the TSV varactor Cv2, and the ground end GND is connected with the output end of the Wheatstone inductor bridge Lv3 and the output end of the Wheatstone inductor bridge Lv 4.
The invention is also characterized in that:
the TSV vertical switch M1 comprises an N-type silicon substrate (4), a vertical TSV copper column (1) is arranged in the N-type silicon substrate (4), a dielectric layer (2) is arranged on the outer side of the TSV copper column (1), p + doping regions (7) are arranged on the outer sides of the dielectric layers (2) at the upper end and the lower end of the N-type silicon substrate (4), heavy wiring layers (3) are arranged on the outer side surfaces of the p + doping regions (7), silicon dioxide layers (6) are arranged on the upper end surface and the lower end surface of the TSV vertical switch M1 except the heavy wiring layers (3), a source electrode S and a drain electrode D which are used as MOS are respectively led out of the upper heavy wiring layer and the lower heavy wiring layer (3), and a grid electrode G which is used as MOS is led out of the top end of the TSV copper column (1).
The TSV inductors L1, L2, L3, L4, L5, and L6 are each formed by 2N TSV inductor copper pillars.
The TSV capacitor tube C1 comprises a P-type silicon substrate (5), a semi-through hole TSV copper column (1) is arranged on the P-type silicon substrate (5), a dielectric layer (2) is arranged on the outer side of the semi-through hole TSV copper column (1), a metal layer (8) is arranged on the outer side of the dielectric layer (2), a rewiring layer (3) is arranged on the outer side surfaces of the metal layer (8) and the P-type silicon substrate (5), the metal layer (8) is led out through the rewiring layer (3) on the surface of the P-type silicon substrate (5) to serve as an output end of the TSV capacitor tube C1, silicon dioxide layers (6) are arranged on the upper end surface and the lower end surface of the TSV capacitor tube C1 except the rewiring layer (3), and an input end of the TSV capacitor tube C1 is led out from the top end of the semi-through hole TSV copper column (1).
The TSV varactor Cv1 comprises a P-type silicon substrate (5), the P-type silicon substrate (5) is provided with a vertical TSV copper column (1), a grid G serving as an MOS is led out from the top end of the TSV copper column (1), a dielectric layer (2) is arranged on the outer side of the TSV copper column (1), P + doped regions (7) are arranged on the outer sides of the dielectric layers (2) at the upper end and the lower end of the P-type silicon substrate (5), heavy wiring layers (3) are arranged on the outer side surfaces of the P + doped regions (7), a source electrode S and a drain electrode D serving as the MOS are respectively led out from the upper heavy wiring layer and the lower heavy wiring layer (3), the source electrode S and the drain electrode D are connected to serve as the output end of the TSV varactor Cv wiring layer 1, silicon dioxide layers (6) are arranged on the upper end surface and the lower end surface of the TSV varactor C1 outside the heavy wiring layers (3), and the grid G of the MOS serves as the input end of the TSV varactor.
The Wheatstone inductor bridges Lv1, Lv2, Lv3 and Lv4 are all composed of 4N +2 TSV inductor copper columns and 1 TSV vertical switch.
The invention has the beneficial effects that: the phase noise of the voltage-controlled oscillator is improved by adding an Lc bias circuit as an impedance transformation network into a circuit and transmitting higher frequency to a grid of an MOS cross coupling pair; and adding resistance and inductance to the drain of the MOS to enhance-Gm; inductors (L1, L2), Wheatstone inductor bridges (Lv1, Lv2, Lv3, Lv4), MOS transistors (M1, M2), capacitor tubes (C1, C2) and varactors (Cv1, Cv2) all adopt TSV three-dimensional structures, the chip area and the cost are reduced, the integration level is improved, the TSV inductors have better quality factors under lower frequency (such as below 20 GHz), compared with planar varactors, the TSV varactors have higher performance under the same area, the performance size can be adjusted by changing the height and the diameter of the TSV, and the depth and the width of a source drain region are changed to adjust the tuning range size; the Wheatstone inductive bridge has larger adjustable range, smaller area and higher quality factor,
compared with the traditional voltage-controlled oscillator, the invention has the advantages of small chip area, low phase noise, low power consumption under low voltage, larger output curve amplitude and the like.
Drawings
Fig. 1 is a circuit diagram of a three-dimensional integrated low phase noise voltage controlled oscillator of the present invention;
FIG. 2 is a schematic structural diagram of a TSV vertical switch in a three-dimensional integrated low-phase-noise voltage-controlled oscillator according to the present invention;
FIG. 3 is a top view of a TSV inductor in the three-dimensional integrated low phase noise voltage controlled oscillator of the present invention;
FIG. 4 is a schematic structural diagram of a TSV capacitor in a three-dimensional integrated low-phase-noise voltage-controlled oscillator according to the present invention;
FIG. 5 is a schematic structural diagram of a TSV varactor in a three-dimensional integrated low phase noise voltage-controlled oscillator according to the present invention;
fig. 6 is a schematic diagram of a wheatstone inductor bridge in a three-dimensional integrated low phase noise voltage-controlled oscillator according to the present invention.
In the figure, 1, a TSV copper column, 2, a dielectric layer, 3, a rewiring layer, 4, an N-type silicon substrate, 5, a P-type silicon substrate, 6, a silicon dioxide layer, 7, a P + doped region and 8, a metal layer.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
The invention discloses a three-dimensional integrated low-phase-noise voltage-controlled oscillator, which comprises two TSV vertical switches M1 and M2 of P-type MOS, two inductors L1 and L2, four Wheatstone inductor bridges Lv1, Lv2, Lv3 and Lv4, two TSV capacitors C1 and C2, two TSV varactors Cv1 and Cv2, two resistors R1 and R2, a power supply VDD, a ground terminal GND, a varactor control power supply Vctr1, a reference power supply Vbias, circuit output ports Vout1 and Vout2, wherein the TSV vertical switches M1 and M2 are connected with the two inductors; a power supply VDD is connected to a source S1 and a substrate B1 of the TSV vertical switch M1 and a source S2 and a substrate B2 of the TSV vertical switch M2, a gate of the TSV vertical switch M1 is connected to an output OUT1 of the wheatstone inductive bridge Lv1 and an input Cin2 of the TSV capacitor C2, a gate of the TSV vertical switch M2 is connected to an output OUT2 of the wheatstone inductive bridge Lv2 and an input Cin1 of the TSV capacitor C1, a reference voltage Vbias is connected to an input IN1 of the wheatstone inductive bridge Lv1 and an input IN2 of the wheatstone inductive bridge Lv2, a drain of the TSV vertical switch M1 is connected to an input Lin1 of the TSV inductor L1, an output Lout1 of the TSV inductor L1 is connected to an input Rin1 of a resistor R1, an output Rout1 of the resistor R1 is connected to an output of the capacitor C36c 1, an output terminal of the TSV inductor Vout1 of the TSV vertical switch M1, a drain of the TSV vertical switch M1, a TSV varactor switch C1, a drain of the TSV inductor Vout1, a TSV varactor switch C1, and an output terminal Vout of the TSV varactor C1, an output end Lout2 of the TSV inductor L2 is connected with an input end Rin2 of a resistor R2, an output end Rout2 of the resistor R2 is connected with an output end Cout2 of a TSV capacitor C2, an output end Cvout2 of a TSV varactor Cv2, an input end IN4 of a wheatstone inductor bridge Lv4 and a circuit output signal Vout2, a varactor control voltage Vctr1 is connected with an input end Cvin1 of the TSV varactor Cv1 and an input end Cvin2 of the TSV varactor Cv2, and a ground end GND is connected with an output end OUT3 of the wheatstone inductor Lv3 and an output end OUT4 of the wheatstone inductor bridge 4;
as shown in fig. 2, the TSV vertical switch M1 includes an N-type silicon substrate 4, a vertical TSV copper pillar 1 is disposed in the N-type silicon substrate 4, a dielectric layer 2 is disposed on the outer side of the TSV copper pillar 1, p + doped regions 7 are disposed on the outer sides of the dielectric layers 2 at the upper and lower ends of the N-type silicon substrate 4, a redistribution layer 3 is disposed on the outer side surface of the p + doped region 7, a silicon dioxide layer 6 is disposed on the upper and lower end surfaces of the TSV vertical switch M1 outside the redistribution layer 3, the upper and lower redistribution layers 3 are respectively led out as a source S and a drain D of an MOS, and a gate G of the MOS is led out from the top end of the TSV copper pillar 1; the TSV vertical switch M2 has the same structure as the TSV vertical switch M1; the TSV vertical switches (M3, M4, M5, M6) in the Wheatstone inductor bridge have the same structure as the TSV vertical switch M1.
As shown in fig. 3, the TSV inductors L1, L2, L3, L4, L5, and L6 are each composed of 2N TSV inductor copper pillars; the size of the TSV inductor can be controlled by changing N, where N is 3, that is, 6 TSV inductor copper pillars are taken as an example, a TSV inductor input end Lin is connected to an a1 end of a TSV inductor copper pillar I1, a b1 end of a TSV inductor copper pillar I1 is connected to a b2 end of the TSV inductor copper pillar I2, an a2 end of a TSV inductor copper pillar I2 is connected to an a3 end of the TSV inductor copper pillar I3, a b3 end of the TSV inductor copper pillar I3 is connected to a b4 end of the TSV inductor copper pillar I4, an a4 end of the TSV inductor copper pillar I4 is connected to an a5 end of the TSV inductor copper pillar I5, a b5 end of the TSV inductor copper pillar I5 is connected to a6 end of the inductor copper pillar I6, and a6 end of the TSV inductor copper pillar I6 is connected to a Lout of the TSV inductor copper pillar I6;
as shown in fig. 4, the TSV capacitor C1 includes a P-type silicon substrate 5, a half-through TSV copper pillar 1 is disposed on the P-type silicon substrate 5, a dielectric layer 2 is disposed on the outer side of the half-through TSV copper pillar 1, a metal layer 8 is disposed on the outer side of the dielectric layer 2, a redistribution layer 3 is disposed on the outer side surfaces of the metal layer 8 and the P-type silicon substrate 5, the metal layer 8 is led out through the redistribution layer 3 on the surface of the P-type silicon substrate 5 to serve as an output Cout1 of the TSV capacitor C1, silicon dioxide layers 6 are disposed on the upper and lower end surfaces of the TSV capacitor C1 outside the redistribution layer 3, and an input end of the TSV capacitor C1 is led out from the top end of the half-through TSV copper pillar 1; c2 is structurally identical to C1;
as shown in fig. 5, the TSV varactor Cv1 includes a P-type silicon substrate 5, the P-type silicon substrate 5 is provided with a vertical TSV copper pillar 1, a gate G serving as an MOS is led out from the top end of the TSV copper pillar 1, a dielectric layer 2 is arranged on the outer side of the TSV copper pillar 1, P + doped regions 7 are arranged on the outer sides of the dielectric layers 2 at the upper and lower ends of the P-type silicon substrate 5, a heavy wiring layer 3 is arranged on the outer side surface of each P + doped region 7, a source S and a drain D serving as MOS are led out from the upper and lower heavy wiring layers 3, respectively, the source S and the drain D are connected to serve as an output end of a TSV varactor Cv1, silicon dioxide layers 6 are arranged on the upper and lower end surfaces of a TSV varactor C1 outside the heavy wiring layer 3, and the gate G of the MOS is used as an input end of the TSV varactor;
as shown in fig. 6, each of the wheatstone inductor bridges Lv1, Lv2, Lv3 and Lv4 is composed of (4N +2) TSV inductor copper pillars and 1 TSV vertical switch; the size of the TSV inductor can be controlled by changing N, where N is 4, i.e., 18 TSV inductor copper pillars are taken as an example. An input end IN of the wheatstone inductor bridge is connected with an end a17 of the TSV inductor copper pillar D17 and an end a1 of the TSV inductor copper pillar D1, an end b1 of the TSV inductor copper pillar D1 is connected with an end b2 of the TSV inductor copper pillar D2, an end a2 of the TSV inductor copper pillar D2 is connected with an end a3 of the TSV inductor copper pillar D3, an end b3 of the TSV inductor copper pillar D3 is connected with an end b4 of the TSV inductor copper pillar D4, an end a4 of the TSV inductor copper pillar D4 is connected with an end a4 of the second non-TSV inductor copper pillar D4 and a source S of the TSV vertical switch M4, an end b4 of the TSV inductor copper pillar D4 is connected with an end b4 of the inductor copper pillar D4, an end a4 of the inductor copper pillar D4 is connected with an end a4 of the TSV inductor copper pillar D4, an end b4 of the inductor copper pillar D4 is connected with an end b4 of the inductor copper pillar D4, an inductor copper pillar D4 is connected with an end b4 of the inductor copper pillar D4, an inductor end b4 of the TSV inductor copper pillar D4, an inductor end b4 is connected with an inductor end b4 of the TSV inductor copper pillar D4, the a9 end of the TSV inductance copper pillar D9 is connected with the a9 end of the TSV inductance copper pillar D9, the b9 end of the TSV inductance copper pillar D9 is connected with the b9 end of the TSV inductance copper pillar D9, the a9 end of the TSV inductance copper pillar D9 is connected with the a9 end of the TSV inductance copper pillar D9, the b9 end of the TSV inductance copper pillar D9 is connected with the b9 end of the TSV inductance copper pillar D9 and the drain D of the TSV vertical switch M9, the a9 end of the TSV inductance copper pillar D9 is connected with the a9 end of the TSV inductance copper pillar D9, the b9 end of the TSV inductance copper pillar D9 is connected with the b9 end of the TSV inductance copper pillar D9, the a9 end of the TSV inductance copper pillar D9 is connected with the a9 end of the TSV inductance copper pillar D9;
the total inductance of a Wheatstone inductance bridge in the three-dimensional integrated low-phase-noise voltage-controlled oscillator is divided into the following two types:
(1) when the inductance control power supply is smaller than the threshold voltage of the TSV vertical switch, the TSV vertical switch is turned off, and the total inductance value Ltot1 of the Wheatstone inductance bridge is as follows:
Ltot1＝[(L0-ΔL)+(L0+ΔL)]||[(L0+ΔL)+(L0-ΔL)]＝L0
i.e., the equivalent inductance value L from the input terminal in1 to the output terminal out1 of the Wheatstone inductor bridge0。
In the above formula (L)0-. DELTA.L) equivalent to the inductance of the series connection of the TSV inductances D1, D2, D3, D4 and the inductance of the series connection of the TSV inductances D9, D10, D11, D12 (L)0And a) equivalent to the inductance of the series connection of TSV inductors D5, D6, D7, D8 and D18 and the inductance of the series connection of TSV inductors D13, D14, D15, D16 and D17.
(2) When the inductance control power supply is greater than the threshold voltage of the TSV vertical switch, the TSV vertical switch is turned on, and the total inductance value Ltot2 of the wheatstone inductance bridge is:
a Wheatstone inductance bridge (Lv1/Lv2/Lv3/Lv4) adopted by the voltage-controlled oscillator adjusts the total inductance value of an inductance circuit through the on/off of a TSV vertical switch (M3/M4/M5/M6), and the frequency adjustment of the voltage-controlled oscillator is realized by matching with TSV varactors Cv1 and Cv2, wherein the inductance control power supply is respectively (V1/V2/V3/V4).
Compared with the traditional voltage-controlled oscillator, the three-dimensional integrated low-phase-noise voltage-controlled oscillator has the advantages of small chip area, low phase noise, low power consumption under low voltage, large output curve amplitude and the like.
Claims (6)
1. A three-dimensional integrated low-phase-noise voltage-controlled oscillator is characterized by comprising a power supply VDD, wherein the power supply VDD is connected with a source electrode and a substrate of a TSV vertical switch M1 and a source electrode and a substrate of a TSV vertical switch M2, a grid electrode of the TSV vertical switch M1 is connected with an output end of a Wheatstone inductance bridge Lv1 and an input end of a TSV capacitor tube C2, a grid electrode of a TSV vertical switch M2 is connected with an output end of the Wheatstone inductance bridge Lv2 and an input end of a TSV capacitor tube C1, a reference voltage Vbias is connected with an input end of the Wheatstone inductance bridge Lv1 and an input end of the Wheatstone inductance bridge Lv2, a drain electrode of the TSV vertical switch M1 is connected with an input end of a TSV inductance L1, an output end of the TSV inductance L1 is connected with an input end of a resistor R1, an output end of a resistor R1 is connected with an output end of a C1, an output end of a TSV varactor 1, an output end of the TSV capacitor tube C6857, an output end of the TSV varactor bridge Lv1, an input end of the Wheatstone inductance L3 and an output end of a circuit 1, the drain electrode of the TSV vertical switch M2 is connected with the input end of a TSV inductor L2, the output end of a TSV inductor L2 is connected with the input end of a resistor R2, the output end of the resistor R2 is connected with the output end of a TSV capacitor C2, the output end of a TSV varactor Cv2, the input end of a Wheatstone inductor bridge Lv4 and the output end of a circuit Vout2, a varactor control power supply Vctr1 is connected with the input end of the TSV varactor Cv1 and the input end of the TSV varactor Cv2, and the ground end GND is connected with the output end of the Wheatstone inductor bridge Lv3 and the output end of the Wheatstone inductor bridge Lv 4.
2. The three-dimensional integrated low-phase-noise voltage-controlled oscillator according to claim 1, wherein the TSV vertical switch M1 comprises an N-type silicon substrate (4), a vertical TSV copper pillar (1) is arranged in the N-type silicon substrate (4), a dielectric layer (2) is arranged outside the TSV copper pillar (1), p + doped regions (7) are arranged outside the dielectric layers (2) at the upper end and the lower end of the N-type silicon substrate (4), a rewiring layer (3) is arranged on the outer side surface of the p + doped region (7), a silicon dioxide layer (6) is arranged on the upper end face and the lower end face of the TSV vertical switch M1 except the rewiring layer (3), a source electrode S and a drain electrode D which are MOS are respectively led out from the upper rewiring layer and the lower rewiring layer (3), and a gate electrode G which is MOS is led out from the top end of the TSV copper pillar (1).
3. The three-dimensional integrated low-phase-noise voltage-controlled oscillator as claimed in claim 1, wherein the TSV inductors L1, L2, L3, L4, L5 and L6 are all formed by 2N TSV inductor copper pillars.
4. The three-dimensional integrated low-phase-noise voltage-controlled oscillator according to claim 1, wherein the TSV capacitor C1 comprises a P-type silicon substrate (5), a semi-through TSV copper column (1) is arranged on the P-type silicon substrate (5), a dielectric layer (2) is arranged on the outer side of the semi-through TSV copper column (1), a metal layer (8) is arranged on the outer side of the dielectric layer (2), a rewiring layer (3) is arranged on the outer side surfaces of the metal layer (8) and the P-type silicon substrate (5), the metal layer (8) is led out through the rewiring layer (3) on the surface of the P-type silicon substrate (5) to serve as an output end of the TSV capacitor C1, silicon dioxide layers (6) are arranged on the upper end face and the lower end face of the TSV capacitor C1 outside the rewiring layer (3), and an input end of the TSV capacitor C1 is led out of the top end of the semi-through TSV copper column (1).
5. The three-dimensional integrated low phase noise voltage controlled oscillator of claim 1, the TSV varactor Cv1 comprises a P-type silicon substrate (5), the P-type silicon substrate (5) is provided with a vertical TSV copper column (1), a grid G serving as an MOS is led out from the top end of the TSV copper column (1), a dielectric layer (2) is arranged on the outer side of the TSV copper column (1), the outer sides of the dielectric layers (2) at the upper end and the lower end of the P-type silicon substrate (5) are respectively provided with a P + doped region (7), the outer side face of the p + doped region (7) is provided with a rewiring layer (3), a source electrode S and a drain electrode D which are used as MOS are respectively led out from the upper rewiring layer (3) and the lower rewiring layer (3), the source electrode S and the drain electrode D are connected to be used as the output end of the TSV varactor Cv1, the upper end face and the lower end face of the TSV varactor C1 outside the rewiring layer (3) are provided with silicon dioxide layers (6), and a grid G of the MOS is used as the input end of the TSV varactor.
6. The three-dimensional integrated low-phase-noise voltage-controlled oscillator according to claim 1, wherein the Wheatstone inductor bridges Lv1, Lv2, Lv3 and Lv4 are each composed of 4N +2 TSV inductor copper pillars and 1 TSV vertical switch.
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