CN113269743B - Chip quantity detection method based on iterative translation verification - Google Patents
Chip quantity detection method based on iterative translation verification Download PDFInfo
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Abstract
The invention provides a chip quantity detection method based on iterative translation verification, which comprises the steps of obtaining a chip template image from a wafer image, determining the position of the chip template on a wafer, and further determining the position of a chip on the chip template by utilizing a contour searching algorithm; determining the position of the chip on the wafer based on the position of the chip template on the wafer; numbering each chip on the chip template using an algorithm to obtain a verified chip at a determined position and number on the template; then, the verified chips are used for iterative translation, so that the chips to be verified with the determined positions but with the undetermined numbers are verified, and the number of the chips with each type of numbers is finally obtained; the method and the device realize the quantity statistics of different types of chips on the wafer, solve the problem that the continuous translation verification error of a group of verified chips is large due to the distortion of the wafer image, and improve the accuracy of quantity detection.
Description
Technical Field
The invention relates to the technical field of machine vision, in particular to a chip quantity detection method based on iterative translation verification.
Background
For a wafer, the chips on the wafer are periodically arranged by a chip template, and the chip template is a set of one or more chips consisting of one or more chips.
The current machine vision is applied to chip quantity detection, and the quantity of all chips is detected simply through contour detection, so that the method is only suitable for the condition that only one chip exists on one wafer, and for the condition that multiple chips exist on one wafer, the current detection technology cannot detect the quantity of various chips respectively.
Disclosure of Invention
In view of the above, it is necessary to provide a chip number detection method based on iterative translation verification to solve the above technical problems.
A chip quantity detection method based on iterative translation verification, the method comprising: collecting a wafer image, and cutting a chip template from the wafer image to obtain a chip template image; determining the position of each chip on the wafer on the chip template; numbering each chip on the chip template in sequence by using an algorithm to obtain the number of each chip; the chips are divided into verified chips and chips to be verified, the chips with determined positions and numbers are defined as the verified chips, and the chips with the determined positions and undetermined numbers are defined as the chips to be verified; carrying out binarization processing on the wafer image, finding out all contours on the wafer according to a contour searching algorithm to obtain the position of each contour on the wafer, wherein each contour corresponds to one chip so as to obtain the position of each chip on the wafer; determining the numbers of all the chips to be verified on the wafer through the iterative translation verification of the verified chips, thereby determining the number of each type of chips; arranging the verified chips in sequence according to sizes from large to small; sequentially translating the central points of the arrayed verified chips up and down, left and right for a preset unit length; the outline range in the chip to be verified comprises the translated central point, and the verified chip corresponding to the central point belongs to the same number and becomes a new verified chip; translating the central point of the newly verified chip up and down, left and right to preset unit length, and sequentially iterating and translating to obtain the serial numbers of all chips to be verified; thereby determining the number of types of chips.
In one embodiment, the determining the position of each chip on the wafer on the chip template specifically includes: matching a chip template on the wafer image by adopting a template matching algorithm based on the chip template image so as to obtain the position of the chip template on the wafer; carrying out binarization processing on the chip template, determining the outline on the chip template by searching an outline algorithm to obtain the position of each outline on the chip template, wherein each outline corresponds to one chip, so as to obtain the position of each chip on the chip template; and obtaining the position of each chip on the wafer according to the position of the chip template on the wafer and the position of each chip on the chip template.
In one embodiment, after the step of sequentially translating the center points of the arranged verified chips up, down, left, and right by a preset unit length, the method further includes: defining all chips to be verified as initial chips to be verified; taking the chip to be verified of which the outline range comprises the translated central point in the chip to be verified as a target chip to be verified; judging whether the difference between the areas of the target chip to be verified and the verified chip is larger than a preset value or not; if the number of the target chip to be verified and the number of the verified chip corresponding to the central point are smaller than the preset value, the target chip to be verified and the verified chip corresponding to the central point belong to the same number, and the target chip to be verified and the verified chip corresponding to the central point are changed into a new verified chip.
In one embodiment, after the step of determining whether the difference between the areas of the target chip to be verified and the verified chip is greater than a preset value, the method further includes: if the current value is larger than the preset value, redefining the target chip to be verified as the initial chip to be verified.
In one embodiment, before the step of sequentially translating the center points of the arranged verified chips up, down, left, and right by a preset unit length, the method further includes: and expanding the area of the chip to be verified, which is smaller than the preset size standard, according to the preset size standard.
According to the chip quantity detection method based on iterative translation verification, the position of the chip template on the wafer is determined by obtaining the chip template image from the wafer image, and the position of the chip on the chip template is further determined by utilizing a contour searching algorithm; determining the position of the chip on the wafer based on the position of the chip template on the wafer; numbering each chip on the chip template using an algorithm to obtain a verified chip at a determined position and number on the template; then, the verified chips are used for iterative translation, so that the chips to be verified with the determined positions but with the undetermined numbers are verified, and the number of the chips with each type of numbers is finally obtained; the method and the device realize the statistics of the number of different types of chips on the wafer, solve the problem that the continuous translation verification error of a group of verified chips is large because the wafer image has distortion, and improve the accuracy of number detection.
Drawings
FIG. 1 is a flow diagram illustrating chip quantity detection based on iterative translation verification, according to one embodiment;
FIG. 2 is an embodiment iterative translation verification diagram;
FIG. 3 is a schematic view of a wafer in one embodiment;
FIG. 4 is a schematic diagram of a die template of the wafer shown in FIG. 3;
FIG. 5 is a diagram illustrating the detection results of chip No. 0 in the wafer shown in FIG. 3;
FIG. 6 is a schematic diagram illustrating the inspection result of chip number 44 in the wafer shown in FIG. 3;
fig. 7 is a statistical chart of the number of various chip tests in the wafer shown in fig. 3.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail by the following detailed description in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The chip quantity detection method based on iterative translation verification can be used for counting the quantity of each type of chip on a wafer.
In one embodiment, as shown in fig. 1, there is provided a chip number detection method based on iterative translation verification, including the following steps:
s110, collecting a wafer image, cutting out a chip template from the wafer image, and obtaining a chip template image.
Specifically, as shown in fig. 3-4, a wafer image is collected, and a chip template is cut out from the wafer image to obtain a chip template image.
S120 determines a position of each chip on the wafer on the chip template.
Specifically, a chip template can be matched on a wafer image through a template matching algorithm, so that the position of the chip template on a wafer is obtained; the method comprises the steps of performing binarization processing on a chip template, determining a contour on the chip template by searching a contour algorithm, wherein the contour corresponds to a chip, and thus obtaining the position of the chip on the chip template; and obtaining the position of the chip on the wafer based on the position of the chip template on the wafer and the position of the chip on the chip template.
In one embodiment, step S120 specifically includes: matching the chip template on the wafer image by adopting a template matching algorithm based on the chip template image so as to obtain the position of the chip template on the wafer; carrying out binarization processing on the chip template, determining the outline on the chip template by searching an outline algorithm to obtain the position of each outline on the chip template, wherein each outline corresponds to one chip, so as to obtain the position of each chip on the chip template; and obtaining the position of each chip on the wafer according to the position of the chip template on the wafer and the position of each chip on the chip template. Specifically, by using a template matching algorithm, a chip template image is used as a template, and the chip template is matched on a wafer image, so that the position of the chip template on a wafer can be obtained; the binarization processing is carried out on the chip template by using a binarization algorithm, and then all contours on the chip template are found out by using a contour searching algorithm, so that the position of each contour on the chip template can be obtained. And combining the detection results to obtain the position of each chip on the wafer on the chip template.
S130, numbering each chip on the chip template in sequence by using an algorithm to obtain the number of each chip.
Specifically, the chips on the chip template are automatically numbered from left to right and from top to bottom by using an algorithm, so that the number of each chip on the chip template is obtained.
The chips are divided into verified chips and chips to be verified, the chips with determined positions and numbers are defined as verified chips, and the chips with the determined positions and undetermined numbers are defined as chips to be verified.
Specifically, the chip whose position and number are determined is referred to as a verified chip, and the chip whose position is determined without the number is referred to as a chip to be verified.
S150, carrying out binarization processing on the wafer image, finding out all contours on the wafer according to a contour searching algorithm, and obtaining the position of each contour on the wafer, wherein each contour corresponds to one chip, so that the position of each chip on the wafer is obtained.
Specifically, the wafer image is binarized by using a binarization algorithm, and then all contours on the wafer are found by using a contour searching algorithm, so that the position of each contour on the wafer can be obtained.
S160 determines the numbers of all chips to be verified on the wafer through the verified chip iterative translation verification, thereby determining the number of each type of chip.
Specifically, the chips to be verified are found in the left, right, up and down directions respectively by translating the verified chips in the left, right, up and down directions according to the preset unit length, the newly verified chips are used as the verified chips of the second round for translation in the second round, and the verified chips of the first round do not participate any more, so that the number of all the various chips can be found.
In one embodiment, step S160 specifically includes: arranging the verified chips in sequence according to sizes from large to small; sequentially translating the central points of the arrayed verified chips up and down, left and right for a preset unit length; the verified chips corresponding to the center point and the contour range of the center point after translation in the chip to be verified belong to the same number and become new verified chips; translating the central point of the newly verified chip up and down, left and right to preset unit length, and sequentially iterating and translating to obtain the serial numbers of all chips to be verified; thereby determining the number of types of chips. Specifically, the verified chips are sorted according to size from large to small; secondly, respectively translating the center point of the 1 st verified chip to the upper part, the lower part, the left part and the right part for a preset unit length, wherein the preset unit length is 1 to M unit lengths (the unit length is the height of the chip template when the chip template is translated up and down; the unit length is the width of the chip template when the chip template is translated left and right), because the wafer image has distortion, M is not suitable to be too large and is generally not more than 3, M is a positive integer, if the center points are just in the range of some chips to be verified, the chips to be verified and the verified chips are considered to be the same number, the newly verified chips are used for the second round of translation verification, and the chips which are verified before are not used for the next round of translation verification, namely iteration translation verification; thirdly, repeating the steps of front left-right up-down translation for the rest verified chips to finish the first round of translation verification; and repeating the steps for the newly verified chips to complete the 2 nd round, the 3 rd round, … … th round and the Nth round of translation verification until the number of the newly verified chips is 0, finally obtaining the numbers of all the chips on the wafer, and further counting the number of the chips of each number.
In one embodiment, as shown in fig. 2, the chip with the black frame and the letter is a new verified chip, the chip with the letter only is a verified chip, and the chip without the black frame and the letter is a chip to be verified. A. B, C, D are four types of verified chips, the type D chip has the largest area, and the areas are from large to small: D. c, B, A are provided. In fig. 2, the preset unit length is set to be 1 unit length, and the verified four chips are A, B, C, D four types of chips respectively. Firstly, carrying out a first round of translation based on verified chips, sorting according to the area size, wherein D > C > B > A, therefore, firstly translating the verified chips of the D type, translating the chips of the D type by 1 unit length left and right, up and down, correspondingly identifying new verified chips of the D type, namely the D type chips with frames in the drawing, then carrying out translation of the verified chips of the C type, sequentially carrying out translation, finally obtaining the result after the first round of translation, and correspondingly verifying 16 chips to be verified to form the new verified chips after the first round of translation; the 16 new verified chips were used as verified chips in the second round of translation, and similarly, the translation was performed by 1 unit length from the large area one by one, and finally 32 new verified chips were obtained. The iterative translation is performed in turn, and finally all the chips to be verified are verified.
In one embodiment, based on the wafer shown in fig. 3, the steps are performed according to the above steps to obtain a chip template shown in fig. 4, and the chips on the chip template are automatically numbered from left to right and from top to bottom to obtain the numbers 0 to 44 of each chip on the chip template; if the verification image for the class-0 chip is shown in fig. 5, the chip in fig. 5 is externally provided with a dashed frame, which is the class-0 chip; the verification image of the 44-class chip is shown in fig. 6, and the chip in fig. 6 is externally provided with a dashed line frame, namely the 44-class chip; finally, the number statistics of all 0-44 chips are obtained, and the specific result is shown in FIG. 7.
In one embodiment, after the step of sequentially translating the center points of the arranged verified chips up, down, left, and right by a preset unit length, the method further includes: defining all chips to be verified as initial chips to be verified; taking the chip to be verified of which the outline range comprises the translated central point in the chip to be verified as a target chip to be verified; judging whether the difference between the areas of the target chip to be verified and the verified chip is larger than a preset value or not; if the number of the chips to be verified is smaller than the preset value, the target chip to be verified and the verified chip corresponding to the central point belong to the same number and become a new verified chip. Specifically, for the inspection to be a verified chip, the area of the verified chip is compared with the area of the chip to be verified whose outline range includes the center point, and if the difference between the two areas is smaller than a preset error value, the chip is of the same type.
In one embodiment, after the step of determining whether the difference between the areas of the target chip to be verified and the verified chip is greater than the predetermined value, the method further includes: if the chip number is larger than the preset value, the target chip to be verified is redefined as the initial chip to be verified. Specifically, if the difference between the areas of the two chips is greater than a preset error value, it indicates that the chip to be verified in which the center point is located is not of the same type as the verified chip.
In one embodiment, before the step of sequentially translating the center points of the arranged verified chips up, down, left, and right by a preset unit length, the method further includes: and expanding the area of the chip to be verified, which is smaller than the preset size standard, according to the preset size standard. Specifically, when iterative translation is actually performed, since the chips to be verified are not arranged in order, translation is performed only by integral multiples, and chips with small sizes in the oblique direction are easily ignored, so that the area of the small-sized chips to be verified can be expanded before translation, and the center coordinates of the verified chips are more easily in the range of the chips to be verified. The expansion is only carried out before translation, if the difference of areas is compared after translation, the original areas are adopted for comparison, and the expanded areas are only used for translation and are not included in the calculation during area comparison. The accuracy of the iterative translation verification method can be improved by expanding the area of the small-size chip to be verified and introducing a size rechecking mechanism.
In the embodiment, the position of the chip template on the wafer is determined by obtaining the chip template image from the wafer image, and the position of the chip on the chip template is further determined by utilizing a contour finding algorithm; determining the position of the chip on the wafer based on the position of the chip template on the wafer; numbering each chip on the chip template using an algorithm to obtain a verified chip at a determined position and number on the template; then, the verified chips are used for iterative translation, so that the chips to be verified with the determined positions but with the undetermined numbers are verified, and the number of the chips with each type of numbers is finally obtained; the method and the device realize the statistics of the number of different types of chips on the wafer, solve the problem that the continuous translation verification error of a group of verified chips is large because the wafer image has distortion, and improve the accuracy of number detection.
It will be apparent to those skilled in the art that the modules or steps of the invention described above may be implemented in a general purpose computing device, they may be centralized on a single computing device or distributed across a network of computing devices, and optionally they may be implemented in program code executable by a computing device, such that they may be stored on a computer storage medium (ROM/RAM, magnetic disks, optical disks) and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The foregoing is a more detailed description of the present invention with reference to specific embodiments thereof, and it is not intended to limit the invention to the specific embodiments thereof. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (5)
1. A chip quantity detection method based on iterative translation verification is characterized by comprising the following steps:
collecting a wafer image, and cutting a chip template from the wafer image to obtain a chip template image; determining the position of each chip on the wafer on the chip template;
numbering each chip on the chip template in sequence by using an algorithm to obtain the number of each chip;
the chips are divided into verified chips and chips to be verified, the chips with determined positions and numbers are defined as the verified chips, and the chips with the determined positions and undetermined numbers are defined as the chips to be verified;
carrying out binarization processing on the wafer image, finding out all contours on the wafer according to a contour searching algorithm to obtain the position of each contour on the wafer, wherein each contour corresponds to one chip so as to obtain the position of each chip on the wafer;
determining the serial numbers of all the chips to be verified on the wafer through iterative translation verification of the verified chips, thereby determining the number of each type of chips; arranging the verified chips in sequence according to sizes from large to small; sequentially translating the central points of the arrayed verified chips up and down, left and right for a preset unit length; the contour range in the chip to be verified comprises the translated central point, and the verified chip corresponding to the central point belongs to the same number and becomes a new verified chip; translating the central point of the newly verified chip up and down, left and right to preset unit length, and sequentially iterating and translating to obtain the serial numbers of all chips to be verified; thereby determining the number of types of chips.
2. The method of claim 1, wherein determining the position of each die on the die template on the wafer comprises:
matching a chip template on the wafer image by adopting a template matching algorithm based on the chip template image so as to obtain the position of the chip template on the wafer;
carrying out binarization processing on the chip template, determining the outline on the chip template by searching an outline algorithm to obtain the position of each outline on the chip template, wherein each outline corresponds to one chip, so as to obtain the position of each chip on the chip template;
and obtaining the position of each chip on the wafer according to the position of the chip template on the wafer and the position of each chip on the chip template.
3. The method as claimed in claim 1, wherein after the step of sequentially translating the center points of the arranged verified chips up, down, left, and right by a preset unit length, the method further comprises:
defining all chips to be verified as initial chips to be verified;
taking the chip to be verified of which the outline range comprises the translated central point in the chip to be verified as a target chip to be verified;
judging whether the difference between the areas of the target chip to be verified and the verified chip is larger than a preset value or not;
if the number of the target chip to be verified and the number of the verified chip corresponding to the central point are smaller than the preset value, the target chip to be verified and the verified chip corresponding to the central point belong to the same number, and the target chip to be verified and the verified chip corresponding to the central point are changed into a new verified chip.
4. The method of claim 3, wherein after the step of determining whether the difference between the areas of the target chip to be verified and the verified chip is greater than a predetermined value, the method further comprises:
if the chip number is larger than the preset value, the target chip to be verified is redefined as the initial chip to be verified.
5. The method as claimed in claim 1, wherein before the step of sequentially translating the center points of the aligned verified chips up, down, left, and right by a predetermined unit length, the method further comprises:
and expanding the area of the chip to be verified, which is smaller than the preset size standard, according to the preset size standard.
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| CN110544240A (en) * | 2019-08-21 | 2019-12-06 | 昆山思雷电子科技有限公司 | patch position error detection method |
| CN111558404A (en) * | 2020-05-12 | 2020-08-21 | 南方科技大学 | Microfluidic chip droplet path planning method, device, equipment and storage medium |
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