JPH0974056A - Method and apparatus for estimating yield of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To estimate the yield by presuming the number of short-circuited pattern elements on a chip before manufacture of a semiconductor. SOLUTION: A pattern managing means 1 abstracts a mask pattern which shows the pattern planned to be formed on a semiconductor chip out of a data base 6 when it receives the name of kind from a keyboard 7, and a short circuit probability computing means 2 assumes the pattern in the same form as the pattern on the chip, using the data of the mask pattern, and computes the probability (virtual short circuit rate) of the fellow virtual pattern elements short-circuiting by virtual foreign matter, separately for each dimension of virtual foreign matter. A foreign matter estimating means 3 measures the dimension of foreign matter and the number of pieces per unit area from a foreign matter inspection device, etc. A short circuit computing means 4 estimates the number of short-circuited pattern elements (the number of short circuits) per unit area on a chip by multiplying the vertual short circuit rate by the number of foreign matters per unit area. A yield computing means 5 estimates the yield of the semiconductors after manufacture, using the number of short circuits, and indicates it on a display 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device yield prediction method and a semiconductor device yield prediction method for taking into consideration that a pattern such as a wiring on a semiconductor chip is short-circuited by a foreign substance generated in a semiconductor manufacturing apparatus. The present invention relates to an apparatus, and since the yield can be predicted for each apparatus before manufacturing a semiconductor, it is effective for identifying a semiconductor manufacturing apparatus that requires intensive management such as examination of profitability and removal of foreign matter.

[0002]

2. Description of the Related Art With the high integration and miniaturization of semiconductor chips, foreign substances generated in a semiconductor manufacturing apparatus are apt to cause short circuits between patterns such as wiring and the yield is reduced.
Therefore, it is important to know in advance how much the yield will be before manufacturing the semiconductor chips in order to prevent a product shortage.

An example of a conventional semiconductor device yield prediction method will be described below with reference to the drawings.
A semiconductor device yield prediction system described in Japanese Patent No. 68 will be described. FIG. 11 shows functional blocks of a conventional semiconductor device yield prediction system. 11, the data analysis station 901 includes an intermediate inspection database 905, a yield prediction database 906, and a final inspection database 907. The intermediate inspection database 905 and the final inspection database 907.
Correlation of each data stored in is calculated, and the correlation coefficient is stored in the yield prediction database 906.

The intermediate inspection device 902 is a clean room 9
08, and the coordinates of the detected intermediate inspection defect position on the product wafer in some specific steps of the manufacturing step 909,
Detects the size of intermediate inspection defects and the number of intermediate defects,
It is stored in the intermediate inspection database 905 through the communication line 910. The final inspection device 903 performs a final inspection as a product of each chip on the processed product wafer, and stores the wafer number and the inspection result data in the final inspection database 907 through the communication line 911.

Reference numeral 904 is a monitor for displaying the output contents of the data analysis station, and reference numerals 912, 913 are wafer number recognition devices. In the semiconductor device yield prediction system configured as described above, the relational expression between the intermediate inspection data and the yield is created by using the data in the yield prediction database 906, and the yield regarding the wafer in the process of production is estimated.

[0006]

However, in the above-described configuration, the yield of semiconductors being manufactured is predicted by collecting the intermediate inspection data and the final inspection data for the past one or two months in advance. In addition, there is a problem in that the yield cannot be predicted, and it is impossible to examine profitability or to identify a device that may cause a decrease in yield before manufacturing.

In view of the above problems, it is an object of the present invention to provide a semiconductor device yield prediction method and device capable of predicting the yield before manufacturing a semiconductor chip.

[0008]

A semiconductor device yield prediction method according to claim 1, wherein a mask pattern used for manufacturing the first semiconductor chip is shown in a virtual plane having the same shape as that of the first semiconductor chip. The probability that at least two independent pattern elements are simultaneously short-circuited by the virtual foreign matter placed on the virtual plane overlapping at least two independent pattern elements forming the mask pattern is calculated for each size of the virtual foreign matter ( Short-circuit probability calculation process). In addition, the size of the foreign matter adhering to the second semiconductor chip and the number of foreign matter per unit area are measured in the semiconductor manufacturing apparatus used in the step of using the mask pattern or the steps before and after the step of using the mask pattern (the foreign matter. Number measurement process). Then, the probability of short circuit in the first semiconductor chip calculated in the short circuit probability calculation step and the number of foreign particles in the second semiconductor chip measured in the foreign particle number measurement step are multiplied for each foreign particle size,
The number of short-circuits between pattern elements per unit area of the semiconductor chip is calculated (short-circuit number calculation process).

According to the method of claim 1, the probability that the pattern elements of the mask pattern used for manufacturing the first semiconductor chip are short-circuited is obtained for each size of the virtual foreign substance by, for example, computer simulation, and semiconductor manufacturing is performed. By measuring the size of the foreign matter adhering to the second semiconductor chip and the number of foreign matter per unit area in the device and multiplying both by the size of the foreign matter, it is possible to obtain In one step, it is possible to estimate the number of pattern elements short-circuited to each other on the first semiconductor chip in the semiconductor manufacturing apparatus per unit area. Since a short circuit between pattern elements causes a defect in the semiconductor chip, the yield of the first semiconductor chip in the process can be estimated by substituting the number of short circuit between pattern elements into, for example, the Poisson yield calculation formula.

A semiconductor device yield prediction method according to a second aspect of the present invention is the semiconductor device yield prediction method according to the first aspect, wherein in the short-circuit probability calculation step, the virtual foreign matter is made rectangular and virtual on a virtual plane. The probability that at least two independent pattern elements are short-circuited is calculated by moving the foreign matter at equal intervals and dividing the number of times the virtual foreign matter simultaneously overlaps at least two independent pattern elements by the number of times the virtual foreign matter moves. .

A semiconductor device yield prediction method according to a third aspect of the present invention is the semiconductor device yield prediction method according to the first aspect, wherein the step of using the mask pattern is a lithography step, and the step prior to the step of using the mask pattern is cleaning. The etching process is a process and a deposited film forming process, and the process subsequent to the process of using the mask pattern is an etching process. The semiconductor device yield prediction method according to claim 4, wherein data of one mask pattern is extracted from a database storing data indicating all mask patterns used in manufacturing the first semiconductor chip, One mask pattern is shown in an imaginary plane that is the same shape, and at least two independent patterns in which virtual foreign matter placed on the imaginary plane are simultaneously overlapped with at least two independent pattern elements that form one mask pattern The probability that elements are short-circuited is calculated for each dimension of a virtual foreign substance (short-circuit probability calculation process). In addition, the size of foreign matter adhering to the second semiconductor chip and the number of foreign matter per unit area in the semiconductor manufacturing apparatus used before or after the step of using one mask pattern or the step of using one mask pattern are Measure (foreign matter number measurement process). Then, the probability of short circuit in the first semiconductor chip calculated in the short circuit probability calculation step and the number of foreign particles in the second semiconductor chip measured in the foreign particle number measurement step are multiplied for each size of the foreign particles, The number of short-circuiting pattern elements per unit area is calculated (short-circuit number calculation process). Further, after repeating the short circuit probability calculation process, the foreign substance number measurement process and the short circuit number calculation process for all the mask patterns used in the manufacture of the first semiconductor chip, all masks used in the manufacture of the first semiconductor chip For the patterns, the number of pattern elements short-circuited per unit area on the first semiconductor chip obtained in the short-circuit number calculation process is totaled, and the pattern elements short-circuited per unit area on the first semiconductor chip. The yield after manufacturing is calculated from the sum of the numbers (yield calculation process).

According to a fourth aspect of the present invention, the probability that the pattern elements of one mask pattern used for manufacturing the first semiconductor chip are short-circuited is obtained for each imaginary size of the foreign matter by, for example, computer simulation. When manufacturing the first semiconductor chip by measuring the size of the foreign matter adhering to the second semiconductor chip and the number of the foreign matter per unit area in the semiconductor manufacturing apparatus and multiplying both by the size of the foreign matter. 1st process in semiconductor manufacturing equipment
It is possible to estimate the number of short-circuiting pattern elements on the semiconductor chip per unit area. Further, when the number of pattern elements short-circuited with respect to all mask patterns is calculated and summed, and the total number of pattern elements short-circuited with respect to all mask patterns is calculated. Moreover, it is possible to estimate the number of pattern elements short-circuited with each other on the first semiconductor chip in the semiconductor manufacturing apparatus per unit area in all steps. Since a short circuit between pattern elements causes a defect in the semiconductor chip, the yield of the first semiconductor chip after manufacturing is estimated by substituting the total number of short circuits between pattern elements into, for example, the Poisson yield calculation formula. it can.

According to a fifth aspect of the semiconductor device yield prediction method, a mask pattern used for manufacturing the first semiconductor chip is shown in a virtual plane having the same shape as the first semiconductor chip, and the mask pattern is placed on the virtual plane. And calculating a probability that at least two independent pattern elements are simultaneously overlapped with at least two independent pattern elements forming the mask pattern and the at least two independent pattern elements are short-circuited for each size of the virtual foreign matter (short-circuit probability calculation process), The short circuit probability in the first semiconductor chip calculated in the short circuit probability calculation process is the probability that pattern elements on the third semiconductor chip are actually short circuited and the short circuit probability in the third semiconductor chip calculated in the short circuit probability calculation process. Correct by the difference from the probability (short-circuit probability correction process). In addition, the size of the foreign matter adhering to the second semiconductor chip and the number of foreign matter per unit area are measured in the semiconductor manufacturing apparatus used in the step of using the mask pattern or the steps before and after the step of using the mask pattern (the foreign matter. Number measurement process). Then, the corrected probability of short circuit in the first semiconductor chip calculated in the short circuit probability correction step and the number of foreign particles in the second semiconductor chip measured in the foreign material number measurement step are multiplied by each foreign particle size to obtain the first The number of short-circuits between pattern elements per unit area of a semiconductor chip is calculated (short-circuit number calculation process).

According to the method of claim 5, the probability that the pattern elements of the mask pattern used for manufacturing the first semiconductor chip are short-circuited is obtained for each size of the virtual foreign substance by, for example, computer simulation, and On the third semiconductor chip in the semiconductor manufacturing apparatus, the pattern elements on the third semiconductor chip are corrected by the difference between the probability that the pattern elements on the semiconductor chip are actually short-circuited and the short-circuit probability on the third semiconductor chip calculated by the short-circuit probability calculation process. By measuring the size of the foreign matter adhering to and the number of foreign matter per unit area, and multiplying both by the foreign matter size, the first semiconductor chip in the semiconductor manufacturing apparatus can be manufactured in one step when manufacturing the first semiconductor chip. It is possible to highly accurately estimate the number of pattern elements short-circuited on one semiconductor chip per unit area. Since a short circuit between pattern elements causes a defect of a semiconductor chip, the number of short circuits between pattern elements is substituted into, for example, Poisson's yield calculation formula to determine the first step in the process.
The yield of semiconductor chips can be estimated.

A semiconductor device yield prediction method according to a sixth aspect is the semiconductor device yield prediction method according to the fifth aspect, wherein the probability of pattern elements being short-circuited on the first semiconductor chip is calculated in the short-circuit probability calculation step. In the process of calculating the short circuit probability, the first function is calculated, in which the vertical axis indicates the probability of short circuit and the horizontal axis indicates the dimension of the virtual foreign substance. A second function is calculated, in which the vertical axis indicates the probability of short-circuiting and the horizontal axis indicates the size of the virtual foreign matter, and the pattern elements are actually short-circuited by the foreign matter actually attached on the third semiconductor chip. Then, the third function is shown in which the vertical axis indicates the probability of actual short circuit and the horizontal axis indicates the size of the foreign matter. Then, the second function is translated in the horizontal axis direction, the difference between the probability of the second function after translation and the probability of the third function is added for each size of the foreign matter, and the probability difference is calculated. Find the movement amount of the second function when the total value becomes the minimum,
In the short-circuit probability correction process, the fourth function is generated by translating the first function in the horizontal axis direction by the movement amount of the second function when the total value of the difference of the probabilities is minimized. The number of foreign matters in the semiconductor chip is measured for each foreign matter size in the foreign matter number measurement process, and a fifth function is created in which the number of foreign matter is plotted on the vertical axis and the foreign matter dimension is plotted on the horizontal axis. And the fourth and fifth functions are multiplied.

According to another aspect of the semiconductor device yield prediction method of the present invention, one mask pattern data is extracted from a database storing data showing all mask patterns used in the manufacture of the first semiconductor chip, and the first mask pattern data is extracted. One mask pattern is shown in a virtual plane having the same shape as the semiconductor chip, and a virtual foreign substance placed on the virtual plane simultaneously overlaps with at least two independent pattern elements constituting one mask pattern, and at least two mask patterns are formed. The probability of short circuit between independent pattern elements is calculated for each size of the virtual foreign substance (short circuit probability calculation process), and the probability of short circuit in the first semiconductor chip calculated in the short circuit probability calculation process is calculated on the third semiconductor chip. Of the actual short circuit between the pattern elements and the short circuit in the third semiconductor chip calculated by the short circuit probability calculation process That is corrected by the difference between the probability (short-circuit probability correction process). In addition, the size of the foreign matter adhering to the second semiconductor chip and the number of foreign matter per unit area are measured in the semiconductor manufacturing apparatus used in the process using one mask pattern or in the process before and after the process (measurement of the number of foreign substances) process). Then, the corrected probability of short circuit in the first semiconductor chip corrected in the short circuit probability correction process and the number of foreign particles in the second semiconductor chip measured in the foreign material number measurement process are multiplied for each size of the foreign material to obtain the first The number of short-circuits between pattern elements per unit area of a semiconductor chip is calculated (short-circuit number calculation process). Further, after repeating the short circuit probability calculation process, the short circuit probability correction process, the foreign matter number measurement process and the short circuit number calculation process for all the mask patterns used in the manufacture of the first semiconductor chip, the manufacture of the first semiconductor chip is performed. The total number of short-circuiting pattern elements per unit area on the first semiconductor chip obtained in the process of calculating the number of short-circuits for all mask patterns used in The yield after manufacturing is calculated from the total number of short-circuited elements (yield calculation process).

According to the method of claim 7, the probability that the pattern elements of one mask pattern used for manufacturing the first semiconductor chip are short-circuited is obtained for each virtual foreign matter size, for example, by computer simulation. Furthermore, the probability that pattern elements on the third semiconductor chip are actually short-circuited and the third calculated by the short-circuit probability calculation process
Corrected by the difference with the probability of short circuit in the semiconductor chip of
When manufacturing the first semiconductor chip by measuring the size of the foreign matter adhering to the second semiconductor chip and the number of the foreign matter per unit area in the semiconductor manufacturing apparatus and multiplying both by the size of the foreign matter. In one step, it is possible to estimate the number of pattern elements short-circuited with each other on the first semiconductor chip in the semiconductor manufacturing apparatus per unit area. Further, when the number of pattern elements short-circuited with respect to all mask patterns is calculated and summed, and the total number of pattern elements short-circuited with respect to all mask patterns is calculated. In addition, it is possible to highly accurately estimate the number of short-circuiting pattern elements on the first semiconductor chip in the semiconductor manufacturing apparatus per unit area in all steps. Since a short circuit between pattern elements causes a defect in the semiconductor chip, the yield of the first semiconductor chip after manufacturing is estimated by substituting the total number of short circuits between pattern elements into, for example, the Poisson yield calculation formula. it can.

According to another aspect of the semiconductor device yield prediction apparatus of the present invention, there is provided a short circuit probability calculating means, a foreign matter number measuring means, and a short circuit number calculating means. The short-circuit probability calculating means indicates a mask pattern used for manufacturing the first semiconductor chip in a virtual plane having the same shape as the first semiconductor chip, and the virtual foreign matter placed on the virtual plane constitutes the mask pattern. The probability that at least two independent pattern elements are simultaneously overlapped with each other and at least two independent pattern elements are short-circuited is calculated for each virtual foreign matter size. Further, the foreign matter number measuring means measures the size of the foreign matter adhered on the second semiconductor chip and the foreign matter per unit area in the semiconductor manufacturing apparatus used in the process using the mask pattern or the process before and after the process using the mask pattern. Count the number. Further, the short-circuit number calculating means multiplies the probability of short-circuiting in the first semiconductor chip calculated by the short-circuit probability calculating means and the number of foreign particles in the second semiconductor chip measured by the foreign particle number measuring means for each foreign particle size, The number of pattern elements short-circuited per unit area of the first semiconductor chip is calculated.

According to the structure described in claim 8, the probability that the pattern elements of the mask pattern used for manufacturing the first semiconductor chip are short-circuited is calculated for each virtual size of the foreign matter by simulation of a computer, and semiconductor manufacturing is performed. By measuring the size of the foreign matter adhering to the second semiconductor chip and the number of foreign matter per unit area in the device and multiplying both by the size of the foreign matter, it is possible to obtain In one step, it is possible to estimate the number of pattern elements short-circuited to each other on the first semiconductor chip in the semiconductor manufacturing apparatus per unit area. Since a short circuit between pattern elements causes a defect in the semiconductor chip, the yield of the first semiconductor chip in the process can be estimated by substituting the number of short circuit between pattern elements into, for example, the Poisson yield calculation formula.

A semiconductor device yield prediction apparatus according to a ninth aspect comprises a database, a short-circuit probability calculation means, a foreign matter number measurement means, a short-circuit number calculation means, and a yield calculation means.
The database stores data indicating all mask patterns used in manufacturing the first semiconductor chip. The short-circuit probability calculation means extracts data of one mask pattern from the database, shows one mask pattern in a virtual plane having the same shape as the first semiconductor chip, and the virtual foreign matter placed on the virtual plane is A probability that at least two independent pattern elements that simultaneously overlap with at least two independent pattern elements that form one mask pattern are short-circuited is calculated for each size of the virtual foreign matter. The foreign matter number measuring unit measures the size and the unit area of the foreign matter deposited on the second semiconductor chip in the semiconductor manufacturing apparatus used in the process using one mask pattern or the process before and after the process using one mask pattern. Measure the number of foreign particles. The short circuit number calculating means multiplies the probability of short circuit in the first semiconductor chip calculated by the short circuit probability calculating means and the number of foreign particles in the second semiconductor chip measured by the foreign particle number measuring means for each foreign particle size, The number of short-circuits between pattern elements per unit area of the semiconductor chip is calculated.
The yield calculation means repeatedly operates the short-circuit probability calculation means, the foreign matter number measurement means, and the short-circuit number calculation means for all mask patterns used in the manufacture of the first semiconductor chip, and is used in the manufacture of the first semiconductor chip. For all mask patterns, the number of short-circuiting pattern elements per unit area of the first semiconductor chip obtained by the short-circuit number calculating means is totaled, and the pattern elements are connected to each other per unit area on the first semiconductor chip. The yield after the end of manufacturing is displayed from the total number of short circuits.

According to a ninth aspect of the present invention, the probability that the pattern elements of one mask pattern used for manufacturing the first semiconductor chip are short-circuited is obtained for each virtual foreign matter size by simulation of a computer, for example. When manufacturing the first semiconductor chip by measuring the size of the foreign matter adhering to the second semiconductor chip and the number of the foreign matter per unit area in the semiconductor manufacturing apparatus and multiplying both by the size of the foreign matter. 1st process in semiconductor manufacturing equipment
It is possible to estimate the number of short-circuiting pattern elements on the semiconductor chip per unit area. Further, when the number of pattern elements short-circuited with respect to all mask patterns is calculated and summed, and the total number of pattern elements short-circuited with respect to all mask patterns is calculated. Moreover, it is possible to estimate the number of pattern elements short-circuited with each other on the first semiconductor chip in the semiconductor manufacturing apparatus per unit area in all steps. Since a short circuit between pattern elements causes a defect in the semiconductor chip, the yield of the first semiconductor chip after manufacturing is estimated by substituting the total number of short circuits between pattern elements into, for example, the Poisson yield calculation formula. it can.

A semiconductor device yield prediction apparatus according to a tenth aspect of the present invention comprises a short circuit probability calculation unit, a short circuit probability correction unit, a foreign matter number measurement unit, and a short circuit number calculation unit. The short-circuit probability calculating means indicates a mask pattern used for manufacturing the first semiconductor chip in a virtual plane having the same shape as the first semiconductor chip, and the virtual foreign matter placed on the virtual plane constitutes the mask pattern. The probability that at least two independent pattern elements are simultaneously overlapped with each other and at least two independent pattern elements are short-circuited is calculated for each virtual foreign matter size. The short-circuit probability correction means calculates the short-circuit probability in the first semiconductor chip calculated by the short-circuit probability calculation means by the probability that pattern elements on the second semiconductor chip are actually short-circuited and the second short-circuit probability calculation means. It is corrected by the difference with the probability of short-circuiting in the semiconductor chip. The foreign matter number measuring means measures the size of the foreign matter deposited on the second semiconductor chip and the number of foreign matter per unit area in the semiconductor manufacturing apparatus used in the process using the mask pattern or the process before and after the process using the mask pattern. taking measurement. The short-circuit number calculating means multiplies the corrected short-circuit probability in the first semiconductor chip calculated by the short-circuit probability correcting means and the number of foreign matters in the second semiconductor chip measured by the foreign matter number measuring means for each foreign matter size. , The number of short circuits between the pattern elements per unit area of the first semiconductor chip is calculated.

According to the structure described in claim 10, the probability that the pattern elements of the mask pattern used for manufacturing the first semiconductor chip are short-circuited is obtained for each size of the virtual foreign substance by, for example, a computer simulation. On the second semiconductor chip in the semiconductor manufacturing apparatus, by correcting the difference between the probability that the pattern elements on the semiconductor chip of 3 are actually short-circuited and the probability of short-circuiting on the third semiconductor chip calculated by the short-circuit probability calculation process. By measuring the size of the foreign matter adhering to and the number of foreign matter per unit area, and multiplying both by the foreign matter size, the first semiconductor chip in the semiconductor manufacturing apparatus can be manufactured in one step when manufacturing the first semiconductor chip. It is possible to highly accurately estimate the number of pattern elements short-circuited on one semiconductor chip per unit area. Since a short circuit between pattern elements causes a defect of a semiconductor chip, the number of short circuits between pattern elements is substituted into, for example, Poisson's yield calculation formula to determine the first step in the process.
The yield of semiconductor chips can be estimated.

A semiconductor device yield prediction apparatus according to an eleventh aspect of the present invention comprises a database, a short circuit probability calculation unit, a short circuit probability correction unit, a foreign matter number measurement unit, a short circuit number calculation unit, and a yield calculation unit. The database stores data indicating all mask patterns used in manufacturing the first semiconductor chip. The short-circuit probability calculation means extracts data of one mask pattern from the database, shows one mask pattern in a virtual plane having the same shape as the first semiconductor chip, and the virtual foreign matter placed on the virtual plane is A probability that at least two independent pattern elements that simultaneously overlap with at least two independent pattern elements that form one mask pattern are short-circuited is calculated for each size of the virtual foreign matter. The short-circuit probability correcting means calculates the short-circuit probability in the first semiconductor chip calculated by the short-circuit probability calculating means by the probability that pattern elements on the third semiconductor chip are actually short-circuited and the third short-circuit probability calculating means. It is corrected by the difference with the probability of short-circuiting in the semiconductor chip. The foreign matter number measuring means measures the size of the foreign matter deposited on the second semiconductor chip and the number of foreign matter per unit area in the semiconductor manufacturing apparatus used in the process using one mask pattern or the process before and after the process. . The short-circuit number calculating means multiplies the corrected short-circuit probability in the first semiconductor chip corrected by the short-circuit probability correcting means and the number of foreign matters in the second semiconductor chip measured by the foreign matter number measuring means for each foreign matter size. , The number of short circuit between pattern elements per unit area of the first semiconductor chip is output. The yield calculation means is
For all the mask patterns used in the manufacture of the first semiconductor chip, the short-circuit probability calculating means, the short-circuit probability correcting means, the foreign matter number measuring means, and the short-circuit number calculating means are repeatedly operated, and the unit area of the first semiconductor chip is reduced. The total number of pattern elements short-circuited with each other is displayed, and the yield after manufacturing is displayed from the total number of pattern element short-circuits per unit area on the first semiconductor chip. According to the configuration of claim 11, the probability that the pattern elements of one mask pattern used for manufacturing the first semiconductor chip are short-circuited is obtained for each size of the virtual foreign matter by simulation of a computer, and the third Correction is performed by the difference between the probability that the pattern elements on the semiconductor chip are actually short-circuited and the probability that the third semiconductor chip is short-circuited calculated by the short-circuit probability calculation process, and the second
Of the foreign matter adhering to the semiconductor chip and the number of the foreign matter per unit area are measured, and both are multiplied by the size of the foreign matter to manufacture the first semiconductor chip in one step. It is possible to estimate the number of short circuiting pattern elements on the first semiconductor chip in the device per unit area. Further, when the number of pattern elements short-circuited with respect to all mask patterns is calculated and summed, and the total number of pattern elements short-circuited with respect to all mask patterns is calculated. Moreover, it is possible to highly accurately estimate the number of pattern elements short-circuited to each other on the first semiconductor chip in the semiconductor manufacturing apparatus per unit area in all steps. Since a short circuit between pattern elements causes a defect in the semiconductor chip, the yield of the first semiconductor chip after manufacturing is estimated by substituting the total number of short circuits between pattern elements into, for example, the Poisson yield calculation formula. it can.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a method of predicting a yield related to semiconductor manufacturing and an apparatus therefor according to embodiments of the present invention will be described with reference to the drawings. The first embodiment relates to claims 1, 2, 3, 4, 8 and 9
The embodiments are described with respect to claims 5, 6, 7, 10, and 11.

(First Embodiment) FIG. 1 is a functional block diagram of a semiconductor device yield prediction apparatus for carrying out a semiconductor device yield prediction method according to a first embodiment of the present invention. Reference numeral 1 denotes a pattern management means for managing data indicating a contour line of a mask pattern used for manufacturing a semiconductor chip (referred to as a mask pattern).

In the second step, data of one mask pattern is extracted from a database storing data showing all mask patterns used in manufacturing the first semiconductor chip,
One mask pattern is shown in a virtual plane having the same shape as that of the semiconductor chip, and a virtual foreign substance placed on the virtual plane simultaneously overlaps with at least two independent pattern elements constituting one mask pattern to form at least 2 It is a short-circuit probability calculation means for calculating the probability that two independent pattern elements will be short-circuited for each size of the virtual foreign matter. That is,
The short-circuit probability calculation means 2 virtualizes a mask pattern on a computer, and the probability that virtual pattern elements (described as virtual pattern elements) are short-circuited due to the difference in the dimension x of a virtual foreign material (described as virtual foreign material) ( Calculated as a virtual short circuit rate).

Numeral 3 is the size and the unit area of the foreign matter adhering to the second semiconductor chip in the semiconductor manufacturing apparatus used in the step of using one mask pattern or the steps before and after the step of using one mask pattern. It is a foreign substance number measuring means for measuring the number of foreign substances. That is, the foreign matter number measuring means 3 measures the size and the number of foreign matter adhered on the second semiconductor chip in the semiconductor manufacturing apparatus by the foreign matter inspection apparatus.

Reference numeral 4 is a short-circuit probability in the first semiconductor chip calculated by the short-circuit probability calculating means 2 and foreign matter number measuring means 3
It is a short-circuit number calculation means for calculating the number of short-circuits between pattern elements per unit area of the first semiconductor chip by multiplying the number of foreign particles in the second semiconductor chip measured in 1) for each size of the foreign particles. That is, the short circuit number calculation means 4
Using the size and the virtual short-circuit rate of the virtual foreign matter calculated by the short-circuit probability calculation means 2 and the size and number of the foreign matter detected by the foreign matter number measurement means 3, a pattern is formed on the first semiconductor chip when the manufacturing apparatus is used. Estimate the number of short-circuits between elements (referred to as the number of short-circuits).

Reference numeral 5 is a first semiconductor by repeatedly operating the short-circuit probability calculating means 2, the foreign matter number measuring means 3 and the short-circuit number calculating means 4 for all mask patterns used in the manufacture of the first semiconductor chip. Units on the first semiconductor chip are summed up by summing up the number of pattern elements short-circuited per unit area on the first semiconductor chip obtained by the short-circuit number calculation means 4 for all mask patterns used in the manufacture of chips. It is a yield calculation means for calculating the yield after the end of manufacturing from the total number of short-circuiting pattern elements per area. That is, the yield calculation means 5 is provided for a plurality of manufacturing apparatuses used for manufacturing the first semiconductor chip.
The operations of the short-circuit probability calculating unit 2, the foreign matter number measuring unit 3, and the short-circuit number calculating unit 4 are repeated, the respective short-circuit numbers are summed, and the sum of the short-circuit numbers is substituted into, for example, Poisson's yield calculation formula, thereby ending the manufacturing. The yield of manufacturing the first semiconductor chip later can be estimated. If the number of short circuits in each process is substituted into the Poisson's yield calculation formula, for example, the yield in each process can be estimated. Moreover, even if the number of short circuits is not substituted in the yield calculation formula, the yield decreases as the number of short circuits increases.
The yield level can be estimated from the number of short circuits.

Reference numeral 6 denotes a database which stores data of the contour line of a mask pattern used for manufacturing a semiconductor chip, which is managed by the pattern management means 1. 7 is a keyboard. Reference numeral 8 is a display for displaying a predicted yield value. The operation of the semiconductor device yield prediction apparatus that implements the semiconductor device yield prediction method configured as described above will be described.

When the pattern management means 1 receives the type name of the semiconductor device from the keyboard 7, it uses the type name as a search key and from the database 6 the name of the manufacturing apparatus used for manufacturing the semiconductor device corresponding to the type name and The mask pattern combinations are sequentially extracted one by one and sent to the short circuit probability calculating means 2. FIG. 2 shows the structure of the database 6. In FIG. 2, 100 is a field for storing a product type name, 101 is a field for storing a name of a manufacturing apparatus, 1
A field 02 stores a mask pattern.

In the data of the field 102, 1 to
The reason why the mask patterns on the third row are the same will be described.
The presence of foreign matter on the mask pattern formed by the stepper device causes a short circuit between pattern elements, so the fields related to the cleaning device (cleaning process) and the oxidation furnace device (deposited film forming process) used before the stepper device 1
In 02, a mask pattern having the same shape as the mask pattern used in the stepper device (lithography process) is stored. In addition, a field 10 corresponding to a dry etching device (etching process) used after the stepper device
The data of 2 is also the same as the mask pattern of the stepper device for the same reason.

The short circuit probability calculating means 2 calculates a virtual short circuit rate using the data of the first mask pattern, and does not handle the second and subsequent data until a virtual short circuit rate calculation command for the next semiconductor manufacturing apparatus arrives. . Hereinafter, the method of calculating the virtual short circuit rate will be described by taking the mask pattern data of the stepper device as an example.

FIG. 3 shows graphic data of a virtual mask pattern used in the calculation of the virtual short circuit rate. The mask pattern is processed as follows and used for calculating the virtual short circuit rate. Dots forming independent pattern elements are set as one group, and a unique value (1, 2, ...) Is given to each dot in the group. The area other than the pattern element is "0". Here, 200 is a chip and 20
1 is a pattern element having a value of "1", and 202 is a pattern element having a value of "2". In addition,
“0” is a value attached to the area where the pattern element does not exist.

FIG. 4 shows an algorithm for calculating the virtual short circuit rate. x and y are variables indicating the position of the virtual foreign substance on the chip. S_COUNT is a variable for substituting the number of short circuits, and M_COUNT is a variable for substituting the number of times the virtual foreign matter has moved. FIG. 5 shows the position of the virtual foreign matter when it is judged in step s101 of FIG. 4 divided into three. The chip 200 is divided into m1 equal parts in the x direction and m2 equal parts in the y direction, and 203 is a virtual foreign substance having the same area as the square, and is a square having a side length of L. 210 is a layout showing the position of the virtual foreign matter 203 at the start of calculation, 220 is the virtual foreign matter 203 is the pattern element 201 and the pattern element 2
The layout when it overlaps 02, 230 is a virtual foreign object 2
03 is a layout in the case where both pattern elements 201 and 202 do not overlap at the same time.

Below, along with the flow of the algorithm of FIG. 4, the virtual short-circuit rate in the case of using the virtual foreign material of the dimension L is calculated. The first step s100 initializes the values of S_COUNT and M_COUNT to 0. Further, the virtual foreign matter 203 is located at the coordinates shown by the layout 210 in FIG.

Steps s101 to s105
Is a routine for determining whether or not the virtual foreign matter 203 overlaps with two or more separated pattern elements while moving the position of the virtual foreign matter 203. Step s101
In, the value held by the bit in the area of the virtual foreign matter 203 is extracted from the graphic data, and it is checked whether or not there are two or more numerical values (excluding 0). If there are two or more different numerical values, it is determined that the virtual foreign matter 203 overlaps the pattern element 201 and the pattern element 202. For example, this is the state of the layout 220 in FIG. However, if two or more different numerical values do not exist, it is determined that the virtual foreign matter 203 does not overlap both the pattern element 201 and the pattern element 202 at the same time.
For example, this is the state of the layout 230 in FIG.

In step s102, the number of times the virtual foreign matter 203 overlaps the pattern element 201 and the pattern element 202 is stored in the variable S_COUNT. Step s103
Is the number of times the virtual foreign matter 203 has moved to the variable M_COUNT.
To be stored. In step s104, the X coordinate of the virtual foreign matter 203 is controlled so as to be increased by 1 with the maximum value being m1.

In step s105, the X-coordinate of the virtual foreign matter 203 is set to 1, and the Y-coordinate is controlled to be increased by 1 with the maximum value being m2. In this way, step s10
By the routine of 1 to step s105, the virtual foreign matter 2
03, the number of times the pattern element 201 and the pattern element 202 overlap (S_COUNT) and the number of movements of the virtual foreign matter 203 (M_COUNT) are calculated, and step s106
Calculate the virtual short circuit rate with.

As described above, by repeating the above algorithm for virtual foreign matters of various sizes (dimensions), it is possible to generate a function indicating the relationship between the virtual foreign matter dimensions and the virtual short circuit rate. The foreign matter number measuring means 3 uses the dimension and the number of the foreign matter actually measured by the foreign matter inspecting device or the like with respect to the semiconductor manufacturing apparatus for which the short circuit number calculating means 2 has calculated the short circuit rate, and the foreign matter dimension x and the number Generate a function that shows the relationship between. This foreign matter inspection is performed in advance using, for example, a pattern defect inspection device (for example, KLA2130 manufactured by KLA).
The pattern defect inspection apparatus described above is capable of performing two types of pattern defect inspections, a random mode (comparison between chips) and an array mode (comparison between cells having the same shape in a chip). Then, for example, the inspection is performed in the array mode.

The inspection principle is as follows. That is, a plurality of cells of the same shape arranged in a line are imaged by a CCD image pickup device or the like, the image data is compared between the center cell and the left cell located on the left side of the cell, and the center cell and the right cell located on the right side The image data are compared with and the result of the comparison is used to determine whether or not there is a defect, that is, a foreign substance, in the central cell while sequentially changing the central cell. The judgment criteria are shown below. The image data differs between the center cell and the left cell, and the image data differs between the center cell and the right cell,
In addition, when the center cell and the left cell have different image data positions and the center cell and the right cell have different image data positions, it is determined that the center cell has a defect (foreign substance). Further, when the center cell and the left cell have different image data, and the center cell and the right cell have the same image data, or the center cell and the left cell have the same image data, and the center cell and the left cell have the same image data. If the right cell has different image data, or if the center cell has the same image data as the left cell, and the center cell has the same image data as the right cell, the center cell has a defect (contamination). Judge that there is no. Note that the cells at both ends of the plurality of cells arranged in a line cannot be inspected because the other cells are not adjacent to one side.

The short-circuit number calculating means 4 calculates the short-circuit number D _i per unit area by using [Equation 1].

[0044]

[Equation 1] Here, f _i (x) is a function generated by the short-circuit probability calculation means 2 and represents the relationship between the size x of the virtual foreign matter and the virtual short-circuit rate. g _i (x) is a function generated by the foreign matter number measuring means 3 and shows the relationship between the foreign matter dimension x and the number. Also, f
_{i of i} (x) and g _i (x) represents the number of the semiconductor manufacturing apparatus used in the i-th semiconductor manufacturing process.

In FIG. 6, the function f _i (x) and the function g
_i (x) is shown. Here, the number of short circuits D _i per unit area
Corresponds to the area of the hatched portion of f _i (x) · g _i (x). Since the function f _i (x) is determined by the mask pattern on the first semiconductor chip and the semiconductor manufacturing apparatus, i
The number of short circuits D _i can be calculated by measuring the function g _i (x) of the semiconductor manufacturing apparatus used in the second step.

In this way, if the size and the number of foreign substances actually attached are detected by using the second semiconductor chip other than the one for manufacturing the first semiconductor chip (arbitrary shape and no pattern is required), Moreover, the number of short circuits when the semiconductor manufacturing apparatus is used can be estimated without manufacturing the first semiconductor chip. The yield calculation means 5 calculates the yield prediction value y _i when the semiconductor manufacturing apparatus is used in the i-th step by using the Poisson's yield calculation formula of [Equation 2].

[0047]

Y _i = exp (−D _i · S) where D _i is the number of short circuits per unit area calculated by the short circuit number calculating means, and S is the surface area of the semiconductor chip.
Thus, by using [Equation 2], it is possible to predict the yield when the semiconductor manufacturing apparatus is used in the i-th step.

Next, at the time of manufacturing the first semiconductor chip, the short-circuit probability calculating means 2 and the short-circuit number calculating means 4 are also operated for other semiconductor manufacturing apparatuses to be used, and the number of short-circuits per unit area is calculated. Then, by substituting the sum of the number of short circuits in [Equation 2] for D _i , the yield of semiconductors after the manufacturing can be estimated. According to this embodiment, for example, by computer simulation, the probability that pattern elements of one mask pattern used for manufacturing the first semiconductor chip are short-circuited is obtained for each size of the virtual foreign matter, and is calculated in the semiconductor manufacturing apparatus. By measuring the size of the foreign matter adhering to the second semiconductor chip and the number of the foreign matter per unit area, and multiplying both by the size of the foreign matter, it is possible to perform one step when manufacturing the first semiconductor chip. It is possible to estimate the number of short-circuiting pattern elements on the first semiconductor chip in the semiconductor manufacturing apparatus per unit area. Further, when the number of pattern elements short-circuited with respect to all mask patterns is calculated and summed, and the total number of pattern elements short-circuited with respect to all mask patterns is calculated. Moreover, it is possible to estimate the number of pattern elements short-circuited with each other on the first semiconductor chip in the semiconductor manufacturing apparatus per unit area in all steps. Since a short circuit between pattern elements causes a defect in a semiconductor chip, the number of short circuit between pattern elements or the sum thereof is substituted into, for example, Poisson's yield calculation formula, so that the yield for each process or the first The yield of semiconductor chips can be estimated.

With the method and the apparatus as described above, the yield can be predicted before manufacturing the first semiconductor chip. As a result, it is possible to select a device that needs to be improved in order to verify profitability and improve yield before manufacturing a semiconductor. Although the virtual foreign matter is a square in the short-circuit probability calculating means 2 of the first embodiment, a polygonal shape and a circle can also obtain the same effect. Further, although the virtual foreign matter is moved at equal intervals in order, the same effect can be obtained by random movement. Furthermore, the calculation time can be shortened by moving the virtual foreign matter with one or more intervals.

Further, the present invention has the same effect on the yield of products in which a short circuit between pattern elements such as a wiring board of an electric product causes a defect. Although the Poisson's yield calculation formula is used in the first embodiment, the same effect can be obtained by using a yield calculation formula such as Seeds or Murphy instead. (Second Embodiment) FIG. 7 is a functional block diagram of a semiconductor device yield prediction apparatus for carrying out a semiconductor device yield prediction method according to a second embodiment of the present invention. This functional block diagram is for correcting the short-circuit probability correcting means 9 in the functional block diagram described in the first embodiment and the virtual short-circuit rate using the virtual pattern so as to match the short-circuit rate calculated from the actual measurement. The database 10 in which the data of 1. is stored is added, and the other points are the same as those in the first embodiment.

The short circuit probability correcting means 9 and the database 10 will be described below. The short-circuit probability correction means 9 uses the data in the database 10 to correct the function f _i (x) indicating the relationship between the size of the virtual foreign matter and the virtual short-circuit rate to obtain the function h _i (x) from the measurement results. Match the calculated short circuit rate. FIG. 8 shows the structure of the database 10. Reference numeral 103 is a field for storing the minimum width between pattern elements formed on the semiconductor chip, and 104 is a field for storing a numerical value used for correction of the function f _i (x).

A method of calculating the data stored in the field 104 will be described. FIG. 9 shows a function h _i ′ (x) and a function f showing the relationship between the size of the foreign matter and the short circuit rate obtained from the actual measurement results.
_i '(x) is shown. ds converts the function f _i ′ (x) to the function h
It is the amount of translation that is translated in the horizontal axis direction so as to best match _i ′ (x). For the movement amount ds, the function f _i ′ (x) is gradually moved in parallel along the horizontal axis, and the total value of the differences between the function f _i ′ (x) and the function h _i ′ (x) is minimum for each size of the foreign matter. It is the value when The movement amount ds is obtained in advance before manufacturing the first semiconductor chip by using another third semiconductor chip having a shape and a mask pattern different from those of the first semiconductor chip. The pattern formed on the third semiconductor chip has, for example, a pair of comb-teeth shapes that mesh with each other.

Next, the relationship between the short circuit probability calculating means 2, the short circuit probability correcting means 9 and the short circuit number calculating means 4 will be described. FIG. 10 shows the structure of the database 6. A field 103 for storing the minimum width between pattern elements is added to the database 6 of the first embodiment. Keyboard 7
When the product type name is input from, the short circuit probability calculation unit 2 extracts the semiconductor manufacturing device name and the minimum width between pattern elements associated with the product type name from the database 6, and the short circuit probability correction unit 9 extracts the manufacturing device name and pattern. The movement amount used for correction is extracted from the database 10 using the minimum width between elements as a search key. If the value equal to the minimum width between the pattern elements extracted from the database 6 is not in the database 10, the value closest to the minimum width is searched. Further, in the short circuit number calculating means 4, unlike the first embodiment,
The function h _i (x) corrected by the short circuit probability correcting means 9 is used. The function h _i (x) is obtained by translating the function f _i (x) in the horizontal axis direction by the movement amount ds according to the minimum width between pattern elements.

In this embodiment, the function f _i (x)
Corresponds to the first function in claim 6, and the function f _i ′
(X) corresponds to the second function in the claim, and the function h
_i ′ (x) corresponds to the third function in the claim, and h
_i (x) corresponds to the fourth function in the claim, and g _i
(X) corresponds to the fifth function in the claims. According to the method and apparatus as described above, the probability that the pattern elements of one mask pattern used for manufacturing the first semiconductor chip will be short-circuited is calculated for each size of the virtual foreign matter, and further on the third semiconductor chip. Since the pattern elements are corrected by the difference between the probability of actual short circuit and the probability of short circuit in the third semiconductor chip calculated by the short circuit probability calculation process, the yield can be predicted with higher accuracy than in the first embodiment. it can.

[0055]

According to the present invention, the probability of short-circuiting between pattern elements is calculated for each dimension of a foreign substance by using a virtual pattern, and in some cases, the above probability is compared with the probability of short-circuiting with other semiconductor chips. While correcting the difference with the probability of short circuit, the number of foreign particles is detected for each dimension of the foreign particles by actual measurement, and the number is multiplied by the probability of short circuit between the virtual pattern elements or the corrected probability, and the first By estimating the number of short-circuiting pattern elements on the semiconductor chip, it is possible to predict the yield of semiconductor devices for each manufacturing apparatus or after the completion of all manufacturing steps.

Furthermore, since the yield can be predicted, it is possible to verify the profitability of semiconductors before manufacturing them and to select a device that needs improvement in order to improve the yield.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing a configuration of a semiconductor device yield prediction apparatus for carrying out a semiconductor device yield prediction method according to a first embodiment of the present invention.

FIG. 2 is a short circuit probability calculation unit 2 in the first embodiment.
It is a schematic diagram showing the structure of the database 6 used in.

FIG. 3 is a schematic diagram showing graphic data of a virtual mask pattern used in calculation of a virtual short circuit rate.

FIG. 4 is a flowchart showing an algorithm for calculating a virtual short circuit rate.

FIG. 5 is a flowchart showing a process in which a virtual pattern element is short-circuited by a virtual foreign substance.

FIG. 6 is a function f _i (x) and a function g _i (x) which are virtual short-circuit rates shown for each size of foreign matter and the number of foreign matter measured.
It is a schematic diagram showing an example of.

FIG. 7 is a functional block diagram showing a configuration of a semiconductor device yield prediction device for carrying out a semiconductor device yield prediction method according to a second embodiment of the present invention.

FIG. 8 is a short circuit probability correction unit 1 in the second embodiment.
It is a schematic diagram showing the composition of database 10 used for 0.

FIG. 9 is a schematic diagram showing a function h _i (x) and a function f _i (x) showing the relationship between the size of the foreign matter and the short-circuit rate obtained from the actual measurement results.

FIG. 10 is a schematic diagram showing a configuration of a database 6 used by the short circuit probability calculation means 2 in the second embodiment.

FIG. 11 is a functional block diagram of a conventional semiconductor device yield prediction system.

[Explanation of symbols]

1 pattern management means 2 short-circuit probability calculation means 3 foreign matter number calculation means 4 short-circuit number calculation means 5 yield calculation means 6 database 7 keyboard 8 display 9 short-circuit probability correction means 10 database 100 field 101 for storing product name 101 semiconductor device name storage Field 102 Field for storing contour data of mask pattern 103 Field for storing minimum width between pattern elements 104 Field for storing movement amount used by short-circuit probability correcting means 9

Claims (11)

[Claims] 1. A mask pattern used for manufacturing the first semiconductor chip is shown in a virtual plane having the same shape as that of the first semiconductor chip, and a virtual foreign substance placed on the virtual plane shows the mask pattern. A short-circuit probability calculating step of calculating the probability that the at least two independent pattern elements are simultaneously short-circuited by at least two independent pattern elements constituting each of the virtual foreign particles, and the step of using the mask pattern, or A foreign matter number measuring step of measuring the size of the foreign matter deposited on the second semiconductor chip and the number of the foreign matter per unit area in the semiconductor manufacturing apparatus used before and after the step of using the mask pattern; The probability of short circuit in the first semiconductor chip calculated in the probability calculation process and the second half measured in the foreign substance number measurement process. The number of foreign substances in the body chips multiplied per size of the foreign matter, the yield prediction method of a semiconductor device including a short number calculation step of calculating the number of pattern elements each other are short-circuited by the unit area per of the first semiconductor chip. 2. The number of times the virtual foreign matter is overlapped with at least two independent pattern elements at the same time in the short-circuit probability calculation process, in which the virtual foreign matter is rectangular and the virtual foreign matter is moved at equal intervals on a virtual plane. 2. The yield prediction method for a semiconductor device according to claim 1, wherein the probability that the at least two independent pattern elements are short-circuited is calculated by dividing by the virtual number of movements of the foreign matter. 3. A step of using a mask pattern is a lithography step, a step before the step of using the mask pattern is a cleaning step and a deposited film forming step, and a step after the step of using the mask pattern is an etching step. The semiconductor device yield prediction method according to claim 1. 4. Data of one mask pattern is extracted from a database storing data showing all mask patterns used in the manufacture of the first semiconductor chip,
Showing one mask pattern in a virtual plane having the same shape as that of the semiconductor chip, and a virtual foreign substance placed on the virtual plane simultaneously overlaps with at least two independent pattern elements constituting the one mask pattern. Before and after the step of using the one mask pattern or the step of using the one mask pattern, a short circuit probability calculating step of calculating the probability of short circuit between the at least two independent pattern elements for each size of the virtual foreign matter. In the semiconductor manufacturing apparatus used in the step of measuring the number of foreign particles adhering to the second semiconductor chip and the number of foreign particles per unit area in the semiconductor manufacturing apparatus; The probability of short circuit in the first semiconductor chip and the foreign matter in the second semiconductor chip measured in the foreign matter number measuring process. And a number of short circuits for calculating the number of short-circuiting pattern elements per unit area of the first semiconductor chip by multiplying the number by the size of the foreign matter, all of which are used in the manufacturing of the first semiconductor chip. After repeating the short circuit probability calculation process, the foreign substance number measurement process, and the short circuit number calculation process for the mask pattern, the short circuit number calculation process is performed for all mask patterns used in the manufacturing of the first semiconductor chip. The total number of pattern elements short-circuited per unit area on the first semiconductor chip obtained as described above is summed, and the total number of pattern elements short-circuited per unit area on the first semiconductor chip is manufactured. A semiconductor device yield prediction method including a yield calculation process of calculating a yield after completion. 5. A mask pattern used for manufacturing the first semiconductor chip is shown in a virtual plane having the same shape as that of the first semiconductor chip, and a virtual foreign substance placed on the virtual plane shows the mask pattern. A short circuit probability calculating step of calculating a probability that the at least two independent pattern elements are simultaneously short-circuited to form at least two independent pattern elements constituting each of the virtual foreign matter dimensions; and a short circuit probability calculating step The probability of short-circuiting in the first semiconductor chip is defined by the probability that pattern elements on the third semiconductor chip are actually short-circuited and the probability of short-circuiting in the third semiconductor chip calculated by the short-circuit probability calculation process. Before the step of using the mask pattern or the step of using the mask pattern In the semiconductor manufacturing apparatus used in the step of measuring the number of foreign particles adhering to the second semiconductor chip and the number of the foreign particles per unit area in the semiconductor manufacturing apparatus; The corrected short circuit probability in one semiconductor chip and the number of foreign particles in the second semiconductor chip measured in the foreign particle number measurement process are multiplied by the size of the foreign particles to obtain a unit area per unit area of the first semiconductor chip. A semiconductor device yield prediction method, comprising: a short-circuit number calculation process of calculating the number of short-circuits between pattern elements. 6. The probability of short-circuiting between pattern elements on a first semiconductor chip is calculated in the short-circuit probability calculation step, the short-circuit probability is shown on the vertical axis, and the size of a virtual foreign substance is shown on the horizontal axis. A first function is created, the probability that pattern elements are short-circuited on the third semiconductor chip is calculated in the short-circuit probability calculation process, the short-circuit probability is shown on the vertical axis, and the size of the virtual foreign substance is shown on the horizontal axis. To detect the probability that the pattern elements are actually short-circuited by the foreign matter actually attached to the third semiconductor chip,
A third function is shown in which the vertical axis indicates the probability of the actual short circuit and the horizontal axis indicates the dimension of the foreign matter, and the second function is translated in the horizontal axis direction, and the second function after the parallel translation is performed. The difference between the probability indicated by the function and the probability indicated by the third function is added for each size of the foreign matter, and the movement amount of the second function when the total value of the difference between the probabilities is minimized, In the short-circuit probability correction process, a fourth function is generated by translating the first function in the horizontal axis direction by the movement amount of the second function when the total value of the probability differences is minimized, The number of foreign matter in the second semiconductor chip is measured for each foreign matter size in the foreign matter number measurement process, and a fifth function is created in which the vertical axis indicates the number of foreign matter and the horizontal axis indicates the foreign matter size. The fourth function and the fifth function are multiplied in the short circuit number calculation process. Item 6. A semiconductor device yield prediction method according to Item 5. 7. The data of one mask pattern is extracted from a database storing data showing all mask patterns used in the manufacture of the first semiconductor chip,
Showing one mask pattern in a virtual plane having the same shape as that of the semiconductor chip, and a virtual foreign substance placed on the virtual plane simultaneously overlaps with at least two independent pattern elements constituting the one mask pattern. A short circuit probability calculating step of calculating a probability of short circuit between the at least two independent pattern elements for each size of the virtual foreign matter; and a short circuit probability in the first semiconductor chip calculated in the short circuit probability calculating step. A short-circuit probability correction step of correcting with a difference between a probability that pattern elements on the third semiconductor chip are actually short-circuited and a short-circuit probability in the third semiconductor chip calculated by the short-circuit probability calculation step; On the second semiconductor chip in the semiconductor manufacturing apparatus used in the step of using the mask pattern or the steps before and after the step. Foreign matter number measuring step for measuring the size of the foreign matter adhered and the number of foreign matter per unit area, short circuit probability after correction in the first semiconductor chip corrected in the short circuit probability correcting step, and the foreign matter number measuring step And multiplying the number of foreign matters in the second semiconductor chip measured for each dimension of the foreign matter, and calculating the number of short-circuiting pattern elements per unit area of the first semiconductor chip. After repeating the short circuit probability calculation process, the short circuit probability correction process, the foreign matter number measurement process, and the short circuit number calculation process for all mask patterns used in the manufacture of the first semiconductor chip, the first Patterns per unit area on the first semiconductor chip obtained in the short circuit number calculation process for all mask patterns used in the manufacture of semiconductor chips. Yield prediction of a semiconductor device including a yield calculation step of totaling the number of short-circuited elements and calculating the yield after manufacturing from the total number of short-circuited pattern elements per unit area on the first semiconductor chip Method. 8. A mask pattern used for manufacturing the first semiconductor chip is shown in a virtual plane having the same shape as that of the first semiconductor chip, and a virtual foreign substance placed on the virtual plane shows the mask pattern. Short-circuit probability calculating means for calculating, for each size of the virtual foreign matter, a probability that the at least two independent pattern elements simultaneously overlap with at least two independent pattern elements constituting the short-circuit, and a step of using the mask pattern or Foreign matter number measuring means for measuring the size of the foreign matter deposited on the second semiconductor chip and the number of the foreign matter per unit area in the semiconductor manufacturing apparatus used before and after the step of using the mask pattern; The probability of short circuit in the first semiconductor chip calculated by the probability calculating means and the second half measured by the foreign matter number measuring means. A yield prediction device for a semiconductor device, comprising: a number of short-circuits calculating means for calculating the number of short-circuits between pattern elements per unit area of the first semiconductor chip by multiplying the number of foreign matters in the body chip for each size of the foreign matter. . 9. A database storing data showing all mask patterns used in the manufacture of the first semiconductor chip, and data of one mask pattern extracted from the database and having the same shape as the first semiconductor chip. The one mask pattern is shown in a virtual plane, and the virtual foreign matter placed on the virtual plane is simultaneously overlapped with at least two independent pattern elements constituting the one mask pattern, and the at least two independent pattern elements are simultaneously formed. Short-circuit probability calculating means for calculating the probability that pattern elements are short-circuited for each size of the virtual foreign matter, and semiconductor manufacturing used in the step of using the one mask pattern or the steps before and after the step of using the one mask pattern. The size of the foreign matter deposited on the second semiconductor chip in the device and the number of the foreign matter per unit area Foreign matter number measuring means for measuring the number of foreign matter in the first semiconductor chip calculated by the short circuit probability calculating means and the number of foreign matter in the second semiconductor chip measured by the foreign matter number measuring means. For each mask pattern used in the manufacturing of the first semiconductor chip, short-circuit number calculation means for calculating the number of pattern elements short-circuited per unit area of the first semiconductor chip, Repeatedly operating the short-circuit probability calculation means, the foreign matter number measurement means and the short-circuit number calculation means,
The total number of short-circuiting pattern elements per unit area of the first semiconductor chip obtained by the short-circuit number calculation means for all mask patterns used in the manufacture of the first semiconductor chip is summed to obtain the first (3) A yield prediction device for a semiconductor device, comprising: a yield calculation means for displaying the yield after the end of manufacturing from the total number of short-circuiting pattern elements per unit area on the semiconductor chip. 10. A mask pattern used for manufacturing the first semiconductor chip is shown in a virtual plane having the same shape as the first semiconductor chip, and a virtual foreign object placed on the virtual plane shows the mask pattern. Said at least two overlapping at least two independent pattern elements constituting at the same time
A short circuit probability calculating means for calculating the probability of short circuit between two independent pattern elements for each dimension of the virtual foreign matter; and a short circuit probability in the first semiconductor chip calculated by the short circuit probability calculating means, A short-circuit probability correcting unit that corrects by a difference between a probability that pattern elements on a semiconductor chip are actually short-circuited and a short-circuit probability in the third semiconductor chip calculated by the short-circuit probability calculating unit; and a step of using the mask pattern Or a foreign matter number measuring means for measuring the size of the foreign matter deposited on the second semiconductor chip and the number of the foreign matter per unit area in the semiconductor manufacturing apparatus used before and after the step of using the mask pattern; The short-circuit probability after correction in the first semiconductor chip calculated by the short-circuit probability correction means and measured by the foreign matter number measurement means A semiconductor device comprising: a number of short-circuits calculating means for multiplying the number of foreign particles in the second semiconductor chip for each size of the foreign particles, and calculating the number of short-circuits between pattern elements per unit area of the first semiconductor chip. Yield prediction device. 11. A database storing data showing all mask patterns used in the manufacture of the first semiconductor chip, and data of one mask pattern extracted from the database and having the same shape as the first semiconductor chip. The one mask pattern is shown in a virtual plane, and the virtual foreign matter placed on the virtual plane is simultaneously overlapped with at least two independent pattern elements constituting the one mask pattern, and the at least two independent pattern elements are simultaneously formed. On the third semiconductor chip, the short-circuit probability calculation means for calculating the probability of short-circuit between pattern elements for each size of the virtual foreign matter and the short-circuit probability in the first semiconductor chip calculated by the short-circuit probability calculation means The third semiconductor chip calculated by the probability that the pattern elements of the above are actually short-circuited and the short-circuit probability calculation means. A short circuit probability correcting means for correcting the difference between the short circuit probability and a short circuit probability in the semiconductor manufacturing apparatus used in the step of using the one mask pattern or the steps before and after the step. Foreign matter number measuring means for measuring the size and the number of foreign matter per unit area; short circuit probability after correction in the first semiconductor chip corrected by the short circuit probability correcting means and the foreign matter number measuring means A short-circuit number calculating means for multiplying the number of foreign particles in the second semiconductor chip for each size of the foreign particles and outputting the number of short-circuits between pattern elements per unit area of the first semiconductor chip; For all mask patterns used in the manufacture of chips, the short-circuit probability calculation means, the short-circuit probability correction means, the foreign matter number measurement means, and the short-circuit number calculation The means is repeatedly operated, the number of pattern elements short-circuited per unit area of the first semiconductor chip is summed, and the sum of the number of pattern elements short-circuited per unit area on the first semiconductor chip is calculated. A yield prediction device for a semiconductor device, comprising: a yield calculation means for displaying a yield after manufacturing is completed.