CN113268435A - Bus verification platform - Google Patents
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- CN113268435A CN113268435A CN202110821816.0A CN202110821816A CN113268435A CN 113268435 A CN113268435 A CN 113268435A CN 202110821816 A CN202110821816 A CN 202110821816A CN 113268435 A CN113268435 A CN 113268435A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
- G06F11/3672—Test management
- G06F11/3676—Test management for coverage analysis
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
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- G06F11/3684—Test management for test design, e.g. generating new test cases
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Abstract
The invention relates to a bus verification platform, comprising: a single sequencer, a master agent, a slave agent, a comparator, an interconnect environment, an interconnect monitor, and an interconnect comparator; the host agent comprises a host driver and a host monitor; the slave agent comprises a slave driver and a slave monitor; a single sequencer for providing test sequences for the master driver and the slave driver; the comparator is used for receiving and comparing the transactions sent by the master monitor and the slave monitor; the interconnection environment is used for simulating interconnection of buses and realizing information interaction of a plurality of hosts and a plurality of slaves, and is respectively connected with the host agent and the slave agent through virtual interfaces; the interconnection monitor is used for collecting transactions of a plurality of hosts and a plurality of slaves in an interconnection environment and sending the transactions to the interconnection comparator; the interconnection comparator is used for judging whether the transaction of the interconnection host agent and the interconnection slave agent in the interconnection environment conforms to the AXI bus protocol. The invention improves the bus verification efficiency.
Description
Technical Field
The invention relates to the technical field of bus verification, in particular to a bus verification platform.
Background
The high integration of the chip and the reduction of the process flow make the chip verification occupy more time in the whole flow sheet flow. This development has driven the work of validation methodologies. The most common verification methods are FPGA verification, directed stimulus verification, and constrained randomized verification. However, FPGA verification cannot be quickly located after a problem is found, and large-scale complex designs require more board resources, increasing capital investment. The directional excitation test requires listing all items to be tested and manually checking the verification results after the simulation is completed. Therefore, constrained randomization tests are increasingly attractive and UVM verification methodology is increasingly widely used as a general theory and library file. At present, the time and validation efficiency required by the UVM validation method need to be improved.
Disclosure of Invention
The invention aims to provide a bus verification platform, which improves the bus verification efficiency.
In order to achieve the purpose, the invention provides the following scheme:
a bus validation platform comprising: a single sequencer, a master agent, a slave agent, a comparator, an interconnect environment, an interconnect monitor, and an interconnect comparator;
the host agent comprises a host driver and a host monitor;
the slave agent comprises a slave driver and a slave monitor;
the single sequencer is used for providing a test sequence for the host driver and the slave driver;
the comparator is used for receiving and comparing the transactions sent by the master monitor and the slave monitor;
the interconnection environment is used for simulating interconnection of buses and realizing information interaction of a plurality of hosts and a plurality of slaves, and is respectively connected with the host agent and the slave agent through virtual interfaces;
the interconnection monitor is used for collecting transactions of a plurality of hosts and a plurality of slaves in the interconnection environment and sending the transactions to the interconnection comparator;
and the interconnection comparator is used for judging whether the transaction of the interconnection host agent and the interconnection slave agent in the interconnection environment conforms to the AXI bus protocol.
Optionally, the bus verification platform further comprises a scenario layer and a test layer;
the scene layer is used for generating a transaction, and the transaction simulates a data packet in the data exchange process of the physical protocol;
the test layer is used for constructing a test case, receiving the affair generated by the scene layer, creating a test sequence according to the affair and the test case generated by the scene layer, and sending the test sequence to the single sequencer.
Optionally, the host agent further includes a host port configurator configured to configure the number of hosts in the host agent.
Optionally, the slave agent further includes a slave port configurator configured to configure the number of slaves in the slave agent.
Optionally, the host agent further includes a first coverage collector connected to the host monitor, the first coverage collector configured to receive a transaction sent by the host monitor.
Optionally, the slave agent further comprises a second coverage collector connected with the slave monitor, the second coverage collector being configured to receive the transaction sent by the slave monitor.
Optionally, the interconnect environment includes a plurality of interconnect master agents, a plurality of interconnect slave agents, an interconnect configurator, and a stimulus generator;
the interconnection configurator configures the interconnection host agents with the same quantity according to the quantity of the host agents externally connected with the interconnection environment, and configures the interconnection slave agents with the same quantity according to the quantity of the slave agents externally connected with the interconnection environment;
the plurality of interconnected master agents and the plurality of interconnected slave agents are connected with the excitation generator, and information transmission between the plurality of interconnected master agents and the plurality of interconnected slave agents is achieved through the excitation generator.
Optionally, the implementing, by the stimulus generator, information transmission between the plurality of interconnected master agents and the plurality of interconnected slave agents specifically includes:
acquiring signals corresponding to the slave agents by utilizing the interconnected slave agents through a virtual interface, and packaging the signals into a first transaction to be transmitted to the excitation generator;
generating a first transaction received with said stimulus generator to a corresponding said interconnected host agent;
converting the received first transaction into an electric signal by using the interconnected host agent, and sending the electric signal to the corresponding host agent through a virtual interface;
collecting a response signal sent by the corresponding host agent through a virtual interface by using the interconnected host agent, and packaging the response signal into a second transaction to be sent to the excitation generator;
sending the received second transaction to the corresponding interconnect slave agent using the stimulus generator;
and sending the received second transaction to the corresponding slave agent through the virtual interface by utilizing the interconnected slave agents.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
according to the bus verification platform, the bus verification platform is constructed by the single sequencer, the host agent, the slave agent, the comparator, the interconnection environment, the interconnection monitor and the interconnection comparator, the bus verification platform can be reused, and the single sequencer inputs test sequences according to different requirements, so that the verification efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a schematic diagram of a bus verification platform according to the present invention;
fig. 2 is a schematic diagram of an interconnection environment structure according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a bus verification platform, which improves the bus verification efficiency.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Fig. 1 is a schematic structural diagram of a bus validation platform according to the present invention, and as shown in fig. 1, the bus validation platform includes: a single sequencer 10, a master agent 20, a slave agent 30, a comparator 40, an interconnect environment 50, an interconnect monitor 100, and an interconnect comparator 110.
The host agent 20 includes a host driver 202 and a host monitor 204.
The slave agent 30 includes a slave driver 302 and a slave monitor 304.
The single sequencer 10 is used to provide a test sequence 80 for both the master driver 202 and the slave driver 302.
The comparator 40 is used to receive and compare transactions sent by the master monitor 204 and the slave monitor 304.
The interconnection environment 50 is used for simulating interconnection of buses to realize information interaction between a plurality of hosts and a plurality of slaves, and the interconnection environment 50 is connected with the host agent 20 and the slave agent 30 through virtual interfaces respectively.
The interconnection monitor 100 is configured to collect transactions of multiple masters and multiple slaves in the interconnection environment 50 and send the transactions to the interconnection comparator 110.
The interconnect comparator 110 is configured to determine whether a transaction of an interconnect master agent and an interconnect slave agent in the interconnect environment 50 conforms to an AXI bus protocol.
The bus verification platform further comprises a scene layer and a test layer;
the scene layer is used to generate transactions 60, which transactions 60 simulate data packets during data exchange of the physical protocol.
The test layer is configured to construct a test case 70, receive the transaction 60 generated by the scenario layer, create a test sequence 80 according to the transaction 60 and the test case 70 generated by the scenario layer, and send the test sequence 80 to the single sequencer 10.
The host agent 20 further comprises a host port configurator 201 for configuring the number of hosts in the host agent 20.
The slave agent 30 further comprises a slave port configurator 302 for configuring the number of slaves in the slave agent 30.
The host agent 20 further comprises a first coverage collector 203, the first coverage collector 203 is connected with the host monitor 204, and the first coverage collector 203 is used for receiving the transaction sent by the host monitor 204.
The slave agent 30 further comprises a second coverage collector 303, the second coverage collector 303 is connected with the slave monitor 304, and the second coverage collector 303 is used for receiving the transaction sent by the slave monitor 304.
Fig. 2 is a schematic structural diagram of an interconnect environment 50 according to the present invention, and as shown in fig. 2, the interconnect environment 50 includes a plurality of interconnect master agents, a plurality of interconnect slave agents, an interconnect configurator, and a stimulus generator.
The interconnection configurator configures the same number of interconnection master agents according to the number of the master agents 20 externally connected to the interconnection environment 50, and configures the same number of interconnection slave agents according to the number of the slave agents 30 externally connected to the interconnection environment 50.
The plurality of interconnected master agents and the plurality of interconnected slave agents are connected with the excitation generator, and information transmission between the plurality of interconnected master agents and the plurality of interconnected slave agents is achieved through the excitation generator.
The implementing, by the stimulus generator, information transmission between the plurality of interconnected master agents and the plurality of interconnected slave agents specifically includes:
signals corresponding to the slave agent 30 are collected by the interconnected slave agents through a virtual interface, and the signals are packaged into a first transaction to be sent to the excitation generator.
Generating a first transaction received with said stimulus generator to a corresponding said interconnected host agent;
the interconnected host agents are used to convert the received first transaction into an electrical signal and send the electrical signal to the corresponding host agent 20 through a virtual interface.
And collecting the corresponding response signal sent by the host agent 20 through the virtual interface by using the interconnected host agents, packaging the response signal into a second transaction, and sending the second transaction to the excitation generator.
Sending the received second transaction to the corresponding interconnect slave agent using the stimulus generator.
The received second transaction is sent to the corresponding slave agent 30 via the virtual interface using the interconnect slave agent.
The main technical means of the invention is to establish a bus Verification platform by adopting a UVM (Universal Verification method component) Verification Methodology, thereby improving the efficiency of bus Verification. The right-hand body of the integrated verification platform is packaged into an integrated verification environment as shown in fig. 1, which includes the components of the general verification methodology used in the various build environments.
The global bus validation platform (Top) includes a master driver 202(master _ driver), a master monitor 204(master _ monitor), a Slave driver 302(Slave _ driver), a Slave monitor 304(Slave _ monitor), a virtual interface (vif), and a comparator 40(checker) component. In the connection relationship between the components, the entire verification environment is packaged by the verification platform, and then the single sequencer 10, the host agent 20, the slave agent 30, and the comparator 40 are packaged by the entire verification environment. The host agent 20 includes components such as a host driver 202, a host monitor 204, and a virtual interface. The slave agent 30 includes components such as a slave driver 302, a slave monitor 304, and a virtual interface. The Single sequencer 10(Single _ sequence) functions to provide test sequences for both the master driver 202 and the slave driver 302. The virtual interfaces are used to connect the host driver 202, the slave driver 302, the interconnect environment 50, and the Design Under Test (DUT) 90, respectively. The interconnection configurator and the port configurator are used for providing configuration information such as the number of the hosts and the number of the slaves for the integral verification platform. The coverage collector is used for collecting coverage information, including code coverage and function coverage.
The left part of the overall verification environment is a part of the overall verification platform and comprises a scene layer and a test layer. The scene layer is the place where transactions (transactions) are generated that simulate packets during data exchange of the physical protocol, and the test sequences (sequences) provide different test sequences 80 to a single sequencer 10. The test layer is the place where various test cases (testcases) are built.
One test sequence is created to correspond to one test case, and a plurality of test cases are needed for creating a plurality of test sequences. For a bus protocol, the packet format is fixed, and thus the transaction is unique. Test sequences sent to a single sequencer 10 are sent by a single transaction completion. Different test cases are switched in the top-layer design code of the overall verification platform, so that different test sequences are used and sent to the single sequencer 10, injection of different test sequences is realized, and verification of different test stimuli is completed.
Data transmission relationships are expressed in two categories.
When the bus is a single master and a single slave: the working principle of the validation platform is that the test sequence generates transactions through a single sequencer 10 to the master driver 202 and through a single sequencer 10 to the slave driver 302. Subsequently, the master driver 202 and the slave monitor 304 process the transaction and drive to the virtual interface. The host monitor 204 converts the sampled electrical signal into a transaction that is stored in an internal mailbox and then passed to the comparator 40. The electric signal output results of the master monitor 204 and the slave monitor 304 are compared automatically through the comparator 40, and the verification result output is completed. While the transaction is passed into a coverage collector (first coverage collector 203) for coverage sampling.
When the bus is a multi-master multi-slave bus: the interconnection environment 50 simulates interconnection of buses, and information interaction of multiple hosts and multiple slaves is completed through the interconnection environment 50, so that the arbitration and routing problems are solved. The interconnect monitor 100 is responsible for collecting transactions of the interconnect slave agents and the interconnect host agents in the interconnect structure, and the transactions are transmitted to the interconnect comparator 110 to check whether the outputs of the interconnect slave agents and the interconnect host agents in the interconnect structure conform to the AXI bus protocol, and to determine whether the interconnect environment 50 normally operates.
The interconnect environment 50 is configured as shown in fig. 2, and its main function is to solve the arbitration and routing problem when multiple masters and multiple slaves transmit. The transaction is transmitted through master agent 20 to slave agent 30, and slave agent 30 returns a response to the corresponding master agent 20.
The interconnect configurator performs configuration of interconnect environment 50. The corresponding number of interconnected slave agents within the interconnected environment 50 is configured according to the number of master agents 20 externally connected to the interconnected environment 50, and similarly, the number of interconnected master agents may also be configured according to the number of externally connected slave agents 30. The internal structure of interconnect environment 50 shows that the interconnect slave agent samples the signals of the virtual interface, packages them into transactions, and transmits them to the corresponding interconnect master agent through the stimulus generator. The interconnect host agent converts the transaction into an electrical signal, driving the virtual interface. And then the interconnection host agent samples the response signals returned from the virtual interface, packages the response signals into transactions, transmits the transactions to the corresponding interconnection slave agent through the excitation generator, and the interconnection slave agent drives the response signals to the virtual interface. When the bus is multi-master multi-slave, the interconnect environment 50 will transmit the transaction to the interconnect monitor 100, the interconnect monitor 100 will send the transaction to the interconnect comparator 110, and the interconnect comparator 110 will perform the automated comparison.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (8)
1. A bus validation platform, comprising: a single sequencer, a master agent, a slave agent, a comparator, an interconnect environment, an interconnect monitor, and an interconnect comparator;
the host agent comprises a host driver and a host monitor;
the slave agent comprises a slave driver and a slave monitor;
the single sequencer is used for providing a test sequence for the host driver and the slave driver;
the comparator is used for receiving and comparing the transactions sent by the master monitor and the slave monitor;
the interconnection environment is used for simulating interconnection of buses and realizing information interaction of a plurality of hosts and a plurality of slaves, and is respectively connected with the host agent and the slave agent through virtual interfaces;
the interconnection monitor is used for collecting transactions of a plurality of hosts and a plurality of slaves in the interconnection environment and sending the transactions to the interconnection comparator;
and the interconnection comparator is used for judging whether the transaction of the interconnection host agent and the interconnection slave agent in the interconnection environment conforms to the AXI bus protocol.
2. The bus validation platform of claim 1, further comprising a scenario layer and a test layer;
the scene layer is used for generating a transaction, and the transaction simulates a data packet in the data exchange process of the physical protocol;
the test layer is used for constructing a test case, receiving the affair generated by the scene layer, creating a test sequence according to the affair and the test case generated by the scene layer, and sending the test sequence to the single sequencer.
3. The bus validation platform of claim 1, wherein the host agent further comprises:
and the host port configurator is used for configuring the number of the hosts in the host agent.
4. The bus validation platform of claim 1, wherein the slave agent further comprises:
and the slave port configurator is used for configuring the number of slaves in the slave agent.
5. The bus validation platform of claim 1, wherein the host agent further comprises a first coverage collector coupled to the host monitor, the first coverage collector configured to receive transactions sent by the host monitor.
6. The bus validation platform of claim 1, wherein the slave agent further comprises a second coverage collector coupled to the slave monitor, the second coverage collector configured to receive transactions sent by the slave monitor.
7. The bus validation platform of claim 1, wherein the interconnect environment comprises a plurality of interconnect master agents, a plurality of interconnect slave agents, an interconnect configurator, and a stimulus generator;
the interconnection configurator configures the interconnection host agents with the same quantity according to the quantity of the host agents externally connected with the interconnection environment, and configures the interconnection slave agents with the same quantity according to the quantity of the slave agents externally connected with the interconnection environment;
the plurality of interconnected master agents and the plurality of interconnected slave agents are connected with the excitation generator, and information transmission between the plurality of interconnected master agents and the plurality of interconnected slave agents is achieved through the excitation generator.
8. The bus validation platform of claim 1, wherein the enabling of information transfer between the plurality of interconnected master agents and the plurality of interconnected slave agents via the stimulus generator specifically comprises:
acquiring signals corresponding to the slave agents by utilizing the interconnected slave agents through a virtual interface, and packaging the signals into a first transaction to be transmitted to the excitation generator;
generating a first transaction received with said stimulus generator to a corresponding said interconnected host agent;
converting the received first transaction into an electric signal by using the interconnected host agent, and sending the electric signal to the corresponding host agent through a virtual interface;
collecting a response signal sent by the corresponding host agent through a virtual interface by using the interconnected host agent, and packaging the response signal into a second transaction to be sent to the excitation generator;
sending the received second transaction to the corresponding interconnect slave agent using the stimulus generator;
and sending the received second transaction to the corresponding slave agent through the virtual interface by utilizing the interconnected slave agents.
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| CN202110821816.0A CN113268435A (en) | 2021-07-21 | 2021-07-21 | Bus verification platform |
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| CN106326056A (en) * | 2016-08-26 | 2017-01-11 | 中国电子科技集团公司第三十八研究所 | Reusable WISHBONE bus protocol verification platform and verification method thereof |
| US20180060453A1 (en) * | 2016-08-24 | 2018-03-01 | Raytheon Company | Universal verification methodology (uvm) register abstraction layer (ral) painter |
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- 2021-07-21 CN CN202110821816.0A patent/CN113268435A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20180060453A1 (en) * | 2016-08-24 | 2018-03-01 | Raytheon Company | Universal verification methodology (uvm) register abstraction layer (ral) painter |
| CN106326056A (en) * | 2016-08-26 | 2017-01-11 | 中国电子科技集团公司第三十八研究所 | Reusable WISHBONE bus protocol verification platform and verification method thereof |
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Application publication date: 20210817 |