CN113268104A - Clock counting synchronization method and device - Google Patents
Clock counting synchronization method and device Download PDFInfo
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- CN113268104A CN113268104A CN202110585580.5A CN202110585580A CN113268104A CN 113268104 A CN113268104 A CN 113268104A CN 202110585580 A CN202110585580 A CN 202110585580A CN 113268104 A CN113268104 A CN 113268104A
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Abstract
A clock counting synchronization method and device, wherein the method includes the following steps, in the first operation stage of the system, operating the low frequency clock unit, operating the high frequency clock unit at the same time, at the time point t1 when the system switches from the first operation stage to the energy-saving stage, stopping operating the high frequency clock unit, at the time point t2 when the system switches from the energy-saving stage to the second operation stage, detecting whether the time tau passing from t1 satisfies the condition: and when the tau meets the condition for the first time, starting to run the high-frequency clock unit, compensating an integer period value to the counting result of the high-frequency clock unit according to the value of the tau, and synchronizing the system clock according to the compensated counting result of the high-frequency clock unit. By switching to the low-frequency clock unit with low energy consumption, the power consumption of the system in the off state or the energy-saving state can be saved, and the running state of the system can be switched at any time point in any period.
Description
Technical Field
The invention relates to the field of chip clock calculation, in particular to a clock counting synchronization method with low power consumption.
Background
Systems running on a chip need to obtain the system run time, typically relying on an on-chip counting module, which typically runs at a higher frequency to achieve high precision time granularity. In order to reduce the function after the system is in a sleep state, the clock supply of the counting module is stopped, so that the counting module does not work any more. Over time, the runtime cannot be updated in time when the system resumes operation. In order to solve the problem, an rtc (real time clock) chip is generally used in the industry, and after the chip is dormant, the rtc chip continues to assist the counting module to count, and after the chip resumes running again, the counting module is informed of the count value in the dormant period, so as to achieve the purpose of compensation. This solution causes a pressure on the cost and also errors in the data synchronization. In order to further optimize the scheme, a low-frequency clock is introduced so as to enable the counting module to work continuously after the high-frequency clock is turned off in the chip sleep period, and thus after the chip resumes running again, the counting module can directly accumulate the count value in the sleep period into the system. However, such a counting scheme has a potential risk point that a little time is lost in the process of switching the frequency before the counting module sleeps, and although the granularity is small, the lost time is still obvious after the counting module is accumulated in a month. In order to solve the technical problem, a clock counting and synchronizing device is designed in the scheme.
Disclosure of Invention
Therefore, a clock counting synchronization method and a clock counting synchronization device are needed to solve the problem of energy consumption under the condition of clock signal counting;
to achieve the above object, the inventor provides a clock count synchronization method, which includes the following steps, during a first operation phase of a system, operating a low frequency clock unit while operating a high frequency clock unit, stopping operating the high frequency clock unit at a time t1 when the system switches from the first operation phase to a power saving phase, and detecting whether a time τ elapsed from t1 satisfies the following condition at a time t2 when the system switches from the power saving phase to a second operation phase:
τ＝n*C
wherein C is: the least common multiple of the period of the low-frequency clock unit and the period of the high-frequency clock unit; n is a natural number;
when tau meets the above condition for the first time, starting to run the high-frequency clock unit, simultaneously compensating an integer period value to the counting result of the high-frequency clock unit according to the value of tau, and synchronizing the system clock according to the compensated counting result of the high-frequency clock unit.
A clock count synchronization method includes the steps of operating a low frequency clock unit while operating a high frequency clock unit in a first operation stage of a system, stopping the operation of the high frequency clock unit at a time t1 when the system switches from the first operation stage to a power saving stage, calculating a first time t3 after t2 at a time t2 when the system switches from the power saving stage to a second operation stage,
t3-t1＝τ
τ＝n*C
wherein C is: the least common multiple of the period of the low-frequency clock unit and the period of the high-frequency clock unit; n is a natural number;
when the time point t3 is reached, the high frequency clock unit starts to run, meanwhile, according to the value of tau, the counting result of an integer period value to the high frequency clock unit is compensated, and according to the compensated counting result of the high frequency clock unit, the system clock is synchronized.
Specifically, the clock signal of the low frequency clock unit is not at the rising edge nor at the falling edge at the time t 3.
Specifically, the clock signal of the low frequency clock unit is not at the rising edge nor at the falling edge at the time t 1.
Specifically, the clock signal of the low frequency clock unit is not at the rising edge nor at the falling edge at the time t 2.
Specifically, the period of the low frequency clock unit is an integer multiple of the period of the high frequency clock unit.
Specifically, the period of the low frequency clock unit is not an integer multiple of the period of the high frequency clock unit.
Further, the method also comprises the following steps: the common mode unit pre-configures the low frequency clock unit and the high frequency clock unit, wherein configuration parameters include C.
A clock counting synchronization device comprises a low-frequency clock unit, a high-frequency clock unit and a clock switching unit; the low frequency clock unit and the high frequency clock unit operate simultaneously in a first operation stage of the system,
the clock switching unit is used for stopping the operation of the high-frequency clock unit at the time t1 when the system is switched from the first operation stage to the energy-saving stage, and detecting whether the time tau elapsed from t1 meets the following condition at the time t2 when the system is switched from the energy-saving stage to the second operation stage:
τ＝n*C
wherein C is: the least common multiple of the period of the low-frequency clock unit and the period of the high-frequency clock unit; n is a natural number; when tau meets the above condition for the first time, the high frequency clock unit starts to run,
or:
the clock switching unit is used for calculating a first time point t3 after t2, which meets the following condition:
t3-t1＝τ
τ＝n*C
wherein C is: the least common multiple of the period of the low-frequency clock unit and the period of the high-frequency clock unit; n is a natural number;
when the time t3 is reached, the high frequency clock unit starts to run,
the clock switching unit also compensates a counting result from an integer period value to the high-frequency clock unit according to the value of tau, and synchronizes the system clock according to the compensated counting result of the high-frequency clock unit.
Further, the device also comprises a common mode unit, wherein the common mode unit is used for pre-configuring the low-frequency clock unit and the high-frequency clock unit, and configuration parameters comprise C.
By the technical scheme, the power consumption of the system in the closed state or the energy-saving state can be saved by operating the low-frequency clock unit with low energy consumption instead, and the operating state of the system can be switched at any time point in any period regardless of whether the upper and lower edges of the low-frequency clock unit and the high-frequency clock unit have corresponding relation with the opening and closing of the system by setting the integral multiple duration of the least common multiple of the low-frequency clock unit and the high-frequency clock unit.
Drawings
FIG. 1 is a flowchart of a clock count synchronization method according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a clock count synchronization method according to another embodiment of the present invention;
FIG. 3 is a timing diagram according to an embodiment of the present invention;
fig. 4 is a block diagram of a clock counting synchronization apparatus according to an embodiment of the present invention.
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 1, a clock count synchronization method is introduced, which includes a step S101 of operating a low frequency clock unit and simultaneously operating a high frequency clock unit in a first operation stage of a system. The system may be a hardware device such as a personal computer, a desktop, a kiosk, a tablet, or may refer to software, an operating system, or the like running on a hardware device such as a personal computer, a desktop, a kiosk, a tablet, or the like. S102 stops operating the high frequency clock unit at time t1 when the system switches from the first operation stage to the power saving stage. The energy saving stage has the characteristic of saving energy consumption relative to the first operation stage or the second operation stage described later, whether the energy saving stage is performed or not may depend on whether the system needs to reduce consumption or not, and whether the system enters the energy saving state or not may be determined, but the step S102 is performed as long as the system enters the energy saving state. S103, at a time t2 when the system switches from the energy saving phase to the second operation phase, detects whether the time τ elapsed from t1 satisfies the following condition:
τ＝n*C
wherein C is: the least common multiple of the period of the low-frequency clock unit and the period of the high-frequency clock unit; n is a natural number;
when τ first satisfies the above condition, the high frequency clock unit starts to run. The step S103 is performed to find the nearest time point of the least common multiple integer after the time t2, so that the time length of the compensated high frequency clock unit can be determined in the shortest time after the power-on. Then, step S104 is performed to compensate an integer period value to the counting result of the high frequency clock unit according to the value of τ, and synchronize the system clock according to the compensated counting result of the high frequency clock unit. By the method, the system can be enabled to operate the low-frequency clock unit with low energy consumption in the energy-saving stage, the power consumption of the system in the closed state or the energy-saving state can be saved, and the operating state of the system can be switched at any time point in any period regardless of whether the upper edge and the lower edge of the low-frequency clock unit and the high-frequency clock unit have a corresponding relation with the opening and the closing of the system by finding the integral multiple time length of the least common multiple of the low-frequency clock unit and the high-frequency clock unit.
In another embodiment shown in fig. 2, we also introduce a clock count synchronization method, which is different in how to find the nearest point in time that is an integer multiple of the least common multiple after time t 2. Comprising the steps of S101 running a low frequency clock unit while running a high frequency clock unit in a first operation stage of the system, S102 stopping running the high frequency clock unit at a time t1 when the system switches from the first operation stage to a power saving stage, S105 calculating a first time t3 after t2 at a time t2 when the system switches from the power saving stage to a second operation stage,
t3-t1＝τ
τ＝n*C
wherein C is: the least common multiple of the period of the low-frequency clock unit and the period of the high-frequency clock unit; n is a natural number;
when the time t3 is reached, the high frequency clock unit starts to run. This step S105 is also used to find the closest point in time of the least common multiple integer after time t 2. At the same time or almost the same time when the high frequency clock unit starts to run, step S104 is performed to compensate an integer period value to the counting result of the high frequency clock unit according to the value of τ, and synchronize the system clock according to the compensated counting result of the high frequency clock unit. By the method, the system can be enabled to operate the low-frequency clock unit with low energy consumption in the energy-saving stage, the power consumption of the system in the closed state or the energy-saving state can be saved, and the operating state of the system can be switched at any time point in any period regardless of whether the upper edge and the lower edge of the low-frequency clock unit and the high-frequency clock unit have a corresponding relation with the opening and the closing of the system by finding the integral multiple time length of the least common multiple of the low-frequency clock unit and the high-frequency clock unit.
In some specific embodiments as shown in fig. 3, we can also see that our solution is to directly find the nearest time point of the least common multiple of the cycle after the power-on, without considering whether the phase of the low-frequency clock unit is consistent with the phase of the high-frequency clock unit, and also without considering whether the high-frequency clock unit and the low-frequency clock unit are both at the rising edge and the falling edge of the half cycle when the specific time point arrives. Also, the period of the low frequency clock unit may be set to be not an integral multiple of the period of the high frequency clock unit. Only two low-frequency and high-frequency clock chips are needed to complete the scheme. Thus, as shown in FIG. 3, the clock signal of the low frequency clock unit is neither at a rising nor a falling edge at time t 3. Similarly, as shown in fig. 3, the clock signal of the low frequency clock unit at the time t1 may not be at the rising edge or the falling edge. Likewise, as shown in fig. 3, the clock signal of the low frequency clock unit is not at the rising edge nor at the falling edge at the time t 2.
It can also be seen from the embodiment shown in fig. 3 that the clock signal of the low frequency clock unit is not at the rising edge nor at the falling edge at the time t 3. Similarly, as shown in fig. 3, the clock signal of the low frequency clock unit at the time t1 may not be at the rising edge or the falling edge. Likewise, as shown in fig. 3, the clock signal of the low frequency clock unit is not at the rising edge nor at the falling edge at the time t 2. The method is characterized in that the time point of the nearest common multiple of the minimum cycle after the computer is started is directly found, whether the phase of the low-frequency clock unit is consistent with that of the high-frequency clock unit or not is not required to be considered, and whether the high-frequency clock unit and the low-frequency clock unit are both in the rising edge and the falling edge of the half cycle when a specific time point arrives is also not required to be considered.
In other embodiments, the timing t1 and t2 is the rising or falling edge of the high frequency clock signal, and the phase of the high frequency clock signal at t3 is not required, since the on/off signal is likely to require the clock unit signal to trigger, which is typically a high frequency clock signal. The setting mode is simpler and more convenient, and the error probability is low.
In some other specific preferred embodiments, the period of the low frequency clock unit is an integer multiple of the period of the high frequency clock unit. Therefore, the integral multiple of the least common multiple of the period can be found more quickly after the time t2, because the least common multiple of the period of the low-frequency clock unit and the period of the high-frequency clock unit is the low-frequency clock unit in the example, the scheme is simpler in arrangement and smaller in error.
In a further embodiment, the method further comprises the steps of: the common mode unit pre-configures the low frequency clock unit and the high frequency clock unit, wherein configuration parameters include C. For example, a common-mode unit can be designed, which can be configured manually or calculated automatically, for correct synchronization of different clock parameters. The correction parameters of the device may be automatically calculated or configured by software. For example, 32KHz and 24MHz, C is the least common multiple of the technology period under two clocks, i.e., C ═ LCM (a, b), and a and b are the periods of the clocks at the frequencies of 32K and 24M, respectively.
In the embodiment shown in fig. 4, we also provide a clock counting synchronization apparatus, which includes a low frequency clock unit 400, a high frequency clock unit 401, and a clock switching unit 402; the low frequency clock unit 400 and the high frequency clock unit 401 operate simultaneously in a first phase of operation of the system,
the clock switching unit is used for stopping the operation of the high-frequency clock unit at the time t1 when the system is switched from the first operation stage to the energy-saving stage, and detecting whether the time tau elapsed from t1 meets the following condition at the time t2 when the system is switched from the energy-saving stage to the second operation stage:
τ＝n*C
wherein C is: the least common multiple of the period of the low-frequency clock unit and the period of the high-frequency clock unit; n is a natural number; when tau meets the above condition for the first time, the high frequency clock unit starts to run,
or:
the clock switching unit is used for calculating a first time point t3 after t2, which meets the following condition:
t3-t1＝τ
τ＝n*C
wherein C is: the least common multiple of the period of the low-frequency clock unit and the period of the high-frequency clock unit; n is a natural number;
when the time t3 is reached, the high frequency clock unit starts to run,
the clock switching unit also compensates a counting result from an integer period value to the high-frequency clock unit according to the value of tau, and synchronizes the system clock according to the compensated counting result of the high-frequency clock unit.
Further, a common mode unit 403 is included, and the common mode unit is used for pre-configuring the low frequency clock unit and the high frequency clock unit, where the configuration parameter includes C.
In some other further embodiments, the system is built in two clock units with clock frequencies of 32k and 24M. After the computer is started, software starts 32K and 24M clock units, the 32K and 24M clock units respectively start to work, according to the mathematical principle, when the 32K clock counts to the position of least common multiple, assuming that the 32K clock counts a total number of A cycles, the integral multiple clock counts converting the 32K clock count value into B cycles under 24M count, accumulating B24M high-frequency clock count values and leading in the 24M clock units, and then the 24M clock units perform clock counting based on the value obtained by increasing the count B, so as to meet the requirement of the processor on clock precision. After the system is in standby, we do not need to care whether the edges of the 24M and 32K clocks are aligned, because we only care about time compensation and do not care about synchronization with a certain sleep period. When the sleep is entered at any time, the 24M clock unit is immediately turned off, and the 32K clock unit continues to run. After the system is awakened, the clock count value of 32K is converted into the clock count value of 24M at the position where the clock count value of the integer multiple of A is reached firstly after the 32K is awakened, the clock count value is led into the 24M clock unit, and then the 24M clock unit carries out clock counting based on the led value, so that the requirement of a processor on the clock precision is met. Of course this scheme based on the least common multiple of the number of cycles is basically the same as the above-described scheme based on the least common multiple of the cycle duration.
When the sleep command is received, the first time point of the system is t1, and the 24M clock counts to b1 at the first time point t 1. If the 32K clock counts exactly to an integer multiple of a cycles at time t1, then the 24M clock is turned off immediately and the 32K clock remains counting. If the 32K clock is at an integer multiple of non-A cycles at time t1, assuming N1(A-1) + a1, then there is a phase difference of a 1; the 24M clock is still turned off immediately at this time, keeping the 32K clock count. When a wakeup command is received at a time point of t2, if the 32K clock counts n complete A, according to a common multiple relation, when the count of n B needs to be supplemented to the 24M clock at this time, the 24M clock is started, the count of the 24M clock is adjusted to be B1+ NB, and then the 24M continues to count. If the 32k clock counts to the incomplete full N2A's, N2(A-1) + a2, there is a relative difference a2, at which time the 32k clock continues to count until a2 increases to A, so that the count at 32k clock reaches N2 xA. Thus, the phase compensation problem is not considered.
Unlike the prior art, the compensation problem of the relative differences a1 and a2 needs to be considered, so that the first edge and the second edge of the 24M and 32K at the time of starting counting switching before sleeping and after waking are aligned, namely the residue problem proposed by the comparison file is solved. The scheme does not need to align the 32K and the 24M at any edge before and after the sleep, namely the two clocks at the positions of t1 and t2 can have different phases, and the phase difference is allowed to exist. We only calculate the relative delta NA to NB.
It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.
Claims (10)
1. A clock counting synchronization method is characterized by comprising the following steps of running a low-frequency clock unit and simultaneously running a high-frequency clock unit in a first operation stage of a system, stopping running the high-frequency clock unit at a time point t1 when the system is switched from the first operation stage to a power-saving stage, and detecting whether the time tau elapsed from t1 meets the following conditions at a time point t2 when the system is switched from the power-saving stage to a second operation stage:
τ＝n*C
wherein C is: the least common multiple of the period of the low-frequency clock unit and the period of the high-frequency clock unit; n is a natural number;
when tau meets the above condition for the first time, starting to run the high-frequency clock unit, simultaneously compensating an integer period value to the counting result of the high-frequency clock unit according to the value of tau, and synchronizing the system clock according to the compensated counting result of the high-frequency clock unit.
2. A clock count synchronization method, comprising the steps of operating a low frequency clock unit while operating a high frequency clock unit in a first operation stage of a system, stopping the operation of the high frequency clock unit at a time t1 when the system switches from the first operation stage to a power saving stage, calculating a first time t3 after t2 at a time t2 when the system switches from the power saving stage to a second operation stage,
t3-t1＝τ
τ＝n*C
wherein C is: the least common multiple of the period of the low-frequency clock unit and the period of the high-frequency clock unit; n is a natural number;
when the time point t3 is reached, the high frequency clock unit starts to run, meanwhile, according to the value of tau, the counting result of an integer period value to the high frequency clock unit is compensated, and according to the compensated counting result of the high frequency clock unit, the system clock is synchronized.
3. The clock count synchronization method of claim 2, wherein the clock signal of the low frequency clock unit at time t3 is neither at a rising edge nor a falling edge.
4. The clock counting synchronization method according to claim 1 or 2, wherein the clock signal of the low frequency clock unit at time t1 is neither at a rising edge nor a falling edge.
5. The clock counting synchronization method according to claim 1 or 2, wherein the clock signal of the low frequency clock unit at time t2 is neither at a rising edge nor a falling edge.
6. The clock count synchronization method according to claim 1 or 2, wherein the period of the low frequency clock unit is an integer multiple of the period of the high frequency clock unit.
7. The clock count synchronization method according to claim 1 or 2, wherein the period of the low frequency clock unit is not an integer multiple of the period of the high frequency clock unit.
8. The clock count synchronization method according to claim 1 or 2, further comprising the steps of: the common mode unit pre-configures the low frequency clock unit and the high frequency clock unit, wherein configuration parameters include C.
9. A clock counting and synchronizing device is characterized by comprising a low-frequency clock unit, a high-frequency clock unit and a clock switching unit; the low frequency clock unit and the high frequency clock unit operate simultaneously in a first operation stage of the system,
the clock switching unit is used for stopping the operation of the high-frequency clock unit at the time t1 when the system is switched from the first operation stage to the energy-saving stage, and detecting whether the time tau elapsed from t1 meets the following condition at the time t2 when the system is switched from the energy-saving stage to the second operation stage:
τ＝n*C
when tau meets the above condition for the first time, the high frequency clock unit starts to run,
or:
the clock switching unit is used for calculating a first time point t3 after t2, which meets the following condition:
t3-t1＝τ
τ＝n*C
wherein C is: the least common multiple of the period of the low-frequency clock unit and the period of the high-frequency clock unit; n is a natural number;
when the time t3 is reached, the high frequency clock unit starts to run,
the clock switching unit also compensates a counting result from an integer period value to the high-frequency clock unit according to the value of tau, and synchronizes the system clock according to the compensated counting result of the high-frequency clock unit.
10. The clock count synchronization device of claim 9, further comprising a common mode unit for pre-configuring the low frequency clock unit and the high frequency clock unit, wherein configuration parameters include C.
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