CN113258930B

CN113258930B - Digital oscilloscope and correction method of time-interleaved analog-to-digital converter

Info

Publication number: CN113258930B
Application number: CN202110609771.0A
Authority: CN
Inventors: 张传民; 陈报; 容嘉喜
Original assignee: Shenzhen Siglent Technologies Co Ltd
Current assignee: Shenzhen Siglent Technologies Co Ltd
Priority date: 2021-06-02
Filing date: 2021-06-02
Publication date: 2021-09-28
Anticipated expiration: 2041-06-02
Also published as: CN113258930A

Abstract

A digital oscilloscope and a correction method of a time-interleaved analog-to-digital converter comprise a reference channel and at least one channel to be corrected, wherein the reference channel is used for collecting and quantizing signals input into the reference channel and outputting code word values; the central processing unit respectively carries out linear fitting on the code word value output by each channel to be corrected and the code word value output by the reference channel to obtain a correction function of each channel to be corrected; the central processing unit also calculates a first configuration value and a second configuration value of each channel to be corrected according to the correction function of each channel to be corrected; the central processing unit also controls the FPGA processor to store a first configuration value and a second configuration value corresponding to each channel to be corrected, so that the FPGA processor performs gain mismatch correction and offset mismatch correction on each channel to be corrected according to the first configuration value and the second configuration value corresponding to each channel to be corrected. The embodiment of the invention can simultaneously correct the offset mismatch and the gain mismatch, simplify the correction step and save the correction time.

Description

Digital oscilloscope and correction method of time-interleaved analog-to-digital converter

Technical Field

The invention relates to the technical field of oscilloscopes, in particular to a digital oscilloscope and a correction method of a time-interleaved analog-to-digital converter.

Background

The digital oscilloscope is a high-performance oscilloscope manufactured by a series of technologies such as data acquisition, analog-to-digital conversion, software programming and the like. Through the acquisition, processing and operation of the signals, a user can directly observe the measured signals on a time domain. The analog-to-digital converter is called ADC for short, and is a core electronic component in a digital oscilloscope. The key indexes of the analog-digital converter, such as vertical resolution, bandwidth, sampling rate, signal-to-noise ratio, effective bit number (ENOB), and the like, have decisive influence on the measurement signal and also determine the grade and price of the digital oscilloscope. Due to the limitation of the semiconductor process, it is difficult to simultaneously achieve very high sampling rate, vertical resolution, bandwidth and other key indexes on a single analog-to-digital converter chip, and an effective solution is to use a Time-interleaved (Time-interleaved) technology to achieve a higher-performance analog-to-digital converter. The time-interleaved analog-to-digital converter is also applied to high-performance oscilloscope products by numerous oscilloscope manufacturers at home and abroad.

The time-interleaved analog-to-digital converter, also called TIADC for short, is composed of a plurality of subchannels with the same resolution, which alternately sample the input signal and output the result after analog-to-digital conversion, thus achieving the purpose of increasing the sampling rate by times. Ideally, the performance of each sub-channel is identical, but in an actual manufacturing process, the acquisition and quantization results of the same signal by each sub-channel are different. The performance of the time-interleaved analog-to-digital converter is greatly affected by the misadjustment mismatch and the gain mismatch of the sub-channels, and indexes such as spurs and signal-to-noise ratios (SNRs) of the time-interleaved analog-to-digital converter are negatively affected, so that the effective number of the time-interleaved analog-to-digital converter is affected, and the reduction of real signals is further affected.

For correcting various types of mismatch errors of the time-interleaved analog-to-digital converter, two modes, namely digital-analog mixed correction and pure digital domain correction, are generally adopted. The mismatch estimation and correction of pure digital domain correction are carried out in a digital domain, the method corrects data output by an analog-digital converter, but the algorithm of digital processing is complex, large hardware resources are consumed, and the hardware cost is high; the digital-analog mixed correction is generally implemented by detecting and estimating the mismatch amount in a digital domain and feeding back the mismatch amount to an analog domain for compensation, so that the correction is completed. However, in the prior art, the offset mismatch and the gain mismatch in the digital-analog hybrid correction method are usually corrected separately, so that the correction step is complicated, and the time cost of correction is increased.

Disclosure of Invention

In order to solve the above problems, the present invention provides a digital oscilloscope and a method for calibrating a time-interleaved analog-to-digital converter, which can simultaneously calibrate offset mismatch and gain mismatch, simplify calibration steps, and save calibration time.

According to a first aspect, there is provided in an embodiment a digital oscilloscope, comprising:

the signal input end is used for acquiring an externally input signal;

the attenuation network is connected with the signal input end and is used for carrying out attenuation processing on the signal input into the attenuation network;

the impedance transformation network is connected with the attenuation network and is used for conditioning and impedance transforming the signals input into the impedance transformation network;

the adjustable gain amplifier is connected with the impedance transformation network and used for amplifying signals input into the adjustable gain amplifier;

the time-interleaved analog-to-digital converter is connected with the adjustable gain amplifier and comprises a reference channel and at least one channel to be corrected, and the time-interleaved analog-to-digital converter is used for collecting and quantizing a signal input into the time-interleaved analog-to-digital converter and outputting a code word value;

the FPGA processor is connected with the time-interleaving analog-to-digital converter and used for storing a first configuration value and a second configuration value; the time-interleaving analog-to-digital converter is further configured to process a codeword value output by the time-interleaving analog-to-digital converter according to the first configuration value and the second configuration value, and obtain a processed codeword value;

the display screen is connected with the FPGA processor and used for displaying waveforms according to the processed code word values;

the bias adjusting circuit is connected with the impedance transformation network and used for outputting signals to the impedance transformation network and adjusting the position of the waveform on the display screen in the vertical direction;

the central processing unit is connected among the adjustable gain amplifier, the FPGA processor and the bias adjusting circuit and is used for controlling a plurality of direct current signals with different sizes to be input into the time-interleaved analog-to-digital converter so that a reference channel and each channel to be corrected of the time-interleaved analog-to-digital converter respectively acquire and quantize the direct current signals with different sizes and output codeword values; the central processing unit is also used for carrying out linear fitting on the code word value output by each channel to be corrected and the code word value output by the reference channel respectively to obtain a correction function of each channel to be corrected; the central processing unit also calculates a first configuration value and a second configuration value of each channel to be corrected according to the correction function of each channel to be corrected; the central processing unit further controls the FPGA processor to store the first configuration value and the second configuration value of each channel to be corrected, so that the FPGA processor performs gain mismatch correction and offset mismatch correction on each channel to be corrected according to the first configuration value and the second configuration value of each channel to be corrected.

In one possible implementation manner, the calculating, by the central processing unit, the first configuration value and the second configuration value of each channel to be corrected according to the correction function of each channel to be corrected includes:

the central processing unit calculates an inverse function of the correction function corresponding to each channel to be corrected, and calculates a first configuration value and a second configuration value of each channel to be corrected according to the inverse function of the correction function of each channel to be corrected.

In one possible implementation, the digital oscilloscope further includes:

the sampling clock generating circuit is used for outputting an initial sampling clock signal;

the phase adjusting circuit is connected between the sampling clock generating circuit and the time-interleaving analog-to-digital converter and is used for storing a plurality of preset sampling delay values of each channel to be corrected relative to the sampling time of the reference channel; the sampling module is also used for respectively outputting a plurality of sampling clock signals to each channel to be corrected according to the initial sampling clock signal and the preset sampling delay value;

the central processing unit is also used for controlling the sine wave signal to be input into the time interleaving analog-to-digital converter; the central processing unit further controls the sampling clock generation circuit to output an initial sampling clock signal, and controls the phase adjustment circuit to output a plurality of sampling clock signals to each channel to be corrected according to the initial sampling clock signal and the plurality of preset sampling delay values, so that each channel to be corrected acquires and quantizes the sine wave signal according to the plurality of sampling clock signals and outputs a code word value, and transmits the code word value to the central processing unit or the FPGA processor for spectrum conversion, and the central processing unit or the FPGA processor outputs a spectrum conversion result; the central processing unit also calculates the optimal sampling delay value of each channel to be corrected according to the preset sampling delay value and the spectrum transformation result corresponding to each sampling clock signal of each channel to be corrected; and the central processing unit also configures the optimal sampling delay value of each channel to be corrected into the phase adjusting circuit, so that the phase adjusting circuit performs sampling time mismatch correction on each channel to be corrected according to the optimal sampling delay value of each channel to be corrected.

In one possible implementation manner, the calculating, by the central processing unit, an optimal sampling delay value of each channel to be corrected according to a preset sampling delay value and a spectrum transformation result corresponding to each sampling clock signal of each channel to be corrected includes:

the central processing unit calculates the effective digit of the time-interleaving analog-digital converter corresponding to each preset sampling delay value of each channel to be corrected according to the frequency spectrum conversion result of each channel to be corrected;

the central processing unit carries out polynomial fitting on each preset sampling delay value of each channel to be corrected and the effective digit of the time-interleaved analog-to-digital converter corresponding to the preset sampling delay value to obtain a correction polynomial of each channel to be corrected;

and the central processing unit calculates the optimal sampling delay value of each channel to be corrected according to the correction polynomial of each channel to be corrected.

In one possible implementation manner, the calculating, by the central processing unit, an optimal sampling delay value of each channel to be corrected according to the correction polynomial of each channel to be corrected includes:

the central processing unit conducts derivation on the correction polynomial of each channel to be corrected to obtain a derivation formula corresponding to the correction polynomial of each channel to be corrected;

and the central processing unit calculates the optimal sampling delay value of each channel to be corrected according to the derivation formula corresponding to the correction polynomial of each channel to be corrected.

In one possible implementation manner, the calculating, by the central processing unit, an optimal sampling delay value of each channel to be corrected according to a derivation expression corresponding to the correction polynomial of each channel to be corrected includes:

the central processing unit calculates real number when the derivation formula corresponding to the correction polynomial of each channel to be corrected is 0;

the central processing unit substitutes the real root when the derivation formula corresponding to the correction polynomial of each channel to be corrected is 0 into the correction polynomial of each channel to be corrected respectively to calculate, and effective digit values of a plurality of time-interleaved analog-to-digital converters corresponding to the real root are obtained;

the central processing unit compares the effective digit values of a plurality of time-interleaved analog-to-digital converters of each channel to be corrected, and selects the maximum effective digit value of the time-interleaved analog-to-digital converters;

and the central processing unit acquires a real root corresponding to the maximum effective digit value of the time-interleaving analog-to-digital converter of each channel to be corrected as the optimal sampling delay value of the channel to be corrected.

According to a second aspect, there is provided in an embodiment a method of correction for a time-interleaved analog-to-digital converter, comprising:

a first signal input step of controlling a plurality of direct current signals with different sizes to be input into a time-interleaved analog-to-digital converter so that a plurality of subchannels of the time-interleaved analog-to-digital converter respectively acquire and quantize the plurality of direct current signals with different sizes and output codeword values; the plurality of sub-channels comprise a reference channel and at least one channel to be corrected;

a linear fitting step, in which the code word value output by each channel to be corrected is linearly fitted with the code word value output by the reference channel respectively to obtain a correction function of each channel to be corrected;

a configuration value calculation step, namely calculating a first configuration value and a second configuration value of each channel to be corrected according to the correction function of each channel to be corrected;

and a first configuration step of controlling and storing a first configuration value and a second configuration value corresponding to each channel to be corrected so that the FPGA processor performs gain mismatch correction and offset mismatch correction on each channel to be corrected according to the first configuration value and the second configuration value corresponding to each channel to be corrected.

In one possible implementation manner, the configuration value calculating step includes:

and an inverse function calculation step of calculating an inverse function of the correction function corresponding to each channel to be corrected, and calculating a first configuration value and a second configuration value of each channel to be corrected according to the inverse function of the correction function of each channel to be corrected.

In one possible implementation manner, the correction method further includes:

a second signal input step of controlling input of a sine wave signal to the time-interleaved analog-to-digital converter;

an initial sampling clock signal output step, controlling to output an initial sampling clock signal;

a frequency spectrum conversion step, namely controlling to output sampling clock signals to each channel to be corrected according to the initial sampling clock signals and a plurality of preset sampling delay values, so that each channel to be corrected acquires and quantizes the sine wave signals according to the plurality of sampling clock signals and outputs code word values, and transmits the sine wave signals to a central processing unit or an FPGA processor for frequency spectrum conversion, and the central processing unit or the FPGA processor outputs a frequency spectrum conversion result;

a first effective digit calculating step, namely calculating the effective digits of the time-interleaving analog-digital converter corresponding to each preset sampling delay value of each channel to be corrected according to the frequency spectrum conversion result of each channel to be corrected;

a polynomial fitting step, in which polynomial fitting is respectively carried out on each preset sampling delay value of each channel to be corrected and the corresponding effective digit of the time-interleaved analog-to-digital converter, so as to obtain a correction polynomial of each channel to be corrected;

a derivation step, namely respectively deriving the correction polynomial of each channel to be corrected to obtain a derivation formula corresponding to the correction polynomial of each channel to be corrected;

a real number calculation step, which is used for respectively calculating the real number when the derivation formula corresponding to the correction polynomial of each channel to be corrected is 0;

a second significant digit calculation step, namely substituting the real root of each channel to be corrected, which corresponds to the correction polynomial of each channel to be corrected, when the derivation formula is 0, into the correction polynomial of each channel to be corrected respectively for calculation, and obtaining the significant digit values of a plurality of time-interleaved analog-to-digital converters corresponding to the real roots;

the effective digit comparison step is used for respectively comparing the effective digit values of a plurality of time-interleaved analog-to-digital converters of each channel to be corrected and selecting the maximum effective digit value of the time-interleaved analog-to-digital converter;

acquiring an optimal sampling delay value, namely acquiring a real root corresponding to the most significant digit value of the time-interleaved analog-to-digital converter of each channel to be corrected, and taking the real root as the optimal sampling delay value of the channel to be corrected;

and a second configuration step, in which the optimal sampling delay value of each channel to be corrected is configured into the phase adjustment circuit, so that the phase adjustment circuit performs sampling time mismatch correction on each channel to be corrected according to the optimal sampling delay value of each channel to be corrected.

According to a third aspect, there is provided in one embodiment a digital oscilloscope, comprising:

a memory for storing a program;

and a processor for implementing the above-described correction method by executing the program stored in the memory.

The embodiment of the invention has the following beneficial effects:

according to the digital oscilloscope and the correction method of the time-interleaved analog-to-digital converter, as the code word value output by each channel to be corrected is respectively subjected to linear fitting with the code word value output by the reference channel to obtain the correction function of each channel to be corrected, the first configuration value and the second configuration value of each channel to be corrected are simultaneously calculated according to the correction function, and the first configuration value and the second configuration value are simultaneously configured in the FPGA processor to finish correction, the invention can simultaneously correct the imbalance mismatch and the gain mismatch, simplify the correction step, reduce the difficulty of the correction algorithm and save the correction time; in addition, the method for searching the optimal sampling delay value of each channel to be corrected through the derivation formula of the correction polynomial only needs to substitute the real number root when the derivation formula is 0 into the correction polynomial to calculate the effective digit of the time-interleaving analog-to-digital converter, so that the effective digit of the time-interleaving mode converter corresponding to the delay value at each sampling moment is prevented from being subjected to traversal calculation, the correction time is shortened, and the correction precision is improved.

Drawings

Fig. 1 is a schematic diagram of a time-interleaved analog-to-digital converter of the present application for acquiring and quantizing a signal input thereto;

FIG. 2 is a first schematic structural diagram of a digital oscilloscope according to an embodiment of the present application;

FIG. 3 is a schematic diagram of an FPGA processor of the present application performing mismatch and gain mismatch correction according to a first configuration value and a second configuration value in one embodiment;

FIG. 4 is a schematic diagram of an output waveform of the clock generation circuit of the present application in one embodiment;

FIG. 5 is a second schematic structural diagram of a digital oscilloscope according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a phase adjustment circuit of the present application outputting a sampling clock signal in one embodiment;

FIG. 7 is a diagram illustrating a preset sampling delay value configured in one embodiment of a phase adjustment circuit according to the present application;

FIG. 8 is a diagram of a digital oscilloscope according to an embodiment of the present application for calculating derivatives and their roots corresponding to a correction polynomial;

FIG. 9 is a first flowchart illustrating a calibration method according to an embodiment of the present disclosure;

FIG. 10 is a second flowchart illustrating a calibration method of the present application in one embodiment;

FIG. 11 is a third flowchart illustrating a calibration method according to an embodiment of the present disclosure;

fig. 12 is a schematic structural diagram three of a digital oscilloscope according to an embodiment of the present application.

Detailed Description

The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.

Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.

The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "coupled", as used herein, includes both direct and indirect coupling, unless otherwise specified; the term "obtaining" as used herein includes both direct and indirect obtaining, unless otherwise specified.

Referring to FIG. 1, a time-interleaved analog-to-digital converter (TIADC) is composed of M sub-channels, each of which has a sampling rate fs/M and is provided by a clock generation circuit. The M sub-channels sample the input signal sequentially, so the total sampling rate of the time-interleaved analog-to-digital converter for the analog signal output by the VGA is fs. And after the time-interleaved analog-to-digital converter finishes analog-to-digital conversion, outputting a result after the acquisition and quantization.

In an ideal situation, the conversion accuracy of the time-interleaved analog-to-digital converter should be consistent with that of each sub-channel on the channel, but due to process limitations, on-chip errors, operating temperature conversion and other factors, output data of each sub-channel is mismatched, such as mismatch and gain mismatch. The inventors have analyzed the effects of mismatch and gain mismatch on the signals, respectively, as described in detail below.

(1) Analysis of the effect of mismatch on signal:

when the input frequency is

Normalized positive signal of (1), mismatching error V existing in single subchannel_OSAt this time, for a single-channel analog-to-digital converter, the acquisition quantization output is:

where T is the period over which the signal is sampled.

It is assumed that the mismatch error of each subchannel of the time-interleaved analog-to-digital converter is

For M subchannels, the sequence of mismatch mismatches after time-interleaved analog-to-digital converter sampling is

With a period of MTs, i.e.

Fourier transform on misadjusted mismatch sequences:

，

where M is the number of sub-channels of the time-interleaved analog-to-digital converter, and Ts is that of two adjacent sub-channelsDelay value of sampling clock, V_OSIn order to offset the mismatch error,

is the frequency of the input signal and,

for the sampling angular frequency at which the signal is sampled, j is an imaginary unit (j × j = -1), k is a frequency point at which spurs occur (k = ± 1, ± 2, ± 3 …), i represents the i-th sub-ADC of the time-interleaved analog-to-digital converter (i =1,2,3 … M),

representing an impulse signal.

It can be seen that the spurious frequency point of the mismatch error appears at the position of the whole frequency spectrum

，

The spectral position caused by the mismatch of offsets is only related to the number of sub-channels and the sampling frequency of the system, and not to the frequency and amplitude of the input signal. Amplitude of the spur and offset voltage V of each channel_OSAnd (4) correlating.

(2) Analysis of the effect of gain mismatch on the signal:

let G be the gain of each subchannel of the time-interleaved analog-to-digital converter_iLet us order

，

So that the mismatch gain

Assuming a Fourier transform of the input signal x (t)

And carrying out Fourier transform on the gain mismatch error of the output sequence of the time-interleaved analog-to-digital converter to obtain:

，

wherein A is the amplitude of the input signal, M is the number of sub-channels of the time-interleaved analog-to-digital converter, Ts is the delay value of the sampling clock of two adjacent sub-channels,

in order to have a mismatched gain, the gain,

is the frequency of the input signal and,

for the sampling angular frequency at which the signal is sampled, j is an imaginary unit (j × j = -1), k is a frequency point at which spurs occur (k = ± 1, ± 2, ± 3 …), and i represents the i-th sub-ADC of the time-interleaved analog-to-digital converter (i =1,2,3 … M).

It follows that the effect of gain mismatch error on the frequency spectrum, and the amplitude of the input signal, the number of sub-channels of the time-interleaved analog-to-digital converter, the mismatch gain

And (4) correlating. The miscellaneous diseases appear in

To (3).

For the correction of various mismatch errors of the time-interleaved analog-to-digital converter, a digital-to-analog mixed correction method is usually used, but the offset mismatch and the gain mismatch in the digital-to-analog mixed correction method are corrected separately, so that the correction step is relatively complicated, and the time cost of correction is increased. In contrast, according to the application, one of the sub-channels of the time-interleaved analog-to-digital converter is used as a reference channel, the other sub-channels are used as channels to be corrected, code word values output by the channels to be corrected are respectively subjected to linear fitting with code word values output by the reference channel, and the offset coefficient and the gain coefficient of each channel to be corrected are obtained according to linear fitting results, so that the offset coefficient and the gain coefficient can be configured at the same time to finish correction, the correction steps are greatly simplified, and the correction time is saved.

Referring to fig. 2, the digital oscilloscope in one embodiment includes a signal input terminal 101, an attenuation network 102, an impedance transformation network 103, an adjustable gain amplifier 104, a time-interleaved analog-to-digital converter 105, an FPGA processor 106, a display screen 107, a bias adjustment circuit 108, and a central processing unit 109.

The signal input terminal 101 is used for acquiring an externally input signal.

The attenuation network 102 is connected to the signal input terminal 101, and is used for performing attenuation processing on a signal input into the attenuation network 102.

The impedance transforming network 103 is connected to the attenuating network 102 for conditioning and impedance transforming the signal input to the impedance transforming network 103.

The adjustable gain amplifier 104 is connected to the impedance transforming network 103 for amplifying the signal inputted to the adjustable gain amplifier 104.

The time-interleaved analog-to-digital converter 105 is connected to the adjustable gain amplifier 104; the time-interleaved analog-to-digital converter 105 includes a reference channel and N channels to be corrected, and is configured to acquire and quantize a signal input to the time-interleaved analog-to-digital converter 105 and output a codeword value. Wherein

And M is a positive integer greater than or equal to 2. In some embodiments, the first sub-channel ADC may be implemented₁As a reference channel, the remaining sub-channels

As a channel to be corrected.

The FPGA processor 106 is connected to the time-interleaved analog-to-digital converter 105, and is configured to store the gain coefficient and the offset coefficient; and is further configured to process the codeword value output by the time interleaving adc 105 according to the gain coefficient and the mismatch coefficient, so as to obtain a processed codeword value.

The display screen 107 is connected to the FPGA processor 106, and is used for displaying waveforms according to the processed codeword values.

The bias adjusting circuit 108 is connected to the impedance transforming network 103 for outputting signals to the impedance transforming network 103 to adjust the position of the waveform on the display screen 107 in the vertical direction.

A central processing unit 109 is connected between the adjustable gain amplifier 104, the FPGA processor 106 and the bias adjusting circuit 108, and is used for controlling the input of a plurality of dc signals with different magnitudes to the time-interleaved analog-to-digital converter 105

So that the reference channel and each channel to be corrected of the time-interleaved analog-to-digital converter 105 are respectively corresponding to a plurality of DC signals with different sizes

And collecting and quantizing the code word and outputting the code word value. Wherein m is a positive integer. In some embodiments, the reference channel ADC₁The output codeword value is

First channel to be corrected ADC₂The output codeword value is

Second channel ADC to be corrected₃The output codeword value is

… … Nth channel ADC to be corrected_MThe output codeword value is

. In some embodiments, m may take on a value of 7. In some embodiments, the cpu 109 may control the signal input terminal 101 to obtain a plurality of initial dc signals with different magnitudes from the outside

Transmitting to the attenuator network 102 for attenuation processing and impedance transformation103, and transmitting the processed signals to an adjustable gain amplifier 104, or controlling a bias adjusting circuit 108 to output a plurality of initial DC signals with different magnitudes

Conditioning and impedance transformation processing are carried out on the signal to an impedance transformation network 103, and the signal is transmitted to an adjustable gain amplifier 104; the CPU 109 then controls the adjustable gain amplifier 104 to adjust the initial DC signal

Amplifying to obtain multiple DC signals with different magnitudes

And output to the time-interleaved analog-to-digital converter 105.

It should be noted that, in general, the correction requires inputting a dc signal to the time-interleaved analog-to-digital converter 105 in a proper step. For a time-interleaved analog-to-digital converter 105 of X bit conversion precision, the range of the code words is

It is usually required that the input dc signal falls within a certain codeword range. For example, the input dc signal is selected to fall within the range of 10% to 90% of the full scale of the time-interleaved

adc

105, and 10% of the full scale of the time-interleaved adc 105 is taken as the step, and for the time-interleaved adc 105 with 8-bit conversion accuracy, the full scale codeword range is 0 to 255, so that after the input dc signal is analog-to-digital converted, the codeword range output by the time-interleaved adc 105 is within about 26 to 220, and the step of the dc signal is about 26. However, the invention has no requirement on the absolute precision of the direct current signal and the stepping of the direct current signal because of the correction of the offset mismatch and the gain mismatch on the oscilloscope.

The central processing unit 109 further performs linear fitting on the code word value output by each channel to be corrected and the code word value output by the reference channel, so as to obtain a correction function of each channel to be corrected. Some implementationsIn an example, reference channel ADC may be used₁Output codeword value

As abscissa, respectively using ADC of the channel to be corrected₂~ADC_MThe output code word value is a vertical coordinate, linear fitting is carried out by using a least square method, and then a channel to be corrected is subjected to

The correction function can be found as follows:

，

wherein k is_zIs an ADC_zRelative to ADC₁Gain factor, intercept b of_zIs an ADC_zRelative to ADC₁The coefficient of misadjustment of (a) is,

。

for example, with reference channel ADC₁Output codeword value

As abscissa, with the first channel ADC to be corrected₂Output codeword value

For the ordinate, linear fitting is carried out by using a least square method to obtain a first channel ADC to be corrected₂Correction function of

Then k is₂Is an ADC₂Relative to ADC₁Gain factor, intercept b of₂Is an ADC₂Relative to ADC₁The coefficient of misadjustment of (d).

The central processing unit 109 also calculates a first configuration value sum of each channel to be corrected according to the correction function of each channel to be correctedA second configuration value. In some embodiments, the central processor 109 may calculate an inverse function of the correction function corresponding to each channel to be corrected, and calculate the first configuration value and the second configuration value of each channel to be corrected according to the inverse function of the correction function of the channel to be corrected. In some embodiments, for the channel to be corrected

The inverse function of the correction function can be found as follows:

，

wherein k is_zIs an ADC_zRelative to ADC₁Gain coefficient of (b)_zIs an ADC_zRelative to ADC₁The coefficient of misadjustment of (a) is,

；1/k_zis an ADC_zA first configuration value, -b_zIs an ADC_zOf the second configuration value.

Referring to fig. 3, the central processing unit 109 further controls the FPGA processor 106 to store the first configuration value and the second configuration value corresponding to each channel to be corrected, so that the FPGA processor 106 performs gain mismatch correction and offset mismatch correction on each channel to be corrected according to the first configuration value and the second configuration value corresponding to each channel to be corrected. In some embodiments, the central processor 109 may control the FPGA processor 106 to assign 1/k_zADC as channel to be corrected_zAnd will-b_zADC as channel to be corrected_zThe second configuration value of (a) is stored, the FPGA processor 106 can then treat the correction channel ADC_zInput codeword value is based on

To carry out

Operated and output so that eachThe final codeword output of the channel to be corrected after the same signal is acquired is the same, thereby realizing the correction of the offset mismatch and the gain mismatch of the time-interleaved analog-to-digital converter 105, wherein

。

Referring to FIG. 4, since the sampling rate of the time-interleaved ADC 105 is fs, the sampling rate of each sub-channel is fs

Is divided by fs. Ideally, the delay value of the sampling clocks of two adjacent sub-channels is Ts, and the sampling period of the time-interleaved analog-to-digital converter 105 is

Each sub-channel having a sampling period of

. Due to chip technology, wiring and other reasons, the sampling time when the sampling clock signal reaches each sub-channel has a mismatch phenomenon, and the delay error between the sampling clock of the adjacent sub-ADCs and the ideal time is

. The skew of the sampling clocks of the individual sub-channels also affects the performance of the time-interleaved analog-to-digital converter 105, and the inventors have analyzed this effect as follows:

with the first sub-channel as a reference, the mismatch time of each sub-channel with respect to the ideal sampling time is

Assuming an input signal

Fourier transform of

Then the Fourier transform of the time-interleaved analog-to-digital converter 105 output sequence

Comprises the following steps:

，

where M is the number of sub-channels of the time-interleaved analog-to-digital converter 105, Ts is the delay value of the sampling clock of two adjacent sub-channels,

is the frequency of the input signal and,

It can be seen that the sampling instant mismatch spurs appear at

The amount of energy is related to the amplitude, frequency and sampling rate of the input signal.

After the offset mismatch and the gain mismatch are corrected, the amplitude and the offset of the signal output by each sub-channel are the same for the input of the same signal, so that the offset mismatch and the gain mismatch are corrected first, the influence caused by the offset mismatch and the gain mismatch can be eliminated first, and the correction at the sampling moment is more concentrated. The idea of the mismatch correction of the sampling time is to adjust the delay value of the sampling clock of each channel to be corrected to approach the ideal sampling time, record the calculated optimal delay value, and compensate the optimal delay value into the phase adjustment circuit of the clock generation circuit, which will be described in detail below.

Referring to fig. 5 and 6, the digital oscilloscope in one embodiment further includes a sampling clock generating circuit 110 and a phase adjusting circuit 111.

The sampling clock generation circuit 110 is configured to output an initial sampling clock signal.

The phase adjustment circuit 111 is connected between the sampling clock generation circuit 110 and the time-interleaved analog-to-digital converter 105, and is configured to store a plurality of preset sampling delay values of each channel to be corrected with respect to a sampling time of the reference channel, and output a plurality of sampling clock signals to each channel to be corrected according to the initial sampling clock signal and the plurality of preset sampling delay values.

The CPU 109 is also used for ADC according to the reference channel₁The sampling time of the correction control module is controlled to sequentially correct each channel to be corrected

And carrying out sampling moment mismatch correction. In some embodiments, the ADC for the channel to be corrected may be controlled first₂And carrying out sampling moment mismatch correction. The central processor 109 controls the input of the sine wave signal to the time-interleaved analog-to-digital converter 105. In some embodiments, the central processing unit 109 may control the signal input end 101 to obtain an initial sine wave signal from the outside, transmit the initial sine wave signal to the attenuation network 102 for attenuation processing, the impedance transformation network 103 for conditioning and impedance transformation processing, and transmit the initial sine wave signal to the adjustable gain amplifier 104, or control the bias adjusting circuit 108 to output the initial sine wave signal to the impedance transformation network 103 for conditioning and impedance transformation processing, and transmit the initial sine wave signal to the adjustable gain amplifier 104; then, the cpu 109 controls the adjustable gain amplifier 104 to amplify the initial sine wave signal, so as to obtain a sine wave signal and output the sine wave signal to the time-interleaved adc 105. The digital-to-analog converter built in the digital oscilloscope bias adjusting circuit 108 can output various signals according to the correction requirement, and has higher flexibility.

The cpu 109 further controls the sampling clock generating circuit 110 to output an initial sampling clock signal, and controls the phase adjusting circuit 111 to perform channel ADC calibration according to the initial sampling clock signal and a plurality of preset sampling delay values₂Outputting a plurality of sampling clock signals to enable the ADC to be corrected₂According to multiple miningThe sine wave signal is acquired and quantized by the sample clock signal, a code word value is output and transmitted to the central processing unit 109 or the FPGA processor 106 for frequency spectrum transformation, and the central processing unit 109 or the FPGA processor 106 outputs a frequency spectrum transformation result. Referring to FIG. 7, in some embodiments, the ADC is applied to the channel to be corrected₂A plurality of preset sampling delay values may be pre-configured in the phase adjustment circuit 111

Where T is the stepping time of the phase adjustment circuit 111, r is the number of steps, T₁For the channel ADC to be corrected₂Q may take the value of 9.

The central processing unit 109 also calculates the channel ADC to be corrected according to the preset sampling delay value and the spectrum conversion result corresponding to each sampling clock signal₂The optimal sample delay value. In some embodiments, the central processing unit 109 may calculate the ADC of the channel to be corrected according to the spectrum transformation result of each channel to be corrected₂Each preset sample delay value of

Significance of corresponding time-interleaved analog-to-digital converter

And ADC the channel to be corrected₂Performing polynomial fitting on each preset sampling delay value and the corresponding effective digit of the time-interleaved analog-to-digital converter to obtain the channel ADC to be corrected₂The correction polynomial of (1). In some embodiments, the channel ADC to be corrected may be used₂Sample delay value of

As abscissa and interleaving the significands of the analog-to-digital converter with corresponding times

For the ordinate, polynomial fitting is carried out to obtain the ADC of the channel to be corrected₂The correction polynomial of (a) is as follows:

，

wherein,

b is the intercept of the polynomial, a is more than or equal to 1 and less than or equal to B, B is a positive integer and B is more than or equal to 2.

The CPU 109 based on the ADC channel to be calibrated₂Calculating the ADC of the channel to be corrected₂The optimal sample delay value. Referring to fig. 8, in some embodiments, the cpu 109 may treat the channel ADC to be corrected₂The correction polynomial is subjected to derivation to obtain the ADC of the channel to be corrected₂The derivation formula corresponding to the correction polynomial

And according to the channel ADC to be corrected₂Calculating the ADC of the channel to be corrected by the derivation formula corresponding to the correction polynomial₂The optimal sample delay value. In some embodiments, the cpu 109 may calculate the channel ADC to be corrected₂The derivation formula corresponding to the correction polynomial of (2) is 0

Real number root of time, and ADC the channel to be corrected₂The real root when the derivation formula corresponding to the correction polynomial is 0 is respectively substituted into the ADC of the channel to be corrected₂The correction polynomial of (2) is calculated to obtain the significant digit values of a plurality of time-interleaved analog-to-digital converters corresponding to each real root; the central processing unit 109 ADC the channel to be corrected₂Comparing the effective digit values of the plurality of time-interleaved analog-to-digital converters, selecting the maximum effective digit value of the time-interleaved analog-to-digital converter, and acquiring the ADC of the channel to be corrected₂The real root corresponding to the most significant digit value of the time-interleaved analog-to-digital converter is used as the ADC of the channel to be corrected₂The optimal sample delay value.

The central processing unit 109 ADC the channel to be corrected₂Is configured into the phase adjusting circuit 111, so that the phase adjusting circuit 111 can perform ADC according to the channel to be corrected₂To-be-corrected channel ADC₂And carrying out sampling moment mismatch correction. Then, the central processing unit 109 sequentially performs sampling time mismatch correction on the remaining channels to be corrected according to the sampling time mismatch correction method.

The main workflow of the digital oscilloscope of the present application is explained below.

In one embodiment, the gain mismatch and offset mismatch can be corrected first: the central processor 109 controls to input a plurality of dc signals with different sizes to the time-interleaved analog-to-digital converter 105, so that the reference channel and each channel to be corrected of the time-interleaved analog-to-digital converter 105 respectively acquire and quantize the plurality of dc signals with different sizes and output codeword values; the central processing unit 109 performs linear fitting on the code word value output by each channel to be corrected and the code word value output by the reference channel respectively to obtain a correction function of each channel to be corrected, calculates an inverse function of the correction function corresponding to each channel to be corrected, and calculates a first configuration value and a second configuration value of each channel to be corrected according to the inverse function of the correction function of each channel to be corrected; the central processing unit 109 controls the FPGA processor 106 to store the first configuration value and the second configuration value corresponding to each channel to be corrected, so that the FPGA processor 106 performs gain mismatch correction and offset mismatch correction on each channel to be corrected according to the first configuration value and the second configuration value corresponding to each channel to be corrected. Then a sample time mismatch correction can be performed: the central processing unit 109 controls the sine wave signal input to the time-interleaved analog-to-digital converter 105, controls the sampling clock generation circuit to output an initial sampling clock signal, controls the phase adjustment circuit to output a plurality of sampling clock signals to each channel to be corrected according to the initial sampling clock signal and a plurality of preset sampling delay values, so that each channel to be corrected acquires and quantizes the sine wave signal according to the plurality of sampling clock signals and outputs a code word value, and transmits the code word value to the central processing unit 109 or the FPGA processor 106 for frequency spectrum conversion, and outputs a frequency spectrum conversion result; the central processing unit 109 calculates the optimal sampling delay value of each channel to be corrected according to the preset sampling delay value and the spectrum transformation result corresponding to each sampling clock signal of each channel to be corrected, and configures the optimal sampling delay value of each channel to be corrected into the phase adjustment circuit, so that the phase adjustment circuit performs sampling time mismatch correction on each channel to be corrected according to the optimal sampling delay value of each channel to be corrected. It can be seen that, since the code word values output by each channel to be corrected are respectively linearly fitted with the code word values output by the reference channel to obtain the correction function of each channel to be corrected, and the first configuration value and the second configuration value of each channel to be corrected are simultaneously calculated according to the correction function and are simultaneously configured in the FPGA processor 106 to complete the correction, the invention can simultaneously correct the offset mismatch and the gain mismatch, simplify the correction steps, reduce the difficulty of the correction algorithm, and save the correction time; in addition, the method for searching the optimal sampling delay value of each channel to be corrected through the derivation formula of the correction polynomial only needs to substitute the real number root when the derivation formula is 0 into the correction polynomial to calculate the effective digit of the time-interleaved analog-to-digital converter, so that the delay value of each sampling moment in a phase adjusting circuit is prevented from being respectively output to the corresponding clock signal to the time-interleaved analog-to-digital converter, the optimal delay value corresponding to the maximum effective digit of the time-interleaved analog-to-digital converter is obtained, the correction time is reduced, and the correction precision is improved.

Referring to fig. 9, in an embodiment, a calibration method of a time-interleaved analog-to-digital converter includes the following steps:

a first signal input step 210, controlling to input a plurality of direct current signals with different sizes to the time-interleaved analog-to-digital converter, so that a plurality of subchannels of the time-interleaved analog-to-digital converter respectively acquire and quantize the plurality of direct current signals with different sizes and output codeword values; the plurality of sub-channels comprise a reference channel and N channels to be corrected; wherein

And M is a positive integer greater than or equal to 2. In some embodiments, the signal input terminal may be controlled to obtain a plurality of initial dc signals with different magnitudes from the outside

And transmitting to an adjustable gain amplifier or controlling a bias adjusting circuit to output a plurality of initial direct current signals with different magnitudes

To the adjustable gain amplifier and controlling the adjustable gain amplifier to the initial DC signal

Amplifying to obtain multiple DC signals with different magnitudes

And outputting the signals to a time-interleaved analog-to-digital converter so that a plurality of subchannels of the time-interleaved analog-to-digital converter respectively correspond to a plurality of direct-current signals with different sizes

Collecting and quantizing the code word values and outputting the code word values; wherein m is a positive integer. In some embodiments, the first sub-channel ADC may be implemented₁As a reference channel, the remaining sub-channels

As a channel to be corrected. In some embodiments, the reference channel ADC₁The output codeword value is

First channel to be corrected ADC₂The output codeword value is

Second channel ADC to be corrected₃Output code wordHas a value of

… … Nth channel ADC to be corrected_MThe output codeword value is

. In some embodiments, m may take on a value of 7.

It should be noted that, in general, the correction requires inputting a dc signal to the time-interleaved analog-to-digital converter in a proper step. For a time-interleaved analog-to-digital converter with an X bit conversion precision, the code word range is

It is usually required that the input dc signal falls within a certain codeword range. For example, the input direct current signal is selected to fall within the range of 10% -90% of the full scale of the time-interleaved analog-to-digital converter, 10% of the full scale of the time-interleaved analog-to-digital converter is taken as the step, for the time-interleaved analog-to-digital converter with 8-bit conversion precision, the full scale codeword range is 0-255, after the input direct current signal is subjected to analog-to-digital conversion, the codeword range output by the time-interleaved analog-to-digital converter is within 26-220, and the step of the direct current signal is about 26. Due to the correction of the detuning mismatch and the gain mismatch on the oscilloscope, the time-interleaved analog-to-digital converter has no requirement on the absolute precision of the direct current signal and the stepping of the direct current signal.

And a linear fitting step 220, performing linear fitting on the code word value output by each channel to be corrected and the code word value output by the reference channel respectively to obtain a correction function of each channel to be corrected. In some embodiments, reference channel ADC may be used₁Output codeword value

The correction function can be found as follows:

，

。

for example, with reference channel ADC₁Output codeword value

As abscissa, with the first channel ADC to be corrected₂Output codeword value

A configuration value calculating step 230, calculating a first configuration value and a second configuration value of each channel to be corrected according to the correction function of each channel to be corrected. Referring to fig. 10, in some embodiments, the configuration value calculating step 230 may include an inverse function calculating step 231:

an inverse function calculation step 231 calculates an inverse function of the correction function corresponding to each channel to be corrected, and calculates a first configuration value and a second configuration value of each channel to be corrected according to the inverse function of the correction function of the channel to be corrected. In some embodiments, for the channel to be corrected

The inverse function of the correction function can be found as follows:

，

A first configuration step 240, controlling the FPGA processor to store the first configuration value and the second configuration value corresponding to each channel to be corrected, so that the FPGA processor performs gain mismatch correction and offset mismatch correction on each channel to be corrected according to the first configuration value and the second configuration value corresponding to each channel to be corrected. In some embodiments, the FPGA processor may be controlled to 1/k_zADC as channel to be corrected_zAnd will-b_zADC as channel to be corrected_zThe second configuration value is stored, so that the FPGA processor can treat the ADC of the correction channel_zInput codeword value is based on

To carry out

Calculating and outputting to make final code word output of each channel to be corrected after same signal is collected be same, thereby realizing correction of offset mismatch and gain mismatch of time-interleaved analog-to-digital converter, wherein

。

Referring to fig. 11, in some embodiments, the method for calibrating a time-interleaved analog-to-digital converter may further include: ADC according to reference channel₁The sampling time of the correction control module is controlled to sequentially correct each channel to be corrected

And carrying out sampling moment mismatch correction. In some embodiments, the ADC for the channel to be corrected may be controlled first₂The sampling timing mismatch correction is performed, and the specific steps are explained below.

A second signal input step 250 controls the input of the sine wave signal to the time-interleaved analog-to-digital converter. In some embodiments, the signal input end may be controlled to obtain an initial sine wave signal from the outside and transmit the initial sine wave signal to the adjustable gain amplifier, or the bias adjustment circuit may be controlled to output the initial sine wave signal to the adjustable gain amplifier, and the adjustable gain amplifier may be controlled to amplify the initial sine wave signal, so as to obtain a sine wave signal and output the sine wave signal to the time-interleaved analog-to-digital converter. The digital-to-analog converter built in the offset adjusting circuit of the digital oscilloscope is utilized, various signals can be output according to the correction requirement, and the digital-to-analog converter has higher flexibility.

An initial sampling clock signal output step 260, controlling to output an initial sampling clock signal.

A spectrum conversion step 270 of controlling the ADC of the channel to be corrected according to the initial sampling clock signal and the plurality of preset sampling delay values₂Outputting sampling clock signal to make channel ADC to be corrected₂And acquiring and quantifying the sine wave signals according to a plurality of sampling clock signals, outputting code word values, and transmitting the code word values to a central processing unit or the FPGA processor for spectrum conversion, wherein the central processing unit or the FPGA processor outputs a spectrum conversion result. In some embodiments, ADC is used for channel to be corrected₂Multiple preset sampling delay values can be pre-configured in the phase adjustment circuit

Where T is the stepping time of the phase adjustment circuit, r is the number of steps, T₁For channels to be corrected ADC₂Q may take the value of 9.

A first effective digit calculation step 280 of ADC according to the channel to be corrected₂Calculating the ADC of the channel to be corrected based on the frequency spectrum conversion result₂Each preset sample delay value of

Significance of corresponding time-interleaved analog-to-digital converter

。

A polynomial fitting step 290 of ADC the channel to be corrected₂Performing polynomial fitting on each preset sampling delay value and the corresponding effective digit of the time-interleaved analog-to-digital converter to obtain the channel ADC to be corrected₂The correction polynomial of (1). In some embodiments, the delay value may be sampled

，

wherein,

Derivation step 300, ADC of channel to be corrected₂The correction polynomial is subjected to derivation to obtain the ADC of the channel to be corrected₂The derivation formula corresponding to the correction polynomial

。

The real number calculation step 310, calculating the channel ADC to be corrected₂The derivation formula corresponding to the correction polynomial of (2) is 0

The real number of the time.

A second effective digit calculating step 320 of ADC the channel to be corrected₂The real number of the correction polynomial corresponding to the derivation equation of 0 is substituted into the channel ADC to be corrected₂The correction polynomial of (2) is calculated to obtain a plurality of significand values corresponding to the respective real roots.

A comparison step 330 of the significant digit, ADC of the channel to be corrected₂Comparing the significant digit values of the plurality of time-interleaved analog-to-digital converters, and selecting the most significant digit value of the time-interleaved analog-to-digital converters.

An optimal sampling delay value obtaining step 340 for obtaining the channel ADC to be corrected₂The real root corresponding to the most significant digit value of the time-interleaved analog-to-digital converter is used as the ADC of the channel to be corrected₂The optimal sample delay value.

A second configuration step 350 of ADC the channel to be corrected₂The optimal sampling delay value is configured into the phase adjusting circuit, so that the phase adjusting circuit ADC is enabled to be according to the channel to be corrected₂To-be-corrected channel ADC₂And carrying out sampling moment mismatch correction. And then, according to the sampling time mismatch correction method, sampling time mismatch correction is sequentially carried out on the rest channels to be corrected.

The main workflow of the calibration method of the present application is explained below.

In one embodiment, the gain mismatch and offset mismatch can be corrected first: controlling to input a plurality of direct current signals with different sizes into the time-interleaved analog-to-digital converter so that a reference channel and each channel to be corrected of the time-interleaved analog-to-digital converter respectively acquire and quantize the plurality of direct current signals with different sizes and output codeword values; respectively carrying out linear fitting on the code word value output by each channel to be corrected and the code word value output by the reference channel to obtain a correction function of each channel to be corrected, calculating an inverse function of the correction function corresponding to each channel to be corrected, and calculating a first configuration value and a second configuration value of each channel to be corrected according to the inverse function of the correction function of each channel to be corrected; and controlling the FPGA processor to store the first configuration value and the second configuration value corresponding to each channel to be corrected so that the FPGA processor performs gain mismatch correction and offset mismatch correction on each channel to be corrected according to the first configuration value and the second configuration value corresponding to each channel to be corrected. Then a sample time mismatch correction can be performed: controlling to input sine wave signals to a time-interleaved analog-to-digital converter, controlling to output initial sampling clock signals, controlling to output a plurality of sampling clock signals to each channel to be corrected according to the initial sampling clock signals and a plurality of preset sampling delay values, so that each channel to be corrected acquires and quantizes the sine wave signals and outputs code word values according to the plurality of sampling clock signals, and transmits the code word values to a central processing unit or an FPGA (field programmable gate array) processor for frequency spectrum conversion, and outputs a frequency spectrum conversion result; and calculating the optimal sampling delay value of each channel to be corrected according to the preset sampling delay value and the spectrum transformation result corresponding to each sampling clock signal of each channel to be corrected, and configuring the optimal sampling delay value of each channel to be corrected into the phase adjusting circuit, so that the phase adjusting circuit performs sampling time mismatch correction on each channel to be corrected according to the optimal sampling delay value of each channel to be corrected. It can be seen that, since the code word values output by each channel to be corrected are respectively subjected to linear fitting with the code word values output by the reference channel to obtain the correction function of each channel to be corrected, the first configuration value and the second configuration value of each channel to be corrected are simultaneously calculated according to the correction function, and the first configuration value and the second configuration value are simultaneously configured in the FPGA processor to complete correction, the invention can simultaneously correct the offset mismatch and the gain mismatch, simplify the correction steps, reduce the difficulty of the correction algorithm, and save the correction time; in addition, the method for searching the optimal sampling delay value of each channel to be corrected through the derivation formula of the correction polynomial only needs to substitute the real number root when the derivation formula is 0 into the correction polynomial to calculate the effective digit of the time-interleaved analog-to-digital converter, so that the delay value of each sampling moment in a phase adjusting circuit is prevented from being respectively output to the corresponding clock signal to the time-interleaved analog-to-digital converter, the optimal delay value corresponding to the maximum effective digit of the time-interleaved analog-to-digital converter is obtained, the correction time is reduced, and the correction precision is improved.

Referring to fig. 12, in one embodiment, the digital oscilloscope includes a memory 10, a processor 20, and an input/output interface 30. The memory 10 is used to store programs. The processor 20 is configured to implement the above-described correction method for the time-interleaved analog-to-digital converter by executing a program stored in the memory. The processor 20 is connected to the memory 10 and the input/output interface 30, respectively, for example, via a bus system and/or other type of connection mechanism. The memory 10 may be used to store programs and data, including a program of a correction method of a time-interleaved analog-to-digital converter involved in an embodiment of the present invention, and the processor 20 executes various functional applications of the digital oscilloscope and data processing by running the program stored in the memory 10.

Those skilled in the art will appreciate that all or part of the functions of the various methods in the above embodiments may be implemented by hardware, or may be implemented by computer programs. When all or part of the functions of the above embodiments are implemented by a computer program, the program may be stored in a computer-readable storage medium, and the storage medium may include: a read only memory, a random access memory, a magnetic disk, an optical disk, a hard disk, etc., and the program is executed by a computer to realize the above functions. For example, the program may be stored in a memory of the device, and when the program in the memory is executed by the processor, all or part of the functions described above may be implemented. In addition, when all or part of the functions in the above embodiments are implemented by a computer program, the program may be stored in a storage medium such as a server, another computer, a magnetic disk, an optical disk, a flash disk, or a removable hard disk, and may be downloaded or copied to a memory of a local device, or may be version-updated in a system of the local device, and when the program in the memory is executed by a processor, all or part of the functions in the above embodiments may be implemented.

The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.

Claims

1. A digital oscilloscope, comprising:

the signal input end is used for acquiring an externally input signal;

2. The digital oscilloscope of claim 1, wherein the central processing unit calculates the first configuration value and the second configuration value of each channel to be corrected according to the correction function of each channel to be corrected, comprising:

3. The digital oscilloscope of claim 1, further comprising:

the phase adjusting circuit is connected between the sampling clock generating circuit and the time-interleaving analog-to-digital converter and is used for storing a plurality of preset sampling delay values of each channel to be corrected relative to the sampling time of the reference channel; the sampling module is further used for outputting a plurality of sampling clock signals to each channel to be corrected according to the initial sampling clock signal and the plurality of preset sampling delay values;

4. The digital oscilloscope of claim 3, wherein the central processing unit calculates the optimal sampling delay value of each channel to be corrected according to the preset sampling delay value and the spectrum transformation result corresponding to each sampling clock signal of each channel to be corrected, and the method comprises the following steps:

5. The digital oscilloscope of claim 4, wherein the central processing unit calculates the optimal sampling delay value of each channel to be corrected according to the correction polynomial of each channel to be corrected, comprising:

6. The digital oscilloscope of claim 5, wherein the central processing unit calculates the optimal sampling delay value of each channel to be corrected according to the derivation formula corresponding to the correction polynomial of each channel to be corrected, and the method comprises the following steps:

7. A method of correcting a time-interleaved analog-to-digital converter, comprising:

a first configuration step, controlling and storing a first configuration value and a second configuration value corresponding to each channel to be corrected, so that the FPGA processor performs gain mismatch correction and offset mismatch correction on each channel to be corrected according to the first configuration value and the second configuration value corresponding to each channel to be corrected;

the correction method further comprises:

8. The correction method according to claim 7, wherein the configuration value calculation step includes:

9. A digital oscilloscope, comprising:

a memory for storing a program;

a processor for implementing the method of any one of claims 7 to 8 by executing a program stored by the memory.