CN113257972B - Silicon-based light emitting diode structure and preparation method thereof - Google Patents
Silicon-based light emitting diode structure and preparation method thereof Download PDFInfo
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- CN113257972B CN113257972B CN202110799492.5A CN202110799492A CN113257972B CN 113257972 B CN113257972 B CN 113257972B CN 202110799492 A CN202110799492 A CN 202110799492A CN 113257972 B CN113257972 B CN 113257972B
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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Abstract
The invention belongs to the technical field of LED chips, and provides a silicon-based light-emitting diode structure which comprises a silicon-based substrate divided into an N electrode area and a P electrode area by an insulation filling area, wherein N welding electrodes and P welding electrodes are respectively arranged on the bottom surfaces of the silicon-based substrate of the N electrode area and the P electrode area; the front surface of the silicon-based substrate in the N electrode area is sequentially provided with an N-GaN layer, a quantum well layer, a P-GaN layer and a transparent conducting layer from bottom to top, a passivation insulating layer covering the insulating filling area is arranged above the transparent conducting layer, a P electrode transmission layer extending to and covering the silicon-based substrate in the P electrode area is arranged above the passivation insulating layer, and the P electrode transmission layer is respectively in contact connection with the transparent conducting layer and the silicon-based substrate in the P electrode area through an exposed area on the passivation insulating layer. The invention can realize the electrical connection with the packaging substrate without welding wires, does not consider the problems of substance diffusion resistance, unstable performance, poor weldability and the like, and can be made into a required special-shaped appearance structure according to requirements.
Description
Technical Field
The invention relates to the technical field of LED chips, in particular to a silicon-based light-emitting diode structure and a preparation method thereof.
Background
A Light Emitting Diode (LED) is a solid semiconductor device capable of converting electric energy into visible Light, and is widely used in the fields of display screens, traffic signals, display Light sources, lamps for automobiles, LED backlight sources, illumination Light sources, and the like. Substrates mainly used for LED epitaxy can be classified into transparent and non-transparent. The transparent substrate is represented by sapphire and silicon carbide, is mainly characterized by non-conductivity, low in visible light wave band absorption rate and transparent; opaque substrates are represented by silicon, gallium arsenide, and are primarily characterized as being conductive and appearing opaque.
The transparent non-conductive sapphire substrate and silicon carbide substrate epitaxy is easy to process into a flip chip structure and a forward chip structure, and the opaque conductive silicon substrate and gallium arsenide substrate epitaxy is easy to process into a forward chip structure and a vertical chip structure. Just adorn structure and vertical structure and all need realize electric continuous through welding gold thread and packaging substrate, flip structure can make the electrode direct carry out the solder to combine to form electric continuous with packaging substrate's electrode, therefore flip chip's preparation does not have the step of bonding wire, the yields of production is high, the technological process is few, and flip chip structure's stability also is superior to the bonding wire technology, but because flip chip's chip face is directly adjacent with the solder, long-time work, diffusion between the material can lead to the stability of chip to descend, in addition, sapphire base, the epitaxial special-shaped appearance shape of taking the substrate that all is difficult to process according to the demand of carborundum base. The opaque conductive silicon-based or gallium arsenide-based epitaxy is required to be made into a flip-chip structure, and the process is difficult because the epitaxy layer is usually transferred to a transparent substrate and then the flip-chip structure is prepared.
Disclosure of Invention
The present inventors have conducted intensive studies to overcome the above-identified drawbacks of the prior art, and as a result, have completed the present invention after having made a great deal of creative efforts.
Specifically, the technical problems to be solved by the present invention are: the silicon-based light emitting diode structure and the preparation method thereof are provided to realize coplanarity of two electrodes of an opaque substrate on packaging, realize electrical connection with a packaging substrate without welding wires, and simultaneously avoid direct adjacency of a chip surface of a flip chip and a welding flux so as to avoid the technical problem of performance stability reduction of the chip caused by diffusion of substances in long-term work.
In order to solve the technical problems, the technical scheme of the invention is as follows:
a silicon-based light emitting diode structure comprises a silicon-based substrate, wherein the silicon-based substrate is divided into an N electrode area and a P electrode area through an insulation filling area, and N welding electrodes and P welding electrodes are respectively arranged on the bottom surfaces of the silicon-based substrate in the N electrode area and the P electrode area;
n electrode zone silicon-based substrate openly from bottom to top is equipped with N-GaN layer, quantum well layer, P-GaN layer and transparent conducting layer in proper order, the top of transparent conducting layer is equipped with the passivation insulating layer, the passivation insulating layer covers insulating filling area, just the passivation insulating layer has the etching respectively extremely transparent conducting layer and P electrode zone silicon-based substrate's the district that exposes, the top of passivation insulating layer is equipped with P electrode transmission layer, P electrode transmission layer extends and covers to P electrode zone silicon-based substrate, just P electrode transmission layer passes through expose on the passivation insulating layer district respectively with transparent conducting layer, P electrode zone silicon-based substrate contact connection.
As an improved technical scheme, the thickness of the silicon-based substrate is 10-95 mu m, the thickness of the N-GaN layer is 2-4 mu m, the thickness of the quantum well layer is 0.1-0.3 mu m, and the thickness of the P-GaN layer is 0.2-0.4 mu m.
As an improved technical scheme, the transparent conducting layer is an ITO film with the thickness of 100-400 angstroms or a Ni/Au metal film with the thickness of 10 angstroms/50 angstroms.
As an improved technical solution, the insulation filling region is an insulation material filling region of at least one of silicone resin, epoxy resin, polyacrylate, polyamide, benzocyclobutene, polyimide, SU8 glue, and a surface of the insulation filling region is flush with a surface of the silicon-based substrate.
As an improved technical scheme, the passivation insulating layer comprises an Al2O3 film with the thickness of 15-25 angstroms and a silicon dioxide or silicon nitride film with the thickness of 400-600 angstroms and grown on the Al2O3 film.
As an improved technical scheme, the N welding electrode, the P welding electrode and the P electrode transmission layer are all of a multilayer metal structure of Cr, Ni, Ti, Pt, Cu and Au, the thickness of the P electrode transmission layer is 0.3-1 mu m, and the uppermost layer of the P electrode transmission layer is a black metal layer.
The invention also provides a preparation method of the silicon-based light-emitting diode structure, which comprises the following steps:
s1, providing a silicon-based substrate, and sequentially preparing an N-GaN layer, a quantum well layer and a P-GaN layer on the silicon-based substrate to obtain a silicon-based epitaxial wafer structure;
s2, preparing an ohmic contact layer on the P-GaN layer, photoetching and etching the ohmic contact layer, and cleaning to remove photoresist to prepare a transparent conducting layer;
s3, making a photoresist pattern of the MESA reserved region on the whole surface through photoetching, etching the non-reserved region to the silicon-based substrate, and then cleaning to remove the photoresist;
s4, making a photoresist pattern of a non-deep etching area on the whole surface through photoetching, then carrying out deep etching on the silicon-based substrate of the deep etching area, and then cleaning to remove the photoresist;
s5, filling the deep etching area in the step S4 with an insulating material to obtain an insulating filling area;
s6, preparing a passivation insulating layer covering the insulating filling area, making a photoresist pattern in an area where the electrode is not required to be exposed through whole-surface photoetching, etching the area where the electrode is required to be exposed to the transparent conducting layer, and cleaning to remove the photoresist;
s7, photoetching the whole surface to expose the region needing to be plated with the transmission metal layer, depositing a metal film in a thermal evaporation mode, stripping the photoresist, and cleaning to obtain a P electrode transmission layer;
s8, photoetching the whole surface to form a required special-shaped photoresist pattern, and then deeply etching the unprotected area of the photoresist to obtain a special-shaped structure;
s9, thinning the silicon-based substrate;
s10, photoetching the bottom surface of the silicon substrate to expose the area needing to be plated with the P/N welding electrode, depositing a layer of metal film in a thermal evaporation mode, peeling off the photoresist, cleaning to obtain the P welding electrode and the N welding electrode, and realizing the preparation of the welding electrode.
As an improved technical scheme, in step S1, the thickness of the silicon-based substrate is 400-600 μm, and a N-GaN layer with a thickness of 2-4 μm, a quantum well layer with a thickness of 0.1-0.3 μm, and a P-GaN layer with a thickness of 0.2-0.4 μm are sequentially grown on the front surface of the silicon-based substrate to obtain a silicon-based epitaxial wafer structure.
As an improved technical scheme, in step S2, an ITO thin film is prepared on the P-GaN layer of the silicon-based epitaxial wafer by super or thermal evaporation, the thickness is 100-400 angstroms, then the ITO thin film is placed in a rapid annealing furnace, the furnace is kept at 550 ℃ in a nitrogen atmosphere for 3 minutes, so that the ITO thin film forms the ohmic contact layer, then a photoresist pattern of the ohmic contact layer in a region needing to be reserved is made, the ohmic contact layer not covering the photoresist region is removed by a wet etching process, and finally the photoresist is cleaned and removed by using an organic solvent, so as to obtain the transparent conductive layer.
As an improved technical solution, in step S3, after a photoresist pattern of the MESA remaining region is formed by a photolithography process, the epitaxial structure not covering the photoresist region is etched by an ICP or RIE process to the silicon-based substrate, and then the photoresist is cleaned and removed by using an organic solvent.
As an improved technical scheme, in step S4, after a photoresist pattern of a non-deep etching region is formed by a photolithography process, a deep etching region of a silicon-based substrate not covered with a photoresist is etched in a laser or deep silicon etching manner to an etching depth of 10 to 100 μm, and then the photoresist is removed by using an organic solvent and cleaned.
As an improved technical solution, in step S5, the deep etching region is filled with at least one of silicone resin, epoxy resin, polyacrylate, polyamide, benzocyclobutene, polyimide, and SU8 glue, and after filling, the surface of the filling base is modified by using a plasma etching process, so that the upper surface of the insulating filling region is modified to be flat with the upper surface of the silicon-based substrate.
As an improved technical scheme, in step S6, an atomic layer deposition process is adopted to deposit an Al2O3 film with the thickness of 15-25 angstroms, then a silicon dioxide or silicon nitride film with the thickness of 400-600 angstroms is grown through PECVD to prepare the passivation insulating layer, then a photoresist pattern which does not need to expose an electrode region is made through whole-surface photoetching, the electrode exposed region which does not cover the photoresist is etched to the transparent conducting layer in an ion etching or chemical etching mode to expose the transparent conducting layer, and then the photoresist is cleaned and removed by using an organic solvent.
As an improved technical scheme, in step S7, depositing a multilayer metal structure of Cr, Ni, Ti, Pt, Cu, and Au by thermal evaporation to form a metal thin film layer for transmission, where the total thickness of the deposition is 0.3 to 1 μm, and the last layer of the deposited metal structure is a black metal, and the metal thin film layer obtained by deposition is filled in the electrode exposed region in step S6 and contacts with the exposed transparent conductive layer to realize connection.
As an improved technical scheme, in step S8, the special-shaped etching of the structure is realized by a deep silicon etching mode, and the etching depth is 100-150 mu m.
As an improved technical scheme, in step S9, adhering the semi-finished product processed in step S8 to a temporary substrate through a temporary adhesive material (wax or UV glue), polishing the bottom surface of the silicon-based substrate, reducing the thickness of the entire silicon-based substrate to 10-95 μm, cleaning the reduced structure, and then processing the polished bottom surface with plasma to remove bottom surface contaminants of the silicon-based substrate.
As an improved technical scheme, in the step S10, the deposited metal thin film layer for the welding electrode is of a multilayer metal structure of Cr, Ni, Ti, Pt, Cu and Au, and the total thickness of the deposition is 2-5 mu m.
After the technical scheme is adopted, the invention has the beneficial effects that:
the silicon-based light-emitting diode structure realizes that the two electrodes of an opaque substrate are coplanar on a package, the silicon-based substrate is divided into two areas through an insulation filling area, and the current of P is led to the back from the front side of the silicon-based substrate; in addition, this silicon-based light emitting diode structure can make to required special-shaped appearance structure according to the demand, and chip surface the superiors are ferrous metal, has improved the contrast of chip in demonstration application, and when carrying out with the packaging substrate welding, can mainly use Cu as electrically conductive welded main part, and relative traditional LED chip structure has avoided using noble metal in a large number when the welding, manufacturing cost greatly reduced.
Drawings
In order to more clearly illustrate the detailed description of the invention or the technical solutions in the prior art, the drawings that are needed in the detailed description of the invention or the prior art will be briefly described below. Throughout the drawings, like elements or portions are generally identified by like reference numerals. In the drawings, elements or portions are not necessarily drawn to scale.
FIG. 1 is a schematic structural diagram of a silicon-based LED according to the present invention;
FIG. 2 is a schematic perspective view of a silicon-based LED according to the present invention;
FIG. 3 is a schematic perspective view of a silicon-based LED according to the present invention;
FIG. 4 is a flow chart of a method for fabricating a silicon-based light emitting diode structure according to the present invention;
reference numerals: 1-a silicon-based substrate; 2-insulating filled region; 3-N welding electrodes; 4-P welding electrode; a 5-N-GaN layer; a 6-quantum well layer; a 7-P-GaN layer; 8-a transparent conductive layer; 9-passivating the insulating layer; 10-P electrode transport layer.
Detailed Description
The invention is further illustrated by the following specific examples. The use and purpose of these exemplary embodiments are to illustrate the present invention, not to limit the actual scope of the present invention in any way, and not to limit the scope of the present invention in any way.
As shown in fig. 1 to fig. 3, the present embodiment provides a silicon-based light emitting diode structure, which includes a silicon-based substrate 1, the silicon-based substrate 1 is divided into an N electrode region and a P electrode region by an insulation filling region 2, and the bottom surfaces of the silicon-based substrate 1 in the N electrode region and the P electrode region are respectively provided with an N welding electrode 3 and a P welding electrode 4.
The front surface of the silicon-based substrate 1 in the N electrode region is sequentially provided with an N-GaN layer 5, a quantum well layer 6, a P-GaN layer 7 and a transparent conducting layer 8 from bottom to top, a passivation insulating layer 9 is arranged above the transparent conducting layer 8, the passivation insulating layer 9 covers the insulation filling region 2, the passivation insulating layer 9 is provided with an exposed region of the silicon-based substrate 1 etched to the transparent conducting layer 8 and the P electrode region respectively, a P electrode transmission layer 10 is arranged above the passivation insulating layer 9, the P electrode transmission layer 10 extends to and covers the silicon-based substrate 1 in the P electrode region, and the P electrode transmission layer 10 is in contact connection with the transparent conducting layer 8 and the silicon-based substrate 1 in the P electrode region through the exposed region on the passivation insulating layer 9.
In this embodiment, the thickness of the silicon-based substrate 1 is 10 to 95 μm, the thickness of the N-GaN layer 5 is 2 to 4 μm, the thickness of the quantum well layer 6 is 0.1 to 0.3 μm, and the thickness of the P-GaN layer 7 is 0.2 to 0.4 μm.
In this embodiment, the transparent conductive layer 8 is an ITO film with a thickness of 100-400 angstroms or a Ni/Au metal film with a thickness of 10 angstroms/50 angstroms.
In this embodiment, the insulating filling region 2 is an insulating material filling region of at least one of silicone resin, epoxy resin, polyacrylate, polyamide, benzocyclobutene, polyimide, and SU8 glue, and the surface of the insulating filling region 2 is flush with the surface of the silicon-based substrate 1.
In this embodiment, the passivation insulating layer 9 includes an Al2O3 film with a thickness of 15-25 angstroms and a silicon dioxide or silicon nitride film with a thickness of 400-600 angstroms grown on the Al2O3 film, the Al2O3 film plays a role in protection, and the silicon dioxide or silicon nitride film makes the passivation insulating layer 9 reach a certain thickness.
In this embodiment, the N welding electrode 3, the P welding electrode 4, and the P electrode transmission layer 10 are all multilayer metal structures of Cr, Ni, Ti, Pt, Cu, and Au, the thickness of the P electrode transmission layer 10 is 0.3 to 1 μm, and the uppermost layer of the P electrode transmission layer 10 is a black metal layer. In this embodiment, the uppermost layer of the P electrode transport layer 10 is Cr.
The embodiment also provides a method for manufacturing the silicon-based light emitting diode structure, as shown in fig. 4, which includes the following steps:
s1, providing a silicon-based substrate, and sequentially preparing an N-GaN layer, a quantum well layer and a P-GaN layer on the silicon-based substrate to obtain a silicon-based epitaxial wafer structure;
in the step, the thickness of the silicon-based substrate is 400-600 mu m, an N-GaN layer with the thickness of 2-4 mu m, a quantum well layer with the thickness of 0.1-0.3 mu m and a P-GaN layer with the thickness of 0.2-0.4 mu m are sequentially grown on the front surface of the silicon-based substrate to obtain a silicon-based epitaxial wafer structure, and the preparation process of the silicon-based epitaxial wafer structure is disclosed by the technical personnel in the field, so the details are not described herein; in this embodiment, the thickness of the selected silicon-based substrate is 500 μm, the thickness of the prepared N-GaN layer is 3 μm, the thickness of the quantum well layer is 0.2 μm, and the thickness of the P-GaN layer is 0.3 μm.
S2, preparing an ohmic contact layer on the P-GaN layer, photoetching and etching the ohmic contact layer, and cleaning to remove photoresist to prepare a transparent conductive layer;
in this step, two preparation methods can be selected for the preparation of the ohmic contact layer. One is to prepare an ITO film on a silicon-based epitaxial wafer structure by means of super, thermal evaporation and the like, wherein the thickness is 100-400 angstroms, and then the ITO film is placed in a rapid annealing furnace and is kept for 3 minutes under the condition of enclosing and keeping 550 ℃ in a nitrogen atmosphere, so that the ITO film forms an ohmic contact layer; the other method is that a Ni/Au film is prepared on a silicon-based epitaxial wafer structure by means of thermal evaporation and the like, the thickness of the Ni/Au film is 10/50 angstroms, then the Ni/Au film is placed in a rapid annealing furnace, and the Ni/Au film is annealed for 30 minutes at the furnace temperature of 450 ℃ under the condition that pure N2/O2 is mixed into air, so that an ohmic contact layer is formed on the Ni/Au film.
Because the metal film has poor light transmittance in the visible light band, generally has a transmittance of only 50%, and the transmittance of the ITO film can reach more than 90%, in this embodiment, the ITO film process is preferably used to prepare the ohmic contact layer; the ITO film (indium tin oxide semiconductor transparent conductive film) is an n-type semiconductor material, has low resistivity, high conductivity, high visible light transmittance, high mechanical hardness and good chemical stability, meets the requirements of good conductivity and light transmittance, and has good service performance, such as an Sn-doped In2O3 film.
In this embodiment, a photoresist pattern of a region of the ohmic contact layer, which needs to be reserved, is formed through a photolithography process, then the ohmic contact layer which does not cover the photoresist region is removed through a wet etching process, and then the photoresist is cleaned and removed by using an organic solvent, so that the transparent conductive layer is prepared.
S3, making a photoresist pattern of the MESA reserved region on the whole surface by photoetching, etching the non-reserved region to the silicon-based substrate, and cleaning to remove the photoresist;
in the step, after a photoresist pattern of an MESA reserved area is made through a photoetching process, an epitaxial structure which does not cover the photoresist area is etched through an ICP (inductively coupled plasma) or RIE (reactive ion etching) process until a silicon-based substrate is etched, and then the photoresist is cleaned and removed by using an organic solvent; in this embodiment, the thickness of the etching in this step is about 3.5 μm, that is, the N-GaN layer, the quantum well layer, and the P-GaN layer on the silicon-based substrate are etched.
S4, making a photoresist pattern of a non-deep etching area on the whole surface through photoetching, then carrying out deep etching on the silicon substrate of the deep etching area, and then cleaning to remove the photoresist;
in the step, after a photoresist pattern of a non-deep etching area is formed through a photoetching process, a laser or deep silicon etching mode is adopted to etch the deep etching area of the silicon-based substrate which is not covered with the photoresist, the etching depth is 10-100 mu m, and then the photoresist is removed through an organic solvent and cleaned.
In the embodiment, the deep etching processing of the silicon substrate is realized by preferably selecting a deep silicon etching mode, the etching uniformity is good, and no pollution is introduced after the process processing.
S5, filling the deep etching area in the step S4 with an insulating material to obtain an insulating filling area;
in the step, at least one of silicon resin, epoxy resin, polyacrylate, polyamide, benzocyclobutene, polyimide and SU8 glue is used for filling the deep etching area, and the deep etching area can be effectively filled in a multi-time filling mode by considering the shrinkage characteristic existing in the curing process of the filling material.
In this embodiment, after the deep etching region is filled, the surface of the filling base is modified by using a plasma etching process, so that the insulating filling region and the upper surface of the silicon-based substrate are kept flat.
After the step of processing, the top of the silicon-based substrate is divided into two areas by the insulation filling area, the N-GaN layer, the quantum well layer, the P-GaN layer and the transparent conducting layer are all located on the silicon-based substrate of one area, and the silicon-based substrate of the other area is free of an epitaxial structure.
S6, preparing a passivation insulating layer covering the insulating filling area, making a photoresist pattern in the area where the electrode is not required to be exposed through whole-surface photoetching, etching the area where the electrode is required to be exposed to the transparent conducting layer, and cleaning to remove the photoresist;
in the step, firstly, an Al2O3 film is deposited by adopting an atomic layer deposition process, the thickness is 15-25 angstroms, the protection effect is achieved, then a silicon dioxide or silicon nitride film is grown by PECVD, the thickness is 400-600 angstroms, and a passivation insulating layer is prepared; the Al2O3 film layer has a more compact structure, so that the airtightness of the chip is better, the capability of resisting the diffusion of substances of the chip is enhanced, and the insulating layer needs to be made to a certain thickness by using silicon nitride or silicon dioxide due to the problem of film stress and the fact that the chip cannot be made to be too thick.
In the step, after a photoresist pattern which does not need to expose the electrode region is formed through whole-surface photoetching, the electrode exposed region which is not covered with the photoresist is etched to the transparent conducting layer in an ion etching or chemical corrosion mode, the transparent conducting layer is exposed, and then the photoresist is cleaned and removed by using an organic solvent.
S7, photoetching the whole surface to expose the area needing to be plated with the transmission metal layer, depositing a metal film in a thermal evaporation mode, then stripping photoresist (Lift-off), and cleaning to obtain a P electrode transmission layer;
in the step, the deposited metal thin film layer for transmission is of a multilayer metal structure of Cr, Ni, Ti, Pt, Cu, Au and the like, the total thickness of the metal thin film layer is 0.3-1 mu m, and the last layer of metal structure is of ferrous metal, such as Cr, so that the chip can have better contrast in a display scene.
After the processing in this step, the obtained P-electrode transmission layer is filled in the electrode exposed region in step S6, and contacts with the exposed transparent conductive layer, so as to realize connection.
S8, photoetching the whole surface to form a required special-shaped photoresist pattern, and then deeply etching the unprotected area of the photoresist to obtain a special-shaped structure;
in the step, the special-shaped etching is realized in a deep silicon etching mode, the etching depth is 100-150 mu m, and the special-shaped appearance can be various required appearance shapes such as rhombus, parallelogram and the like. Sapphire base and silicon carbide base are very difficult to process into the special-shaped LED with the substrate, which is the key point that silicon base is selected as the substrate in the embodiment, and gallium arsenide base can be selected as the substrate, and the method is not limited to the material selection of the substrate.
In particular, in this step, an etching gas different from that used for silicon etching is selected according to the insulating material filled in the insulating filling region in the step S5, and alternating etching is performed in the same process, or after the profile of the silicon-based substrate is separately etched, ICP etching of the insulating filling region in the step S5 may be performed in another process.
S9, thinning the silicon-based substrate;
in the step, the semi-finished product processed in the step 8 is adhered to a temporary substrate through temporary adhesive materials such as wax and UV glue, the bottom surface of the silicon-based substrate is polished, and the thickness of the whole silicon-based substrate is reduced to 10-95 mu m. In this embodiment, the thinning thickness of the silicon-based substrate corresponds to the deep etching depth in step 4, i.e., the silicon-based substrate is thinned until the insulating filling region leaks, so that the silicon-based substrate is insulated and separated from the two regions separated by the insulating filling region, and no electrical connection is made.
In this step, the coarse grain grinding process may be performed first to thin the silicon-based substrate to a certain extent, but since the hardness of the silicon-based substrate is low, although the grinding can achieve the rapid thinning, the damage to the silicon-based substrate is much greater than that of the polishing process, and therefore, in this embodiment, the polishing process is preferably used to achieve the thinning of the silicon-based substrate.
After the silicon-based substrate is polished and thinned, the thinned structure is cleaned, and the polished bottom surface is treated by plasma to remove the bottom surface contamination of the silicon-based substrate so as to improve the adhesion during subsequent metal film plating.
S10, photoetching the bottom surface of the silicon substrate to expose the area needing to be plated with the P/N welding electrode, depositing a layer of metal film in a thermal evaporation mode, peeling off photoresist (Lift-off), cleaning to obtain the P welding electrode and the N welding electrode, and realizing the preparation of the welding electrode.
In the step, the deposited metal film layer for the welding electrode is of a multilayer metal structure of Cr, Ni, Ti, Pt, Cu, Au and the like, and the total deposited thickness is 2-5 mu m.
The silicon-based light emitting diode structure prepared based on the method realizes that the two electrodes of the opaque substrate are coplanar on the package, the silicon-based substrate 1 is divided into two areas through the insulation filling area 2, the current of P is led to the back from the front side through the silicon-based substrate, the back electrode of the structure is used as a welding area due to the welding of the electrode on the back side, the electrical connection with the package substrate can be realized without welding wires, and the problems of substance diffusion resistance, unstable performance, poor weldability and the like are not considered after the electrode and the package substrate are subjected to welding flux combination, so that the silicon-based light emitting diode structure is strong in practicability, and the influence and damage of the welding flux migration on the chip surface are avoided.
This silicon-based emitting diode structure adopts the silicon-based substrate, can make to required special-shaped appearance structure according to the demand, and chip surface the superiors are ferrous metal, has improved the contrast of chip in demonstration application, and when this silicon-based emitting diode structure carries out with the packaging substrate welding, can mainly use Cu as conductive bonding's main part, and relative traditional LED chip structure has avoided using noble metal in a large number when welding, manufacturing cost greatly reduced.
It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should also be understood that various alterations, modifications and/or variations can be made to the present invention by those skilled in the art after reading the technical content of the present invention, and all such equivalents fall within the protective scope defined by the claims of the present application.
Claims (10)
1. A silicon-based light emitting diode structure is characterized in that: the silicon-based substrate is divided into an N electrode area and a P electrode area through an insulation filling area, and N welding electrodes and P welding electrodes are respectively arranged on the bottom surfaces of the silicon-based substrate in the N electrode area and the P electrode area;
n electrode zone silicon-based substrate openly from bottom to top is equipped with N-GaN layer, quantum well layer, P-GaN layer and transparent conducting layer in proper order, the top of transparent conducting layer is equipped with the passivation insulating layer, the passivation insulating layer covers insulating filling area, just the passivation insulating layer has the etching respectively extremely transparent conducting layer and P electrode zone silicon-based substrate's the district that exposes, the top of passivation insulating layer is equipped with P electrode transmission layer, P electrode transmission layer extends and covers to P electrode zone silicon-based substrate, just P electrode transmission layer passes through expose on the passivation insulating layer district respectively with transparent conducting layer, P electrode zone silicon-based substrate contact connection.
2. The silicon-based led structure of claim 1, wherein: the thickness of the silicon-based substrate is 10-95 mu m, the thickness of the N-GaN layer is 2-4 mu m, the thickness of the quantum well layer is 0.1-0.3 mu m, and the thickness of the P-GaN layer is 0.2-0.4 mu m.
3. The silicon-based led structure of claim 2, wherein: the transparent conducting layer is an ITO film with the thickness of 100-400 angstroms or a Ni/Au metal film with the thickness of 10 angstroms/50 angstroms;
the insulation filling area is an insulation material filling area made of at least one of silicon resin, epoxy resin, polyacrylate, polyamide, benzocyclobutene, polyimide and SU8 glue, and the surface of the insulation filling area is flush with the surface of the silicon-based substrate;
the passivation insulating layer comprises an Al2O3 film with the thickness of 15-25 angstroms and a silicon dioxide or silicon nitride film with the thickness of 400-600 angstroms and grown on the Al2O3 film;
the N welding electrode, the P welding electrode and the P electrode transmission layer are all of a multilayer metal structure of Cr, Ni, Ti, Pt, Cu and Au, the thickness of the P electrode transmission layer is 0.3-1 mu m, and the uppermost layer of the P electrode transmission layer is a black metal layer.
4. A method for fabricating a silicon-based light emitting diode structure according to claim 1, wherein: the method comprises the following steps:
s1, providing a silicon-based substrate, and sequentially preparing an N-GaN layer, a quantum well layer and a P-GaN layer on the silicon-based substrate to obtain a silicon-based epitaxial wafer structure;
s2, preparing an ohmic contact layer on the P-GaN layer, photoetching and etching the ohmic contact layer, and cleaning to remove photoresist to prepare a transparent conducting layer;
s3, making a photoresist pattern of the MESA reserved region on the whole surface through photoetching, etching the non-reserved region to the silicon-based substrate, and then cleaning to remove the photoresist;
s4, making a photoresist pattern of a non-deep etching area on the whole surface through photoetching, then carrying out deep etching on the silicon-based substrate of the deep etching area, and then cleaning to remove the photoresist;
s5, filling the deep etching area in the step S4 with an insulating material to obtain an insulating filling area;
s6, preparing a passivation insulating layer covering the insulating filling area, making a photoresist pattern in an area where the electrode is not required to be exposed through whole-surface photoetching, etching the area where the electrode is required to be exposed to the transparent conducting layer, and cleaning to remove the photoresist;
s7, photoetching the whole surface to expose the region needing to be plated with the transmission metal layer, depositing a metal film in a thermal evaporation mode, stripping the photoresist, and cleaning to obtain a P electrode transmission layer;
s8, photoetching the whole surface to form a required special-shaped photoresist pattern, and then deeply etching the unprotected area of the photoresist to obtain a special-shaped structure;
s9, thinning the silicon-based substrate;
s10, photoetching the bottom surface of the silicon substrate to expose the area needing to be plated with the P/N welding electrode, depositing a layer of metal film in a thermal evaporation mode, peeling off the photoresist, cleaning to obtain the P welding electrode and the N welding electrode, and realizing the preparation of the welding electrode.
5. The method of claim 4, wherein the step of forming the silicon-based light emitting diode structure comprises: in step S2, an ITO thin film is prepared on the P-GaN layer of the silicon-based epitaxial wafer by super or thermal evaporation, with a thickness of 100-400 angstroms, and then placed in a rapid annealing furnace, and kept at 550 ℃ under a nitrogen atmosphere for 3 minutes, so that the ITO thin film forms the ohmic contact layer, and then a photoresist pattern of a region of the ohmic contact layer that needs to be preserved is made, the ohmic contact layer that does not cover the photoresist region is removed by a wet etching process, and finally the photoresist is cleaned and removed by using an organic solvent, so as to obtain the transparent conductive layer.
6. The method of claim 5, wherein the step of forming the silicon-based light emitting diode structure comprises: in step S4, after a photoresist pattern of a non-deep etching area is formed through a photoetching process, etching the deep etching area of the silicon-based substrate which is not covered with the photoresist in a laser or deep silicon etching mode, wherein the etching depth is 10-100 mu m, then removing the photoresist by using an organic solvent, and cleaning;
in step S5, the deep etching region is filled with at least one of silicone resin, epoxy resin, polyacrylate, polyamide, benzocyclobutene, polyimide, and SU8 glue, and after filling, the surface of the filling base is modified by a plasma etching process, so that the upper surface of the insulating filling region is modified to be flat with the upper surface of the silicon-based substrate.
7. The method of claim 6, wherein: in step S6, an atomic layer deposition process is used to deposit an Al2O3 thin film with a thickness of 15-25 angstroms, a silicon dioxide or silicon nitride thin film with a thickness of 400-600 angstroms is grown by PECVD to prepare the passivation insulating layer, a photoresist pattern not requiring an exposed electrode region is formed by full-surface lithography, the exposed electrode region not covered with the photoresist is etched to the transparent conductive layer by ion etching or chemical etching to expose the transparent conductive layer, and then the photoresist is removed by organic solvent.
8. The method of claim 7, wherein: in step S7, depositing a multilayer metal structure of Cr, Ni, Ti, Pt, Cu and Au by means of thermal evaporation to form a metal film layer for transmission, wherein the total thickness of the deposition is 0.3-1 [ mu ] m, and the last layer of the deposited metal structure is ferrous metal.
9. The method of claim 8, wherein: in step S8, the special-shaped etching of the structure is realized by a deep silicon etching mode, and the etching depth is 100-150 mu m.
10. The method of claim 9, wherein the step of forming the silicon-based led structure comprises: in step S9, the semi-finished product processed in step S8 is adhered to a temporary substrate through a temporary adhesive material, the bottom surface of the silicon-based substrate is polished, the thickness of the whole silicon-based substrate is reduced to 10-95 mu m, then the reduced structure is cleaned, the polished bottom surface is processed through plasma, and bottom surface contamination of the silicon-based substrate is removed.
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| CN116387428B (en) * | 2023-06-02 | 2024-03-15 | 江西兆驰半导体有限公司 | LED chip preparation method |
| CN116613626B (en) * | 2023-07-21 | 2023-09-26 | 南昌凯迅光电股份有限公司 | AuSn electrode back surface light emitting VCSEL chip and preparation method thereof |
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