CN113255271A - Automatic verification system and method for IO pin of chip - Google Patents
Automatic verification system and method for IO pin of chip Download PDFInfo
- Publication number
- CN113255271A CN113255271A CN202110535984.3A CN202110535984A CN113255271A CN 113255271 A CN113255271 A CN 113255271A CN 202110535984 A CN202110535984 A CN 202110535984A CN 113255271 A CN113255271 A CN 113255271A
- Authority
- CN
- China
- Prior art keywords
- pin
- tested
- module
- auxiliary
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67294—Apparatus for monitoring, sorting or marking using identification means, e.g. labels on substrates or labels on containers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Evolutionary Computation (AREA)
- General Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The system comprises a chip module to be tested with a built-in chip program to be tested and an auxiliary verification module connected with the chip module to be tested; the chip module to be tested comprises a plurality of IO pins, the auxiliary verification module comprises a plurality of auxiliary pins, and each IO pin is correspondingly connected with one auxiliary pin; the auxiliary verification module is used for acquiring and controlling a corresponding auxiliary pin to output a first level signal according to a signal input instruction, and transmitting the first level signal to an IO pin to be detected of the chip module to be detected through the corresponding auxiliary pin; and the chip module to be tested is used for operating the chip program to be tested to determine the IO pin to be tested, sending a signal input instruction to the auxiliary verification module and detecting whether the IO pin to be tested is normal or not according to the level signal. The method and the device are used for solving the problem that the coverage rate of IO pin verification of the chip in the prior art is complex to realize.
Description
Technical Field
The application relates to the field of chips, in particular to an automatic verification system and method for IO pins of a chip.
Background
Later discovery in the chip design process results in higher wasted cost, and particularly after tape out, a serious problem may need to be tape out again, resulting in high cost and also causing a serious delay of the project. The Input/Output (IO) pin interfaces included in the chip are numerous, and verification can be completed quickly and at a high coverage rate, so that the chip can find defects in time, and the quality of the chip is improved.
At present, the following schemes are mainly used for verifying the IO pins of the chip:
scheme 1: the manual random extraction part of pins directly configures the register, and the verification content is very limited.
Scheme 2: and generating partial configuration items through a tool, and verifying all the IO pins of the chip by using a special auxiliary board.
The existing scheme has the following defects:
scheme 1: and all chip IO pins cannot be covered by pure manual testing.
Scheme 2: the special auxiliary board is needed, the control logic of the auxiliary board is complex, the implementation process is more, and errors are easy to cause abnormity.
Disclosure of Invention
In view of this, the present application provides a system and a method for automatically verifying an IO pin of a chip, so as to solve the problem that in the prior art, the coverage rate of the IO pin verification of the chip is complex to implement.
In a first aspect, an embodiment of the present application provides an automatic verification system for an IO pin of a chip, including: a chip module to be tested with a built-in chip program to be tested and an auxiliary verification module connected with the chip module to be tested; wherein the content of the first and second substances,
the chip module to be tested comprises a plurality of IO pins, the auxiliary verification module comprises a plurality of auxiliary pins, each IO pin is correspondingly connected with one auxiliary pin, and one IO pin is only correspondingly connected with one auxiliary pin;
the auxiliary verification module is used for acquiring and controlling a corresponding auxiliary pin to output a first level signal according to a signal input instruction, and transmitting the first level signal to an IO pin to be detected of the chip module to be detected through the corresponding auxiliary pin; the first level signal is a level signal required for the chip module to be tested to detect whether an IO pin of the chip module to be tested is normal or not;
the chip module to be tested is used for operating the IO pin to be tested is determined by the chip program to be tested, the signal input instruction is sent to the auxiliary verification module according to the IO pin to be tested, and whether the IO pin to be tested is normal or not is detected according to the level signal received by the IO pin to be tested.
Preferably, the chip module to be tested includes: the system comprises a to-be-tested chip submodule and a first processor, wherein the to-be-tested chip submodule is internally provided with a chip program to be tested and comprises a plurality of IO pins; the secondary verification module includes: the system comprises an auxiliary verification sub-module and a second processor, wherein the auxiliary verification sub-module comprises a plurality of auxiliary pins, and the second processor is connected with the auxiliary verification sub-module;
the chip module to be tested and the auxiliary verification module are connected and comprise:
the first processor is connected with the second processor, and an IO pin of the to-be-tested chip sub-module is correspondingly connected with an auxiliary pin of the auxiliary verification sub-module;
the to-be-tested chip submodule is used for operating the to-be-tested chip program to determine an IO pin to be tested and sending request information of a pin input signal to the first processor according to the IO pin to be tested;
the first processor is used for receiving the request information of the pin input signal and sending the request information of a signal input instruction to the second processor according to the request information of the pin input signal; the request information of the signal input instruction is used for requesting an auxiliary pin corresponding to the auxiliary verification submodule to output information of a first level signal;
the second processor is used for acquiring request information of a signal input instruction and sending the signal input instruction to the auxiliary verification submodule according to the request information of the signal input instruction;
the auxiliary verification sub-module is used for receiving and controlling a corresponding auxiliary pin to output a first level signal according to the signal input instruction, and transmitting the first level signal to an IO pin to be tested of the to-be-tested chip sub-module;
the to-be-tested chip sub-module is further configured to receive the first level signal output by the auxiliary verification sub-module through an auxiliary pin through the to-be-tested IO pin;
the first processor is further configured to detect whether the IO pin to be inspected is normal according to the level signal received by the IO pin to be inspected.
Preferably, the to-be-tested chip sub-module is realized based on FPGA configuration; the auxiliary verification sub-module is realized based on FPGA configuration.
Preferably, the first processor is specifically configured to determine that the IO pin to be tested is normal when the IO pin to be tested of the chip sub-module to be tested receives the first level signal; and when the IO pin to be tested of the chip sub-module to be tested does not receive the first level signal, determining that the IO pin to be tested is abnormal.
Preferably, the auxiliary verification sub-module is further configured to send a signal output feedback signal to the second processor when a first level signal is output through the corresponding auxiliary pin;
the second processor is further configured to receive the signal output feedback signal and transmit the signal output feedback signal to the first processor;
the first processor is further configured to acquire the signal output feedback signal, generate pin signal input completion information according to the signal output feedback signal, and send the pin signal input completion information to the to-be-tested chip sub-module;
the chip sub-module to be tested is further used for receiving the pin signal input completion information to acquire that the corresponding auxiliary pin of the auxiliary verification sub-module outputs a first level signal.
Preferably, the to-be-tested chip sub-module is further configured to send request information of a to-be-input signal corresponding to a next to-be-tested IO pin to the first processor when the pin signal input completion information is received and the to-be-tested IO pin receives the first level signal;
the first processor is specifically configured to determine that the IO pin to be inspected of the chip sub-module to be tested receives the first level signal when the request information of the signal to be input sent by the chip sub-module to be tested is received again within a preset time period.
Preferably, the second processor is specifically configured to determine whether an auxiliary pin outputting a first level signal exists in auxiliary pins of the auxiliary verification sub-module when request information of a signal input instruction is acquired; if the first level signal exists, a signal stopping instruction is sent to the auxiliary verification sub-module, so that the auxiliary verification sub-module changes an output signal of an auxiliary pin which outputs the first level signal into a second level signal; when no first level signal is output by the auxiliary pin of the auxiliary verification submodule, a signal input instruction is sent to the auxiliary verification submodule; the second level signal is a level signal which cannot trigger the chip module to be detected to detect whether the IO pin of the chip module to be detected is normal or not;
and the auxiliary verification submodule is also used for changing the output signal of each auxiliary pin into a second level signal when a signal suspension instruction is received.
Preferably, the method further comprises the following steps: a server device;
the first processor being connected to the second processor comprises:
the first processor is connected with the server equipment, and the second processor is connected with the server equipment;
the first processor is specifically configured to store request information of the signal input instruction into the server device;
the second processor is specifically configured to obtain request information of the signal input instruction from the server device.
Preferably, the first processor is connected with the chip sub-module to be tested through a Universal Asynchronous Receiver Transmitter (UART);
the second processor is connected with the auxiliary verification sub-module through the UART.
In a second aspect, an embodiment of the present application provides an automatic verification method for a chip IO pin, which is applied to the automatic verification system for a chip IO pin in any one of the first aspects, and the method includes:
the chip module to be tested runs the chip program to be tested, and determines an IO pin to be tested according to the chip program to be tested; sending a signal input instruction to an auxiliary verification module according to the IO pin to be verified;
the auxiliary verification module acquires a signal input instruction, controls a corresponding auxiliary pin to output a first level signal according to the signal input instruction, and transmits the first level signal to an IO pin to be verified of the chip module to be tested through the corresponding auxiliary pin;
and the chip module to be tested detects whether the IO pin to be tested is normal or not according to the level signal received by the IO pin to be tested.
Preferably, when the chip module to be tested includes a chip sub-module to be tested and a first processor, and the auxiliary verification module includes an auxiliary verification sub-module and a second processor, the chip module to be tested detects whether the IO pin to be tested is normal according to the level signal received by the IO pin to be tested:
when the IO pin to be tested of the chip sub-module to be tested receives the first level signal, the first processor determines that the IO pin to be tested is normal; and when the IO pin to be tested of the chip sub-module to be tested does not receive the first level signal, the first processor determines that the IO pin to be tested is abnormal.
Preferably, the method further comprises the following steps:
the auxiliary verification sub-module sends a signal output feedback signal to the second processor when outputting a first level signal through a corresponding auxiliary pin;
the second processor receives the signal output feedback signal and transmits the signal output feedback signal to the first processor;
the first processor acquires the signal output feedback signal, generates pin signal input completion information according to the signal output feedback signal, and sends the pin signal input completion information to the to-be-tested chip sub-module;
and the to-be-tested chip submodule receives the pin signal input completion information to acquire a first level signal output by a corresponding auxiliary pin of the auxiliary verification submodule.
Preferably, the controlling, by the auxiliary verification module, the corresponding auxiliary pin to output the first level signal according to the signal input instruction includes:
when the second processor acquires request information of a signal input instruction, determining whether an auxiliary pin for outputting a first level signal exists in auxiliary pins of the auxiliary verification submodule; if the first level signal exists, a signal stopping instruction is sent to the auxiliary verification sub-module, so that the auxiliary verification sub-module changes an output signal of an auxiliary pin which outputs the first level signal into a second level signal; when no first level signal is output by the auxiliary pin of the auxiliary verification submodule, a signal input instruction is sent to the auxiliary verification submodule;
the method further comprises the following steps:
and the auxiliary verification submodule changes the output signal of each auxiliary pin into a second level signal when receiving a signal suspension instruction.
By adopting the scheme provided by the embodiment of the application, the automatic verification system for the IO pins of the chip comprises a chip module to be tested and an auxiliary verification module, wherein the chip module to be tested is internally provided with a chip program to be tested, the auxiliary verification module is connected with the chip module to be tested, the chip module to be tested comprises a plurality of IO pins, the auxiliary verification module comprises a plurality of auxiliary pins, and each IO pin is correspondingly connected with one auxiliary pin. Therefore, the auxiliary pin of the auxiliary verification module is connected with each IO pin of the chip module to be tested, when the IO pins are detected, the corresponding auxiliary pin of the auxiliary verification module is controlled to output a first level signal to the IO pins to be tested, and then whether the IO pins to be tested are normal or not is detected according to the level signal received by the IO pins to be tested, so that automatic verification of the IO pins is completed. In the process, the full coverage of the IO pins of the chip can be ensured by carrying out automatic verification on each IO pin without manual participation, the complexity of automatic verification is reduced, the coverage rate of the IO pin verification of the chip in the prior art is solved, and the problem of complexity is solved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.
Fig. 1 is a schematic structural diagram of an automatic verification system for IO pins of a chip according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of another automatic verification system for IO pins of a chip according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of another automatic verification system for IO pins of a chip according to an embodiment of the present application;
fig. 4 is a schematic flowchart of an automatic verification method for an IO pin of a chip according to an embodiment of the present application;
fig. 5 is a schematic flowchart of another method for automatically verifying an IO pin of a chip according to an embodiment of the present application.
Detailed Description
For better understanding of the technical solutions of the present application, the following detailed descriptions of the embodiments of the present application are provided with reference to the accompanying drawings.
It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of associative relationship that describes an associated object, meaning that three types of relationships may exist, e.g., A and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
Before specifically describing the embodiments of the present application, terms applied or likely to be applied to the embodiments of the present application will be explained first.
An IO (input output) pin is an input output pin of the chip.
The level signal refers to a signal represented by a level value, which is divided into a high level value "1" and a low level value "0".
UART (Universal Asynchronous Receiver/Transmitter) is used to convert data to be transmitted between serial communication and parallel communication.
In the related art, chip IO pin verification is mainly implemented by two schemes. The scheme is that part of pins are manually and randomly extracted to directly configure a register, and verification content is very limited. And the second scheme is that partial configuration items are generated through a tool, and verification of all the IO pins of the chip is performed by means of a special auxiliary board. However, in the above scheme, the scheme is a pure manual test, and all chip IO pins cannot be covered. In the second scheme, a special auxiliary board is needed, the control logic of the auxiliary board is complex, the implementation flow is more, and errors are easy to cause abnormity.
In view of the above problems, an embodiment of the present application provides an automatic verification system for IO pins of a chip, where the automatic verification system for IO pins of a chip includes a chip module to be tested, which includes a chip program to be tested, and an auxiliary verification module connected to the chip module to be tested, where the chip module to be tested includes a plurality of IO pins, the auxiliary verification module includes a plurality of auxiliary pins, and each IO pin is correspondingly connected to one auxiliary pin. Therefore, the auxiliary pin of the auxiliary verification module is connected with each IO pin of the chip module to be tested, when the IO pins are detected, the corresponding auxiliary pin of the auxiliary verification module is controlled to output a first level signal to the IO pins to be tested, and then whether the IO pins to be tested are normal or not is detected according to the level signal received by the IO pins to be tested, so that automatic verification of the IO pins is completed. In the process, the full coverage of the IO pins of the chip can be ensured by carrying out automatic verification on each IO pin without manual participation, the complexity of automatic verification is reduced, the coverage rate of the IO pin verification of the chip in the prior art is solved, and the problem of complexity is solved. The details will be described below.
Referring to fig. 1, a schematic structural diagram of an automatic verification system for an IO pin of a chip according to an embodiment of the present application is provided. The system comprises: a chip module to be tested 10 with a built-in chip program to be tested and an auxiliary verification module 20 connected with the chip module to be tested 10. The chip module to be tested 10 includes a plurality of IO pins, the auxiliary verification module 20 includes a plurality of auxiliary pins, each IO pin is correspondingly connected to one auxiliary pin, and one IO pin is only correspondingly connected to one auxiliary pin.
The auxiliary verification module 20 is configured to obtain and control a corresponding auxiliary pin to output a first level signal according to the signal input instruction, and transmit the first level signal to an IO pin to be verified of the chip module to be tested 10 through the corresponding auxiliary pin.
The first level signal is a level signal required for the chip module to be tested 10 to detect whether the IO pin is normal.
The to-be-tested chip module 10 is configured to run a to-be-tested chip program to determine an IO pin to be tested, send a signal input instruction to the auxiliary verification module 20 according to the IO pin to be tested, and detect whether the IO pin to be tested is normal according to a level signal received by the IO pin to be tested.
Specifically, the automatic verification system for the IO pin of the chip includes a chip module to be tested 10 and an auxiliary verification module 20. The chip module 10 to be tested is internally provided with a chip program to be tested, so that the chip module 10 to be tested can operate the chip program to be tested to realize the function of the chip to be tested, and the chip to be tested can be verified by verifying the chip module 10 to be tested, so that the problem of the chip to be tested can be found in time, and the quality of the chip can be improved. Because this application is for the IO pin to the chip to inspect, consequently contain a plurality of IO pins in the chip module 10 that awaits measuring, supplementary verification module 20 is used for the supplementary IO pin of verifying the chip module 10 that awaits measuring normal. In order to inspect each IO pin of the chip module 10 to be tested, the auxiliary verification module 20 includes a plurality of auxiliary pins, each IO pin is correspondingly connected to a first auxiliary pin, and one IO pin is connected to only one auxiliary pin, and the auxiliary pins connected to different IO pins are different.
The chip module to be tested 10 is internally provided with a chip program to be tested, the chip program to be tested is operated in the process of automatically verifying the IO pin, and the IO pin to be tested can be determined by operating the chip program to be tested. And after the IO pin to be detected is determined, generating a signal input instruction according to the IO pin to be detected, wherein the signal input instruction is used for representing an input signal required by the IO pin to be detected. After the chip module to be tested 10 generates the signal input command, the signal input command is sent to the auxiliary verification module 20. After receiving the signal input instruction, the auxiliary verification module 20 analyzes the signal input instruction, so as to know which IO pin to be tested of the chip module 10 to be tested is, and further determine the corresponding auxiliary pin. And after the auxiliary pin corresponding to the IO pin to be detected is determined, controlling the auxiliary pin to output a first level signal. Since the auxiliary pin is connected to the IO pin to be inspected of the chip module 10 to be inspected, the auxiliary pin outputs the first level signal and then transmits the first level signal to the IO pin to be inspected of the chip module 10 to be inspected. The chip module to be tested 10 can obtain the level signal received by the IO pin to be tested, and then detect whether the IO pin to be tested is normal according to the received level signal. When detecting that the IO pin to be detected is normal, the chip module to be detected 10 runs the chip program to be detected to continue to determine the next IO pin to be detected, and repeatedly executes the above process until all the IO pins are detected, or until the abnormal IO pin is detected.
It should be noted that, a specific implementation manner of detecting whether the IO pin to be inspected is normal according to the received level signal by the chip module to be inspected 10 may be to detect whether the level signal received by the IO pin to be inspected is the first level signal, if so, the IO pin to be inspected may be considered to be normal, and if not, the IO pin to be inspected may be considered to be abnormal, and an abnormal report may be generated and fed back to the user. Of course, other methods in the prior art are also possible, and the present application does not limit this.
It should be noted that the first level signal may be a high level signal, and at this time, when the auxiliary verification module 20 outputs a high level signal at the auxiliary pin corresponding to the IO pin to be verified, other auxiliary pins need to output a low level signal. The first level signal may also be a low level signal, and at this time, when the auxiliary verification module 20 outputs a low level signal at the auxiliary pin corresponding to the IO pin to be verified, other auxiliary pins need to output a high level signal. The first level signal may be set to be a high level signal or a low level signal according to actual requirements, which is not limited in this application.
It should be noted that, the sequence of the IO pin inspection is recorded in the program of the inspection chip to be tested, and when the program is executed, the IO pins may be determined as the IO pins to be inspected in sequence according to the sequence of the IO pin inspection recorded in the program.
Therefore, the auxiliary pin of the auxiliary verification module is connected with each IO pin of the chip module to be tested, when the IO pins are detected, the corresponding auxiliary pin of the auxiliary verification module is controlled to output a first level signal to the IO pins to be tested, and then whether the IO pins to be tested are normal or not is detected according to the level signal received by the IO pins to be tested, so that automatic verification of the IO pins is completed. In the process, the full coverage of the IO pins of the chip can be ensured by carrying out automatic verification on each IO pin without manual participation, the complexity of automatic verification is reduced, the coverage rate of the IO pin verification of the chip in the prior art is solved, and the problem of complexity is solved.
Further, for convenience of implementation, as shown in fig. 2, the chip module to be tested 10 includes: the device comprises a to-be-tested chip submodule 101 which is internally provided with a to-be-tested chip program and comprises a plurality of IO pins and a first processor 102 connected with the to-be-tested chip submodule 101. The auxiliary authentication module 20 includes: an auxiliary verification sub-module 201 including a plurality of auxiliary pins, and a second processor 202 connected to the auxiliary verification sub-module 201.
At this time, the connection of the chip module to be tested 10 and the auxiliary verification module 20 includes:
the first processor 102 is connected with the second processor 202, and IO pins of the chip sub-module 101 to be tested are correspondingly connected with auxiliary pins of the auxiliary verification sub-module 201.
The to-be-tested chip submodule 101 is configured to run a to-be-tested chip program to determine an IO pin to be tested, and send request information of a pin input signal to the first processor 102 according to the IO pin to be tested.
The first processor 102 is configured to receive request information of the pin input signal, and send request information of the signal input instruction to the second processor 202 according to the request information of the pin input signal.
The request information of the signal input instruction is used for requesting an auxiliary pin corresponding to the auxiliary verification submodule to output information of a first level signal.
The second processor 202 is configured to obtain request information of the signal input instruction, and send the signal input instruction to the auxiliary verification sub-module 201 according to the request information of the signal input instruction.
And the auxiliary verification sub-module 201 is configured to receive and control the corresponding auxiliary pin to output a first level signal according to the signal input instruction, and transmit the first level signal to an IO pin to be tested of the chip sub-module 101 to be tested.
The chip sub-module 101 to be tested is further configured to receive, through the IO pin to be tested, the first level signal output by the auxiliary verification sub-module 201 through the auxiliary pin.
The first processor 102 is further configured to detect whether the IO pin to be inspected is normal according to the level signal received by the IO pin to be inspected.
Specifically, the chip module to be tested 10 includes: a chip sub-module 101 to be tested and a first processor 102. The chip submodule 101 to be tested is internally provided with a chip program to be tested, and the chip submodule 101 to be tested comprises IO pins. At this time, the chip sub-module 101 to be tested is used to implement the function of the chip to be tested. The first processor 102 is connected to the chip sub-module 101 to be tested, and is used for communicating with the chip sub-module 101 to be tested and the auxiliary verification module 20.
The to-be-tested chip submodule 101 runs a to-be-tested chip program in the to-be-tested chip submodule, and determines an IO pin to be tested. The request information of the pin input signal is generated according to the IO pin to be inspected, and the request information of the pin input signal is sent to the first processor 102. The first processor 102 receives the request information of the pin input signal, analyzes the request information, obtains the IO pin to be tested, and generates the request information of the signal input instruction for requesting to input the level signal of the IO pin to be tested according to the IO pin to be tested. The request information of this signal input instruction is sent to the second processor 202.
The auxiliary authentication module 20 includes: a secondary verification sub-module 201 and a second processor 202. The auxiliary verification sub-module 201 includes a plurality of auxiliary pins, and the auxiliary pins of the auxiliary verification sub-module 201 are connected to IO pins of the to-be-tested chip sub-module 101. The second processor 202 is connected to the first processor 102, and the auxiliary verification sub-module 201 is connected to the second processor 202.
The second processor 202 obtains the request information of the signal input instruction sent by the first processor 102, parses the signal input instruction, sends the signal input instruction to the auxiliary verification sub-module 201.
After the auxiliary verification sub-module 201 receives the signal input instruction, the IO pin to be verified is obtained by analyzing the signal input instruction, so that the auxiliary pin corresponding to the IO pin to be verified can be determined, the first level signal is output through the auxiliary pin corresponding to the IO pin to be verified, and the first level signal is transmitted to the IO pin to be verified of the chip sub-module 101 to be tested.
The chip submodule 101 to be tested receives the level signal through the IO pin to be tested, and feeds the received level signal back to the first processor 102, and the first processor 102 determines whether the IO pin to be tested is normal according to the level signal received by the chip submodule 101 to be tested.
Further, the first processor 102 is specifically configured to determine that an IO pin to be tested is normal when the IO pin to be tested of the chip sub-module 101 to be tested receives the first level signal. When the IO pin to be tested of the chip sub-module 101 to be tested does not receive the first level signal, it is determined that the IO pin to be tested is abnormal.
That is, the first processor 102 may detect whether the IO pin to be inspected receives the first level signal when the level signal received by the IO pin to be inspected is normal, and determine that the IO pin to be inspected is normal if it is determined that the IO pin to be inspected receives the first level signal and a related circuit of the IO pin to be inspected is normal. When the IO pin to be detected does not receive the first level signal, it is indicated that a related circuit of the IO pin to be detected cannot work normally, and the IO pin to be detected is determined to be abnormal, so that abnormal information can be generated and fed back to a user.
Further, the chip sub-module 101 to be tested is configured and implemented based on an FPGA (Field Programmable Gate Array). The auxiliary verification sub-module 201 is implemented based on FPGA configuration. Optionally, the to-be-tested chip sub-module 101 is an FPGA on Haps, and is used as a verification platform for detecting a to-be-tested chip.
Further, in order to prevent the chip sub-module 101 to be tested from being in a state of waiting for receiving the first level signal through the IO pin to be tested, after the auxiliary verification sub-module 201 outputs the first level signal through the corresponding auxiliary pin, a feedback signal that the first level signal has been output may be sent to the chip sub-module 101 to be tested, so that the chip sub-module 101 to be tested knows that the auxiliary verification sub-module 201 has output the first level signal through the corresponding auxiliary pin. The method comprises the following specific steps:
the auxiliary verification sub-module 201 is further configured to send a signal output feedback signal to the second processor 202 when the first level signal is output through the corresponding auxiliary pin.
The second processor 202 is further configured to receive the signal output feedback signal and transmit the signal output feedback signal to the first processor 102.
The first processor 102 is further configured to obtain a signal output feedback signal, generate pin signal input completion information according to the signal output feedback signal, and send the pin signal input completion information to the to-be-tested chip sub-module 101.
The chip sub-module 101 to be tested is further configured to receive the pin signal input completion information, so as to know that the corresponding auxiliary pin of the auxiliary verification sub-module 201 outputs the first level signal.
Specifically, when the auxiliary verification sub-module 201 outputs the first level signal through the corresponding auxiliary pin, it generates a signal output feedback signal representing that the corresponding auxiliary pin outputs the first level signal, and sends the signal output feedback signal to the second processor 202. After receiving the signal output feedback signal, the second processor 202 transmits the signal output feedback signal to the first processor 102. The first processor 102 obtains the signal output feedback signal transmitted by the second processor 202, analyzes the signal output feedback signal, generates pin signal input completion information according to an analysis result, and sends the pin signal input completion information to the to-be-tested chip sub-module 101. The chip sub-module 101 to be tested receives the pin signal input completion information, and after the pin signal input completion information is analyzed, it can be known that the corresponding auxiliary pin of the auxiliary verification sub-module 201 has output the first level signal. Therefore, when the IO pin to be tested of the chip sub-module 101 to be tested does not receive the first level signal and the chip sub-module 101 to be tested receives the pin signal input completion information, the IO pin to be tested may not receive the first level signal and may be fed back to the first processor 102, at this time, the first processor 102 may determine that the IO pin to be tested is abnormal, and the first processor 102 generates the abnormal information and feeds back the information to the user. When the IO pin to be inspected of the chip sub-module 101 to be inspected receives the first level signal and the chip sub-module 101 to be inspected receives the pin signal input completion information, the IO pin to be inspected may be sent to the first processor 102 to receive the first level signal, and then the first processor 102 may determine that the IO pin to be inspected is normal.
In this way, the auxiliary verification sub-module 201 sends a signal output feedback signal to inform the chip sub-module 101 to be tested that the corresponding auxiliary pin of the auxiliary verification sub-module 201 outputs the first level signal, so that the chip sub-module 101 to be tested can be prevented from waiting for a long time because the IO pin to be tested does not receive the first level signal.
It should be noted that the above-mentioned situation of preventing the to-be-tested chip sub-module 101 from waiting for the IO pin to be tested to receive the first level signal for a long time may also be implemented in other ways, for example, a time threshold may be set. The time threshold may be set according to actual requirements, which is not limited in this application. If the to-be-tested chip sub-module 101 does not receive the first level signal through the to-be-tested IO pin within the preset time threshold, the to-be-tested IO pin is fed back to the first processor 102, the first processor 102 can determine that the to-be-tested IO pin is abnormal, and the first processor 102 generates abnormal information to feed back the information to a user. Within the preset time threshold, when the IO pin to be tested of the chip sub-module 101 receives the first level signal, the IO pin to be tested may be sent to the first processor 102 to receive the first level signal, and then the first processor 102 may determine that the IO pin to be tested is normal. Of course, the method can also be realized in other ways, and the application is not limited to the method.
Optionally, the chip sub-module 101 to be tested is further configured to send request information of a signal to be input corresponding to the next IO pin to be tested to the first processor 102 when the pin signal input completion information is received and the IO pin to be tested receives the first level signal.
The first processor 102 is specifically configured to determine that the IO pin to be inspected of the chip sub-module 101 to be tested receives the first level signal when the request information of the signal to be input sent by the chip sub-module 101 to be tested is received again within the preset time period.
That is to say, in this embodiment, when the first processor 102 determines that the level signal received by the IO pin to be tested of the chip sub-module 101 to be tested is received, the chip sub-module 101 to be tested may send a message to the first processor 102 to inform whether the first level signal is received, and may inform in other ways. The details are as follows.
When the to-be-tested chip submodule 101 receives the pin signal input completion information and the IO pin to be tested receives the first level signal, it can be known that the IO pin to be tested is normal, and at this time, the to-be-tested chip submodule 101 can determine the request information of the to-be-tested signal corresponding to the next IO pin to be tested, and does not send the information whether the IO pin to be tested receives the first level signal to the first processor 102. At this time, when the first processor 102 receives the request information of the signal to be input again within the preset time period, it may be known that the last IO pin to be inspected has received the first level signal, and it may be determined that the last IO pin to be inspected is normal. And continuing whether the IO pin to be checked next is normal or not.
Therefore, information interaction between the chip sub-module 101 to be tested and the first processor 102 can be reduced, and the inspection efficiency is improved.
Further, after the auxiliary verification sub-module 201 outputs the first level signal through the corresponding auxiliary pin, the chip sub-module 101 to be tested receives the first level signal through the IO pin to be tested, and when the first processor 102 determines that the IO pin to be tested is normal, the chip sub-module 101 to be tested continues to detect whether the next IO pin is normal. At this time, request information of a signal to be input of the IO pin to be checked next is sent to the first processor 102. The first processor 102 sends request information of the signal input instruction to the second processor 202. At this time, when the second processor 202 acquires the request information of the signal input instruction, in order to prevent the auxiliary pin of the auxiliary verification sub-module 201 corresponding to the last IO pin to be verified from still outputting the first level signal, it may be determined whether there is an auxiliary pin of the auxiliary verification sub-module 201 outputting the first level signal.
At this time, the second processor 202 is specifically configured to determine whether an auxiliary pin outputting a first level signal exists in the auxiliary pins of the auxiliary verification sub-module 201 when acquiring request information of a signal input instruction; if the first level signal exists, a signal suspension instruction is sent to the auxiliary verification sub-module 201, so that the auxiliary verification sub-module 201 changes an output signal of an auxiliary pin outputting the first level signal into a second level signal; when no auxiliary pin of the auxiliary verification sub-module 201 outputs the first level signal, a signal input instruction is sent to the auxiliary verification sub-module 201.
The auxiliary verification sub-module 201 is further configured to change the output signal of each auxiliary pin to a second level signal when receiving the signal suspension command.
The second level signal is a level signal that does not trigger the chip module to be detected 10 to detect whether the IO pin thereof is normal.
That is, after acquiring the request information of the signal input command, the second processor 202 needs to confirm that the auxiliary pin of the auxiliary verification sub-module 201 does not output the first level signal. Therefore, the second processor 202 may send a message to the auxiliary verification sub-module 201 to know whether the auxiliary pin of the auxiliary verification sub-module 201 outputs the first level signal. If the second processor 202 learns that there are auxiliary pins outputting the first level signal in all the auxiliary pins in the auxiliary verification sub-module 201 through the message fed back by the auxiliary verification sub-module 201, the second processor 202 sends a signal suspension instruction to the auxiliary verification sub-module 201, and when the auxiliary verification sub-module 201 receives the signal suspension instruction, the auxiliary verification sub-module 201 changes the output signal of each auxiliary pin into the second level signal. If the second processor 202 learns that there is no auxiliary pin outputting the first level signal among all auxiliary pins in the auxiliary verification sub-module 201 through the message fed back by the auxiliary verification sub-module 201, the second processor 202 directly sends a signal input instruction to the auxiliary verification sub-module 201.
The second level signal is a signal that is preset and is different from the first level signal. For example, if the first level signal is a high level signal, the second level signal is a low level signal. While one auxiliary pin of the auxiliary verification sub-module 201 outputs a first level signal, the other auxiliary pin of the auxiliary verification sub-module 202 outputs a second level signal.
Further, in the above system for automatically verifying the IO pin of the chip, as shown in fig. 3, the system further includes: a server device 30.
At this time, the connection of the first processor 102 and the second processor 202 includes:
the first processor 102 is connected to the server device 30, and the second processor 202 is connected to the server device 30.
The first processor 102 is specifically configured to store request information of the signal input instruction in the server device 30.
The second processor 202 is specifically configured to obtain request information of the signal input instruction from the server device 30.
That is, the first processor 102 and the second processor 202 are connected via the server device 30 and communicate via the server device 30. At this time, the first processor 102 may directly store the information that it needs to send to the second processor 202 in the server device 30, and the second processor 202 directly obtains the information sent by the first processor 102 from the server device 30. Similarly, when the second processor 202 sends information to the first processor 102, the information to be sent may be directly stored in the server device 30, and the first processor 102 directly washes the server device 30 to obtain the information sent by the second processor 202. For example, the first processor 102 stores the request information of the signal input instruction into the server device 30, and the second processor 202 may directly acquire the request information of the signal input instruction from the server device 30. After the second processor 202 receives the signal output feedback signal sent by the auxiliary verification sub-module 201, the signal output feedback signal may be stored in the server apparatus 30. The first processor 102 may obtain this signal directly from the server device 30 to output a feedback signal.
Alternatively, the first processor 102 and the second processor 202 may be PCs (Personal computers).
Optionally, the first processor 102 is connected to the chip sub-module 101 to be tested through a UART (Universal Asynchronous Receiver/Transmitter). The second processor 202 is connected with the auxiliary verification sub-module 201 through UART. At this time, in the system configuration file, the pins connected to the UART in the chip sub-module 101 to be tested are set as other pins except the IO pin corresponding to the chip to be tested, so as to ensure that the automatic verification of the chip IO pin is not interrupted.
Therefore, the embodiment of the application provides an automatic verification system for the IO pins of a chip, which comprises a chip module to be tested and an auxiliary verification module, wherein the chip module to be tested comprises a plurality of IO pins, the auxiliary verification module comprises a plurality of auxiliary pins, and each IO pin is correspondingly connected with one auxiliary pin. Therefore, the auxiliary pin of the auxiliary verification module is connected with each IO pin of the chip module to be tested, when the IO pins are detected, the corresponding auxiliary pin of the auxiliary verification module is controlled to output a first level signal to the IO pins to be tested, and then whether the IO pins to be tested are normal or not is detected according to the level signal received by the IO pins to be tested, so that automatic verification of the IO pins is completed. In the process, the full coverage of the IO pins of the chip can be ensured by carrying out automatic verification on each IO pin without manual participation, the complexity of automatic verification is reduced, the coverage rate of the IO pin verification of the chip in the prior art is solved, and the problem of complexity is solved.
As shown in fig. 4, the present application provides a method for automatically verifying a chip IO pin, which is applied to the system for automatically verifying a chip IO pin in the foregoing embodiment, and the method includes:
step S401, the chip module to be tested runs the chip program to be tested, and the IO pin to be tested is determined according to the chip program to be tested; and sending a signal input instruction to the auxiliary verification module according to the IO pin to be verified.
Step S402, the auxiliary verification module obtains a signal input instruction, controls a corresponding auxiliary pin to output a first level signal according to the signal input instruction, and transmits the first level signal to an IO pin to be tested of the chip module to be tested through the corresponding auxiliary pin.
Step S403, the to-be-tested chip module detects whether the IO pin to be tested is normal according to the level signal received by the IO pin to be tested.
Further, when the chip module to be tested includes a chip sub-module to be tested and a first processor, and the auxiliary verification module includes an auxiliary verification sub-module and a second processor, the chip module to be tested in step S401 runs the chip program to be tested, and determines the IO pin to be tested according to the chip program to be tested; the step of sending a signal input instruction to the auxiliary verification module according to the IO pin to be verified comprises the following steps: and the sub-module of the chip to be tested operates the program of the chip to be tested, determines the IO pin to be tested according to the program of the chip to be tested, and sends request information of a pin input signal to the first processor according to the IO pin to be tested.
The first processor receives the request information of the pin input signal and sends the request information of the signal input instruction to the second processor according to the request information of the pin input signal. The request information of the signal input instruction is used for requesting an auxiliary pin corresponding to the auxiliary verification submodule to output information of a first level signal.
Step S402, the auxiliary verification module obtains a signal input instruction, controls a corresponding auxiliary pin to output a first level signal according to the signal input instruction, and transmits the first level signal to an IO pin to be tested of the chip module to be tested through the corresponding auxiliary pin, where the IO pin to be tested specifically includes: and the second processor acquires the request information of the signal input instruction and sends the signal input instruction to the auxiliary verification submodule according to the request information of the signal input instruction.
And the auxiliary verification sub-module receives and controls a corresponding auxiliary pin to output a first level signal according to the signal input instruction, and transmits the first level signal to an IO pin to be tested of the sub-module of the chip to be tested.
Step S403, the detecting, by the chip module to be tested, whether the IO pin to be tested is normal according to the level signal received by the IO pin to be tested specifically includes: and the to-be-tested chip submodule receives the first level signal output by the auxiliary verification submodule through the auxiliary pin through the to-be-tested IO pin.
And the first processor detects whether the IO pin to be detected is normal or not according to the level signal received by the IO pin to be detected.
Specifically, the step S403 of detecting, by the chip module to be tested, whether the IO pin to be tested is normal according to the level signal received by the IO pin to be tested specifically includes:
when the IO pin to be tested of the sub-module of the chip to be tested receives the first level signal, the first processor determines that the IO pin to be tested is normal; when the IO pin to be tested of the sub-module of the chip to be tested does not receive the first level signal, the first processor determines that the IO pin to be tested is abnormal.
Further, as shown in fig. 5, the method further includes:
step 501, when the auxiliary verification sub-module outputs the first level signal through the corresponding auxiliary pin, the auxiliary verification sub-module sends a signal output feedback signal to the second processor.
And S502, the second processor receives the signal output feedback signal and transmits the signal output feedback signal to the first processor.
Step S503, the first processor acquires the signal output feedback signal, generates pin signal input completion information according to the signal output feedback signal, and sends the pin signal input completion information to the to-be-tested chip submodule.
Step S504, the to-be-tested chip submodule receives the pin signal input completion information so as to acquire that the corresponding auxiliary pin of the auxiliary verification submodule outputs a first level signal.
Optionally, the step S402 of controlling, by the auxiliary verification module according to the signal input instruction, the corresponding auxiliary pin to output the first level signal specifically includes:
when the second processor acquires request information of a signal input instruction, determining whether an auxiliary pin for outputting a first level signal exists in auxiliary pins of the auxiliary verification submodule; if the first level signal exists, a signal stopping instruction is sent to the auxiliary verification sub-module, so that the auxiliary verification sub-module changes an output signal of an auxiliary pin which outputs the first level signal into a second level signal; when no first level signal is output by the auxiliary pin of the auxiliary verification submodule, a signal input instruction is sent to the auxiliary verification submodule;
the method further comprises the following steps:
and the auxiliary verification submodule changes the output signal of each auxiliary pin into a second level signal when receiving the signal suspension command.
Further, when the automatic verification system for the IO pin of the chip further includes a server device, the step of sending, by the first processor, request information of a signal input instruction to the second processor specifically includes: the first processor stores request information of the signal input instruction into the server apparatus.
The step of acquiring request information of the signal input instruction by the second processor specifically includes: the second processor acquires request information of the signal input instruction from the server apparatus.
The step of transmitting the signal output feedback signal to the first processor by the second processor specifically includes: the second processor transmits the signal output feedback signal to the server device.
The step of acquiring the signal output feedback signal by the first processor specifically includes: the first processor acquires a signal output feedback signal from the server device.
It should be noted that, for a specific implementation manner of the chip IO pin automatic verification method in this embodiment, reference may be made to the specific description of the chip IO pin automatic verification system in the foregoing embodiment, and details are not described here again.
Therefore, the chip module to be tested in the embodiment of the application comprises a plurality of IO pins, the auxiliary verification module comprises a plurality of auxiliary pins, and each IO pin is correspondingly connected with one auxiliary pin. Therefore, the auxiliary pin of the auxiliary verification module is connected with each IO pin of the chip module to be tested, when the IO pins are detected, the corresponding auxiliary pin of the auxiliary verification module is controlled to output a first level signal to the IO pins to be tested, and then whether the IO pins to be tested are normal or not is detected according to the level signal received by the IO pins to be tested, so that automatic verification of the IO pins is completed. In the process, the full coverage of the IO pins of the chip can be ensured by carrying out automatic verification on each IO pin without manual participation, the complexity of automatic verification is reduced, the coverage rate of the IO pin verification of the chip in the prior art is solved, and the problem of complexity is solved.
Those skilled in the art will readily appreciate that the techniques of the embodiments of the present invention may be implemented as software plus a required general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be essentially or partially implemented in the form of a software product, which may be stored in a storage medium, such as ROM/RAM, magnetic disk, optical disk, etc., and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method according to the embodiments or some parts of the embodiments.
The same and similar parts in the various embodiments in this specification may be referred to each other. Especially, as for the device embodiment and the terminal embodiment, since they are basically similar to the method embodiment, the description is relatively simple, and the relevant points can be referred to the description in the method embodiment.
Claims (13)
1. An automatic verification system for IO pins of a chip is characterized by comprising: a chip module to be tested with a built-in chip program to be tested and an auxiliary verification module connected with the chip module to be tested; wherein the content of the first and second substances,
the chip module to be tested comprises a plurality of IO pins, the auxiliary verification module comprises a plurality of auxiliary pins, each IO pin is correspondingly connected with one auxiliary pin, and one IO pin is only correspondingly connected with one auxiliary pin;
the auxiliary verification module is used for acquiring and controlling a corresponding auxiliary pin to output a first level signal according to a signal input instruction, and transmitting the first level signal to an IO pin to be detected of the chip module to be detected through the corresponding auxiliary pin; the first level signal is a level signal required for the chip module to be tested to detect whether an IO pin of the chip module to be tested is normal or not;
the chip module to be tested is used for operating the IO pin to be tested is determined by the chip program to be tested, the signal input instruction is sent to the auxiliary verification module according to the IO pin to be tested, and whether the IO pin to be tested is normal or not is detected according to the level signal received by the IO pin to be tested.
2. The system of claim 1,
the chip module to be tested includes: the system comprises a to-be-tested chip submodule and a first processor, wherein the to-be-tested chip submodule is internally provided with a chip program to be tested and comprises a plurality of IO pins; the secondary verification module includes: the system comprises an auxiliary verification sub-module and a second processor, wherein the auxiliary verification sub-module comprises a plurality of auxiliary pins, and the second processor is connected with the auxiliary verification sub-module;
the chip module to be tested and the auxiliary verification module are connected and comprise:
the first processor is connected with the second processor, and an IO pin of the to-be-tested chip sub-module is correspondingly connected with an auxiliary pin of the auxiliary verification sub-module;
the to-be-tested chip submodule is used for operating the to-be-tested chip program to determine an IO pin to be tested and sending request information of a pin input signal to the first processor according to the IO pin to be tested;
the first processor is used for receiving the request information of the pin input signal and sending the request information of a signal input instruction to the second processor according to the request information of the pin input signal; the request information of the signal input instruction is used for requesting an auxiliary pin corresponding to the auxiliary verification submodule to output information of a first level signal;
the second processor is used for acquiring request information of a signal input instruction and sending the signal input instruction to the auxiliary verification submodule according to the request information of the signal input instruction;
the auxiliary verification sub-module is used for receiving and controlling a corresponding auxiliary pin to output a first level signal according to the signal input instruction, and transmitting the first level signal to an IO pin to be tested of the to-be-tested chip sub-module;
the to-be-tested chip sub-module is further configured to receive the first level signal output by the auxiliary verification sub-module through an auxiliary pin through the to-be-tested IO pin;
the first processor is further configured to detect whether the IO pin to be inspected is normal according to the level signal received by the IO pin to be inspected.
3. The system of claim 2, wherein the chip sub-module under test is implemented based on FPGA configuration; the auxiliary verification sub-module is realized based on FPGA configuration.
4. The system of claim 2,
the first processor is specifically configured to determine that the IO pin to be inspected is normal when the IO pin to be inspected of the chip sub-module to be inspected receives the first level signal; and when the IO pin to be tested of the chip sub-module to be tested does not receive the first level signal, determining that the IO pin to be tested is abnormal.
5. The system of claim 4,
the auxiliary verification sub-module is further configured to send a signal output feedback signal to the second processor when a first level signal is output through the corresponding auxiliary pin;
the second processor is further configured to receive the signal output feedback signal and transmit the signal output feedback signal to the first processor;
the first processor is further configured to acquire the signal output feedback signal, generate pin signal input completion information according to the signal output feedback signal, and send the pin signal input completion information to the to-be-tested chip sub-module;
the chip sub-module to be tested is further used for receiving the pin signal input completion information to acquire that the corresponding auxiliary pin of the auxiliary verification sub-module outputs a first level signal.
6. The system of claim 5,
the to-be-tested chip submodule is further used for sending request information of a to-be-input signal corresponding to the next to-be-tested IO pin to the first processor when the pin signal input completion information is received and the to-be-tested IO pin receives the first level signal;
the first processor is specifically configured to determine that the IO pin to be inspected of the chip sub-module to be tested receives the first level signal when the request information of the signal to be input sent by the chip sub-module to be tested is received again within a preset time period.
7. The system according to any one of claims 2 to 6,
the second processor is specifically configured to determine whether an auxiliary pin outputting a first level signal exists in auxiliary pins of the auxiliary verification sub-module when request information of a signal input instruction is acquired; if the first level signal exists, a signal stopping instruction is sent to the auxiliary verification sub-module, so that the auxiliary verification sub-module changes an output signal of an auxiliary pin which outputs the first level signal into a second level signal; when no first level signal is output by the auxiliary pin of the auxiliary verification submodule, a signal input instruction is sent to the auxiliary verification submodule; the second level signal is a level signal which does not trigger the chip module to be detected to detect whether the IO pin of the chip module to be detected is normal or not;
and the auxiliary verification submodule is also used for changing the output signal of each auxiliary pin into a second level signal when a signal suspension instruction is received.
8. The system of claim 2, further comprising: a server device;
the first processor being connected to the second processor comprises:
the first processor is connected with the server equipment, and the second processor is connected with the server equipment;
the first processor is specifically configured to store request information of the signal input instruction into the server device;
the second processor is specifically configured to obtain request information of the signal input instruction from the server device.
9. The system of claim 2,
the first processor is connected with the to-be-tested chip submodule through a universal asynchronous receiver-transmitter (UART);
the second processor is connected with the auxiliary verification sub-module through the UART.
10. An automatic verification method for IO pins of a chip, which is applied to the system of any one of claims 1 to 9, the method comprising:
the chip module to be tested runs the chip program to be tested, and determines an IO pin to be tested according to the chip program to be tested; sending a signal input instruction to an auxiliary verification module according to the IO pin to be verified;
the auxiliary verification module acquires a signal input instruction, controls a corresponding auxiliary pin to output a first level signal according to the signal input instruction, and transmits the first level signal to an IO pin to be verified of the chip module to be tested through the corresponding auxiliary pin;
and the chip module to be tested detects whether the IO pin to be tested is normal or not according to the level signal received by the IO pin to be tested.
11. The method according to claim 10, wherein when the chip module under test includes a chip sub-module under test and a first processor, and the auxiliary verification module includes an auxiliary verification sub-module and a second processor, the chip module under test detecting whether the IO pin to be verified is normal according to the level signal received by the IO pin to be verified includes:
when the IO pin to be tested of the chip sub-module to be tested receives the first level signal, the first processor determines that the IO pin to be tested is normal; and when the IO pin to be tested of the chip sub-module to be tested does not receive the first level signal, the first processor determines that the IO pin to be tested is abnormal.
12. The method of claim 11, further comprising:
the auxiliary verification sub-module sends a signal output feedback signal to the second processor when outputting a first level signal through a corresponding auxiliary pin;
the second processor receives the signal output feedback signal and transmits the signal output feedback signal to the first processor;
the first processor acquires the signal output feedback signal, generates pin signal input completion information according to the signal output feedback signal, and sends the pin signal input completion information to the to-be-tested chip sub-module;
and the to-be-tested chip submodule receives the pin signal input completion information to acquire a first level signal output by a corresponding auxiliary pin of the auxiliary verification submodule.
13. The method of claim 11,
the auxiliary verification module controls the corresponding auxiliary pin to output a first level signal according to the signal input instruction, and the method comprises the following steps:
when the second processor acquires request information of a signal input instruction, determining whether an auxiliary pin for outputting a first level signal exists in auxiliary pins of the auxiliary verification submodule; if the first level signal exists, a signal stopping instruction is sent to the auxiliary verification sub-module, so that the auxiliary verification sub-module changes an output signal of an auxiliary pin which outputs the first level signal into a second level signal; when no first level signal is output by the auxiliary pin of the auxiliary verification submodule, a signal input instruction is sent to the auxiliary verification submodule;
the method further comprises the following steps:
and the auxiliary verification submodule changes the output signal of each auxiliary pin into a second level signal when receiving a signal suspension instruction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110535984.3A CN113255271B (en) | 2021-05-17 | 2021-05-17 | Automatic verification system and method for IO pin of chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110535984.3A CN113255271B (en) | 2021-05-17 | 2021-05-17 | Automatic verification system and method for IO pin of chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113255271A true CN113255271A (en) | 2021-08-13 |
| CN113255271B CN113255271B (en) | 2022-09-09 |
Family
ID=77182380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110535984.3A Active CN113255271B (en) | 2021-05-17 | 2021-05-17 | Automatic verification system and method for IO pin of chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113255271B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113945827A (en) * | 2021-10-13 | 2022-01-18 | 深圳康姆科技有限公司 | Abnormal chip identification method and device |
| CN113960443A (en) * | 2021-09-23 | 2022-01-21 | 瑞芯微电子股份有限公司 | IO static parameter testing method and system |
| CN114120619A (en) * | 2021-11-12 | 2022-03-01 | 天津朗泽科技有限公司 | Apparatus for detecting matching relation of radio remote control device and method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7853851B1 (en) * | 2006-11-06 | 2010-12-14 | Oracle America, Inc. | Method and apparatus for detecting degradation in an integrated circuit chip |
| CN105844056A (en) * | 2016-04-15 | 2016-08-10 | 万高(杭州)科技有限公司 | GPIO (general purpose input/output) verification system and method |
| CN106531654A (en) * | 2016-11-14 | 2017-03-22 | 福州瑞芯微电子股份有限公司 | Chip input pin test method and device |
| CN109032878A (en) * | 2018-09-13 | 2018-12-18 | 郑州云海信息技术有限公司 | A kind of GPIO test method and device |
| CN112270152A (en) * | 2020-10-29 | 2021-01-26 | 厦门紫光展锐科技有限公司 | Chip IO pin verification system and method |
-
2021
- 2021-05-17 CN CN202110535984.3A patent/CN113255271B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7853851B1 (en) * | 2006-11-06 | 2010-12-14 | Oracle America, Inc. | Method and apparatus for detecting degradation in an integrated circuit chip |
| CN105844056A (en) * | 2016-04-15 | 2016-08-10 | 万高(杭州)科技有限公司 | GPIO (general purpose input/output) verification system and method |
| CN106531654A (en) * | 2016-11-14 | 2017-03-22 | 福州瑞芯微电子股份有限公司 | Chip input pin test method and device |
| CN109032878A (en) * | 2018-09-13 | 2018-12-18 | 郑州云海信息技术有限公司 | A kind of GPIO test method and device |
| CN112270152A (en) * | 2020-10-29 | 2021-01-26 | 厦门紫光展锐科技有限公司 | Chip IO pin verification system and method |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113960443A (en) * | 2021-09-23 | 2022-01-21 | 瑞芯微电子股份有限公司 | IO static parameter testing method and system |
| CN113960443B (en) * | 2021-09-23 | 2024-06-07 | 瑞芯微电子股份有限公司 | IO static parameter testing method and system |
| CN113945827A (en) * | 2021-10-13 | 2022-01-18 | 深圳康姆科技有限公司 | Abnormal chip identification method and device |
| CN113945827B (en) * | 2021-10-13 | 2024-06-04 | 深圳康姆科技有限公司 | Method and device for identifying abnormal chip |
| CN114120619A (en) * | 2021-11-12 | 2022-03-01 | 天津朗泽科技有限公司 | Apparatus for detecting matching relation of radio remote control device and method thereof |
| CN114120619B (en) * | 2021-11-12 | 2023-10-10 | 天津朗泽科技有限公司 | Device and method for detecting matching relation of radio remote control device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113255271B (en) | 2022-09-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113255271B (en) | Automatic verification system and method for IO pin of chip | |
| KR100629412B1 (en) | Device test apparatus and test method | |
| US7971110B2 (en) | System and method for testing a serial attached small computer system interface | |
| CN108983077B (en) | Circuit board test system and test method based on JTAG link | |
| WO2018201763A1 (en) | Test method for connector, device and storage medium | |
| US10613963B2 (en) | Intelligent packet analyzer circuits, systems, and methods | |
| JP2006085708A (en) | Control device and control method for console | |
| CN116627861B (en) | Data processing method and system based on expander, electronic equipment and storage medium | |
| CN110968004B (en) | Cable test system based on FPGA prototype verification development board | |
| CN109508271B (en) | Device and method for detecting dynamic single event upset of clock resource of FPGA | |
| US7849375B2 (en) | Semiconductor test system | |
| US20080068036A1 (en) | Semiconductor test system capable of virtual test and semiconductor test method thereof | |
| CN112003759B (en) | Automatic test method and device for hardware TCP/IP network accelerator | |
| CN112564825B (en) | Method, device, equipment and system for detecting Bluetooth equipment function | |
| US20140055160A1 (en) | Apparatus and method for inspection of marking | |
| CN113359014A (en) | Fool-proof method and system for chip test | |
| CN115616372A (en) | Fault injection test method and system | |
| CN115980541A (en) | Data processing method, data processing device, data testing device, data processing equipment and data testing equipment, and storage medium | |
| KR101563123B1 (en) | Method for testing device under test | |
| CN116381452B (en) | Chip testing method, device and system and readable storage medium | |
| KR101544967B1 (en) | Method for testing device under test | |
| JP2014202699A (en) | Cable inspection system, cable inspection device, information processing device, cable inspection method, and cable inspection program | |
| CN110249316A (en) | Debugger and chip adjustment method | |
| KR101131961B1 (en) | Virtual Test System and method for Verification of Handler | |
| CN115470124A (en) | Test scene detection method and device, electronic equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |