CN113224160A - 半导体元件及其制作方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 25
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 18
- 229910021332 silicide Inorganic materials 0.000 claims description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 13
- 238000005040 ion trap Methods 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 64
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 229910008812 WSi Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66409—Unipolar field-effect transistors
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Abstract
本发明公开一种半导体元件及其制作方法,其中该半导体元件包含:一基底,包含一主动区域和至少一虚设区域;一第一绝缘区域,隔绝所述主动区域;一第二绝缘区域,隔绝所述至少一虚设区域;一晶体管,设于所述主动区域上,其中所述晶体管包含一栅极,穿越所述主动区域、一源极区域,设于所述栅极的第一侧的所述主动区域内、和一漏极区域,设于栅极的第二侧的所述主动区域内;一源极应力层,设于所述源极区域内;一漏极应力层,设于所述漏极区域内;以及一虚设应力层,设于所述至少一虚设区域内。
Description
技术领域
本发明涉及半导体技术领域,特别是涉及一种改良的半导体元件及其制作方法。
背景技术
为了进一步增强MOS元件的性能,可以在MOS晶体管的通道区域引入应力以改善载流子迁移率。通常,期望在源极-漏极方向上的N型金属氧化物半导体(“NMOS”)元件的通道区域中引起伸张应力(tensile stress),并在源极-漏极方向上的P型金属氧化物半导体(“PMOS”)元件的通道区域中引起压缩应力(compressive stress)。
向PMOS元件的通道区域施加压缩应力的常用方法是在源极和漏极区域中生长SiGe应力源。这种方法通常包括以下步骤:在半导体基底上形成栅极叠层;在栅极叠层的侧壁上形成间隔物;沿着栅极间隔物在硅基底中形成凹槽;在凹槽中外延生长SiGe应力源;以及退火。由于SiGe的晶格常数大于硅,因此它在退火后会膨胀并向位于源极SiGe应力源和漏极SiGe应力源之间的通道区域施加压缩应力。
然而,上述方法具有由于图案密度不同而产生的图案加载效果的缺点。图案加载效应涉及在较高密度的区域和较低密度的区域中同时外延生长时发生的现象。由于膜从一个位置到另一位置的生长速率的差异,生长量根据局部图案密度而变得局部致密或稀疏,这导致所得膜的厚度不均匀。
发明内容
本发明的主要目的在于提供一种改良的半导体元件及其制作方法,以解决上述现有技术的不足与缺点。
本发明一方面提供一种半导体元件,包含:一基底,包含一主动区域和至少一虚设区域;一第一绝缘区域,隔绝所述主动区域;一第二绝缘区域,隔绝所述至少一虚设区域;一晶体管,设于所述主动区域上,其中所述晶体管包含一栅极,穿越所述主动区域、一源极区域,设于所述栅极的第一侧的所述主动区域内、和一漏极区域,设于所述栅极的第二侧的所述主动区域内;一源极应力层,设于所述源极区域内;一漏极应力层,设于所述漏极区域内;以及一虚设应力层,设于所述至少一虚设区域内。
依据本发明实施例,其中所述至少一虚设区域包含硅。
依据本发明实施例,其中所述至少一虚设区域包含一凹陷沟槽。
依据本发明实施例,其中所述虚设应力层设于所述凹陷沟槽内。
依据本发明实施例,其中所述源极区域包含一源极沟槽,又其中所述源极应力层设于所述源极沟槽内。
依据本发明实施例,其中所述漏极区域包含一漏极沟槽,又其中所述漏极应力层设于所述漏极沟槽内。
依据本发明实施例,其中所述源极沟槽、所述漏极沟槽和所述凹陷沟槽具有相同沟槽深度。
依据本发明实施例,其中所述源极应力层、所述漏极应力层和所述虚设应力层是由相同的外延材料所构成。
依据本发明实施例,其中所述外延材料包含SiGe、SiC或SiP。
依据本发明实施例,其中所述外延材料为P型掺杂SiGe。
依据本发明实施例,其中在所述至少一虚设区域的正上方未形成栅极。
本发明另一方面提供一种形成半导体元件的方法,包含:提供一基底,具有一第一导电型,其中所述基底具有一主表面,且所述基底包含一主动区域和至少一虚设区域;形成一第一绝缘区域,隔绝所述主动区域;形成一第二绝缘区域,隔绝所述至少一虚设区域;在所述主动区域形成一离子阱,具有一第二导电型;在所述主动区域上形成一栅极介电层;于所述栅极介电层上形成一栅极;在所述主动区域内的一源极区域内形成一源极沟槽、在所述主动区域内的一漏极区域内形成一漏极沟槽,并且于所述至少一虚设区域内形成凹陷沟槽;以及分别于源极沟槽内、所述漏极沟槽内和所述凹陷沟槽内形成一源极应力层、一漏极应力层和一虚设应力层。
依据本发明实施例,其中所述源极应力层、所述漏极应力层和所述虚设应力层具有所述第一导电型。
依据本发明实施例,其中所述第一导电型是P型,所述第二导电型是N型。
依据本发明实施例,其中所述源极应力层、所述漏极应力层和所述虚设应力层是由相同的外延材料所构成。
依据本发明实施例,其中所述外延材料包含SiGe、SiC或SiP。
依据本发明实施例,其中所述外延材料为P型掺杂SiGe。
依据本发明实施例,其中所述源极沟槽、所述漏极沟槽和所述凹陷沟槽具有相同沟槽深度。
依据本发明实施例,其中在所述至少一虚设区域的正上方未形成栅极。
依据本发明实施例,其中另包含:在所述源极应力层上形成一源极硅化金属层,并且于所述漏极应力层上形成一漏极硅化金属层。
附图说明
图1至图6为本发明一实施例所绘示的一种形成半导体元件的方法的剖面示意图。
主要元件符号说明
1基底
1a主表面
4第一绝缘区域
5第二绝缘区域
10离子阱
100主动(有源)区域
104栅极介电层
106栅极
110轻掺杂漏极区域
116间隙壁
118D漏极沟槽
118S源极沟槽
120D漏极应力层
120S源极应力层
122D重掺杂漏极区域
122S重掺杂源极区域
130D漏极硅化金属层
130G栅极硅化金属层
130S源极硅化金属层
200虚设区域
218凹陷沟槽
220虚设应力层
310蚀刻停止层
320层间介电层
d沟槽深度
D漏极区域
S源极区域
L半导体元件
T晶体管
具体实施方式
在下文中,将参照附图说明细节,该些附图中的内容也构成说明书细节描述的一部分,并且以可实行该实施例的特例描述方式来绘示。下文实施例已描述足够的细节使该领域的一般技术人士得以具以实施。
当然,也可采行其他的实施例,或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此,下文的细节描述不应被视为是限制,反之,其中所包含的实施例将由随附的权利要求来加以界定。
请参阅图1至图6,其为依据本发明一实施例所绘示的一种形成半导体元件的方法的剖面示意图。如图1所示,首先提供一基底1,具有一第一导电型,例如,P型。基底1具有一主表面1a,且基底1包含一主动区域100和至少一虚设区域200。后续,在主动区域100上会形成电路元件,例如,金属氧化物半导体(MOS)晶体管,但是在虚设区域200上则不会形成主动电路元件。依据本发明实施例,所述虚设区域200可以是设置在逻辑核心电路区域的外围,但不限于此。
在图中虽然仅绘示出一个虚设区域200,但是熟悉该项技术者应理解,基底1可以包含多个虚设区域200,例如,彼此互相平行的长条状硅区域或者多个块状硅区域,但不限于此。
在基底1的主表面1a内形成有第一绝缘区域4,隔绝主动区域100,且在基底1的主表面1a内形成有第二绝缘区域5,隔绝虚设区域200。依据本发明实施例,第一绝缘区域4和第二绝缘区域5可以是浅沟绝缘(STI)区域,但不限于此。依据本发明实施例,第一绝缘区域4和第二绝缘区域5内可以包含绝缘沟槽填充层,例如,氧化硅或氮化硅等。
接着,在主动区域100内形成一离子阱10。依据本发明实施例,离子阱10可以具有一第二导电型,例如,N型。依据本发明实施例,在虚设区域200内可以不形成离子阱。然后,在主动区域100上形成一栅极介电层104,再于栅极介电层104上形成一栅极106。依据本发明实施例,在虚设区域200的正上方未形成任何的栅极。
如图2所示,接着可以利用离子注入制作工艺在栅极106两侧的主动区域100内形成轻掺杂漏极(LDD)区域110。同样的,依据本发明实施例,在虚设区域200内可以不形成轻掺杂漏极区域。接着,可以在栅极106的侧壁上形成间隙壁116,例如,氮化硅间隙壁。
如图3所示,接着在主动区域100内的一源极区域S内形成一源极沟槽118S、在主动区域100内的一漏极区域D内形成一漏极沟槽118D,并且于虚设区域200内形成凹陷沟槽218。依据本发明实施例,源极沟槽118S、漏极沟槽118D和凹陷沟槽218具有相同的沟槽深度d。形成源极沟槽118S、漏极沟槽118D和凹陷沟槽218的方法是周知技术,例如,可以用湿蚀刻或干蚀刻等方式形成。
如图4所示,接着进行一外延制作工艺,分别于源极沟槽118S内、漏极沟槽118D内和凹陷沟槽218内形成一源极应力层120S、一漏极应力层120D和一虚设应力层220。依据本发明实施例,源极应力层120S、漏极应力层120D和虚设应力层220可以具有第一导电型,例如,P型。
依据本发明实施例,源极应力层120S、漏极应力层120D和虚设应力层220是由相同的外延材料所构成。依据本发明实施例,所述外延材料包含SiGe、SiC或SiP。例如,针对PMOS晶体管,所述外延材料可以是P型掺杂SiGe。
如图5所示,完成前述外延制作工艺之后,可以继续进行一离子注入制作工艺,在栅极106两侧的主动区域100内形成重掺杂源极区域122S和重掺杂漏极区域122D。依据本发明实施例,在虚设区域200内可以不形成重掺杂区域。
如图6所示,接着于源极应力层120S上形成一源极硅化金属层130S,并且于漏极应力层120D上形成一漏极硅化金属层130D。此外
可以在栅极106上形成栅极硅化金属层130G。例如,栅极硅化金属层130G、源极硅化金属层130S和漏极硅化金属层130D可以包含NiSi或CoSi、WSi或TiSi等,但不限于此。最后,可以在基底1上形成一蚀刻停止层(CESL)310,再于蚀刻停止层310上沉积一层间介电(ILD)层320。
本发明通过增加虚设区域200,在外延制作工艺过程中可以提高SiGe开口率,增加SiGe等外延成长面积,如此可以更佳的控制源极沟槽118S内和漏极沟槽118D内的外延时间,降低外延制作工艺的不稳定性和厚度偏差,达到减少MOS晶体管电性偏移的好处。
结构上,如图6所示,半导体元件L包含:基底1,包含主动区域100和至少一虚设区域200;第一绝缘区域4,隔绝主动区域100;第二绝缘区域5,隔绝虚设区域200;一晶体管T,设于主动区域100上,其中晶体管T包含栅极106,穿越主动区域100、源极区域S,设于栅极106的第一侧的主动区域100内、和漏极区域D,设于栅极106的第二侧的主动区域100内;源极应力层120S,设于源极区域S内;漏极应力层120D,设于漏极区域D内;以及虚设应力层220,设于虚设区域200内。
依据本发明实施例,其中虚设区域200包含硅。依据本发明实施例,其中虚设区域200包含凹陷沟槽218。依据本发明实施例,其中虚设应力层220设于凹陷沟槽218内。
依据本发明实施例,其中源极区域S包含源极沟槽118S,又其中源极应力层120S设于源极沟槽118S内。依据本发明实施例,其中漏极区域D包含漏极沟槽118D,又其中漏极应力层120D设于漏极沟槽118D内。
依据本发明实施例,其中源极沟槽118S、漏极沟槽118D和凹陷沟槽218具有相同沟槽深度。
依据本发明实施例,其中源极应力层120S、漏极应力层120D和虚设应力层220是由相同的外延材料所构成。依据本发明实施例,其中所述外延材料包含SiGe、SiC或SiP。依据本发明实施例,其中所述外延材料为P型掺杂SiGe。
依据本发明实施例,其中在虚设区域200的正上方未形成任何的栅极。
以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。
Claims (20)
1.一种半导体元件,其特征在于,包含:
基底,包含主动区域和至少一虚设区域;
第一绝缘区域,隔绝所述主动区域;
第二绝缘区域,隔绝所述至少一虚设区域;
晶体管,设于所述主动区域上,其中所述晶体管包含栅极,穿越所述主动区域、源极区域,设于所述栅极的第一侧的所述主动区域内、和漏极区域,设于所述栅极的第二侧的所述主动区域内;
源极应力层,设于所述源极区域内;
漏极应力层,设于所述漏极区域内;以及
虚设应力层,设于所述至少一虚设区域内。
2.如权利要求1所述的半导体元件,其中所述至少一虚设区域包含硅。
3.如权利要求1所述的半导体元件,其中所述至少一虚设区域包含凹陷沟槽。
4.如权利要求3所述的半导体元件,其中所述虚设应力层设于所述凹陷沟槽内。
5.如权利要求4所述的半导体元件,其中所述源极区域包含源极沟槽,又其中所述源极应力层设于所述源极沟槽内。
6.如权利要求5所述的半导体元件,其中所述漏极区域包含漏极沟槽,又其中所述漏极应力层设于所述漏极沟槽内。
7.如权利要求6所述的半导体元件,其中所述源极沟槽、所述漏极沟槽和所述凹陷沟槽具有相同沟槽深度。
8.如权利要求1所述的半导体元件,其中所述源极应力层、所述漏极应力层和所述虚设应力层是由相同的外延材料所构成。
9.如权利要求8所述的半导体元件,其中所述外延材料包含SiGe、SiC或SiP。
10.如权利要求8所述的半导体元件,其中所述外延材料为P型掺杂SiGe。
11.如权利要求1所述的半导体元件,其中在所述至少一虚设区域的正上方未形成栅极。
12.一种形成半导体元件的方法,包含:
提供基底,具有第一导电型,其中所述基底具有主表面,且所述基底包含主动区域和至少一虚设区域;
形成第一绝缘区域,隔绝所述主动区域;
形成第二绝缘区域,隔绝所述至少一虚设区域;
于所述主动区域形成离子阱,具有第二导电型;
在所述主动区域上形成栅极介电层;
在所述栅极介电层上形成栅极;
在所述主动区域内的源极区域内形成源极沟槽、在所述主动区域内的漏极区域内形成漏极沟槽,并且于所述至少一虚设区域内形成凹陷沟槽;以及
分别于源极沟槽内、所述漏极沟槽内和所述凹陷沟槽内形成源极应力层、漏极应力层和虚设应力层。
13.如权利要求12所述的方法,其中所述源极应力层、所述漏极应力层和所述虚设应力层具有所述第一导电型。
14.如权利要求12所述的方法,其中所述第一导电型是P型,所述第二导电型是N型。
15.如权利要求12所述的方法,其中所述源极应力层、所述漏极应力层和所述虚设应力层是由相同的外延材料所构成。
16.如权利要求15所述的方法,其中所述外延材料包含SiGe、SiC或SiP。
17.如权利要求15所述的方法,其中所述外延材料为P型掺杂SiGe。
18.如权利要求12所述的方法,其中所述源极沟槽、所述漏极沟槽和所述凹陷沟槽具有相同沟槽深度。
19.如权利要求12所述的方法,其中在所述至少一虚设区域的正上方未形成栅极。
20.如权利要求12所述的方法,其中另包含:
在所述源极应力层上形成源极硅化金属层,并且在所述漏极应力层上形成漏极硅化金属层。
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