CN113224014A - Semiconductor package structure and manufacturing method thereof - Google Patents

Semiconductor package structure and manufacturing method thereof Download PDF

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Publication number
CN113224014A
CN113224014A CN202010348023.7A CN202010348023A CN113224014A CN 113224014 A CN113224014 A CN 113224014A CN 202010348023 A CN202010348023 A CN 202010348023A CN 113224014 A CN113224014 A CN 113224014A
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China
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heat dissipation
substrate
chip
semiconductor package
package structure
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CN202010348023.7A
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Chinese (zh)
Inventor
潘玉堂
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Chipmos Technologies Inc
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Chipmos Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention provides a semiconductor packaging structure, which comprises a substrate, a chip, a packaging colloid, a heat dissipation assembly and a plurality of conductive terminals. The substrate has a first surface and a second surface opposite to the first surface. The chip is located on the first surface and electrically connected with the substrate. The encapsulation colloid encapsulates the chip. The heat dissipation assembly is located on the second surface and a part of the heat dissipation assembly is embedded in the substrate. The orthographic projection of the chip on the substrate is overlapped with the heat dissipation component. The plurality of conductive terminals are located on the second surface and electrically connected with the substrate. The plurality of conductive terminals surround the heat dissipation assembly. A method for manufacturing the semiconductor package structure is also provided.

Description

Semiconductor package structure and manufacturing method thereof
Technical Field
The present invention relates to a package structure and a method for manufacturing the same, and more particularly, to a semiconductor package structure and a method for manufacturing the same.
Background
In order to ensure continuous miniaturization and versatility of electronic products, semiconductor packages having versatility are expected. In addition, in order to meet the demand for the multifunctional semiconductor package, the number of Input/output (I/O) connection terminals needs to be further increased. However, increasing the number of i/o connection terminals increases the heat generated during operation of the chip in the semiconductor package, which may cause performance degradation or even failure due to overheating of the chip. Therefore, it is a challenge for those skilled in the art to reduce the problem of performance degradation or even failure of the chip in the semiconductor package due to overheating.
Disclosure of Invention
The invention aims at a semiconductor packaging structure and a manufacturing method thereof, which can effectively improve the heat dissipation efficiency of the semiconductor packaging structure and further reduce the problem of efficiency attenuation and even failure caused by overheating of a chip in the semiconductor packaging structure.
The invention provides a semiconductor packaging structure, which comprises a substrate, a chip, a packaging colloid, a heat dissipation assembly and a plurality of conductive terminals. The substrate has a first surface and a second surface opposite to the first surface. The chip is located on the first surface and electrically connected with the substrate. The encapsulation colloid encapsulates the chip. The heat dissipation assembly is located on the second surface and a part of the heat dissipation assembly is embedded in the substrate. The orthographic projection of the chip on the substrate is overlapped with the heat dissipation component. The plurality of conductive terminals are located on the second surface and electrically connected with the substrate. The plurality of conductive terminals surround the heat dissipation assembly.
The invention provides a manufacturing method of a semiconductor packaging structure, which comprises the step of providing a substrate, wherein the substrate is provided with a first surface and a second surface opposite to the first surface. The chip is disposed on the first surface and electrically connected to the substrate. And forming an encapsulation colloid to encapsulate the chip. And forming a heat dissipation assembly on the second surface, wherein part of the heat dissipation assembly is embedded in the substrate. The orthographic projection of the chip on the substrate is overlapped on the heat dissipation component. And forming a plurality of conductive terminals on the second surface and electrically connected with the substrate. The plurality of conductive terminals surround the heat dissipation assembly.
Based on the above, the heat dissipation assembly embedded in the substrate of the present invention can form an effective heat dissipation path for the chip, so that the heat generated during the operation of the chip can be transferred from the first surface to the second surface of the substrate to be dissipated via the heat dissipation assembly, thereby effectively improving the heat dissipation efficiency of the semiconductor package structure, and further reducing the problem of performance attenuation and even failure of the chip in the semiconductor package structure due to overheating.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.
Fig. 1A to 1I are schematic partial cross-sectional views illustrating a part of a method for manufacturing a semiconductor package structure according to an embodiment of the invention;
FIG. 2 is a schematic cross-sectional view of a portion of a semiconductor package according to another embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of a portion of a semiconductor package according to yet another embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view of a portion of a semiconductor package according to yet another embodiment of the present invention;
fig. 5 is a partial cross-sectional view of a semiconductor package structure according to yet another embodiment of the invention.
Description of the reference numerals
10, a multilayer board;
12. 112, a core layer;
12a, an upper surface;
12b, the lower surface;
14. 1141, a first conductive layer;
16. 1161a second conductive layer;
20, heat dissipation glue;
100. 200, 300, 400, 500, a semiconductor package structure;
114, a first patterned circuit layer;
116 a second patterned circuit layer;
1141a, 1161a: outer surface;
120, a heat dissipation block;
120a, a top surface;
120b, a bottom surface;
130a substrate;
130a first surface;
130b a second surface;
142, a first patterned solder mask layer;
144, a second patterned solder mask layer;
1421, a first solder mask layer;
1441: a second solder mask layer;
150, a chip;
160, packaging colloid;
170. 370, 470 heat dissipation components;
172. 372, 472 heat radiation module;
180, a conductive terminal;
390 a circuit board;
592, a thermal grease;
l is a lead;
OP1, OP2, OP3, OP4 and OP 5.
Detailed Description
Directional phrases used herein (e.g., upper, lower, right, left, front, rear, top, bottom) are used only as referring to the drawings and are not intended to imply absolute orientation.
Unless expressly stated otherwise, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a specific order.
The present invention will now be described more fully hereinafter with reference to the accompanying drawings of the present embodiments. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The same or similar reference numerals denote the same or similar components, and the following paragraphs will not be repeated.
Fig. 1A to 1I are schematic partial cross-sectional views illustrating a part of a method for manufacturing a semiconductor package structure according to an embodiment of the invention. Referring to fig. 1A, first, a multi-layer board 10 is provided, wherein the multi-layer board 10 may be composed of a core layer 12 and a conductive layer formed on the core layer 12. For example, the conductive layer may include a first conductive layer 14 formed on the upper surface 12a of the core layer 12 and a second conductive layer 16 formed on the lower surface 12b of the core layer 12. In other words, as shown in fig. 1A, the multilayer board 110 may be a three-layer structure formed by sequentially stacking the second conductive layer 16, the core layer 12 and the first conductive layer 14, but the invention is not limited thereto, and the number of layers and the arrangement of the layers of the multilayer board may depend on actual requirements.
In some embodiments, the material of the first and second conductive layers 14 and 16 may be a conductive metal or alloy. For example, the material of the first conductive layer 14 and the second conductive layer 16 is copper, aluminum or an alloy thereof, but the invention is not limited thereto, and the material of the first conductive layer 14 and the second conductive layer 16 may be other suitable conductive materials.
Referring to fig. 1A and 1B, a portion of the core layer 12 and a portion of the conductive layer are removed to form an opening OP1 penetrating the multilayer board 10, wherein removing a portion of the conductive layer may be removing a portion of the first conductive layer 14 and a portion of the second conductive layer 16. In other words, the remaining core layer 112, the remaining first conductive layer 1141, and the remaining second conductive layer 1161 may have portions on both sides of the opening OP1, respectively.
Referring to fig. 1C, the opening OP1 is filled with a heat conductive material to form the heat slug 120, wherein the heat slug 120 may form a heat dissipation path. For example, the thermally conductive material may fill the opening OP1, such that the top surface 120a of the heat slug 120 may be substantially coplanar with the outer surface 1141a of the remaining first conductive layer 1141, and the bottom surface 120b of the heat slug 120 may be substantially coplanar with the outer surface 1161a of the remaining second conductive layer 1161. In some embodiments, the thermally conductive material may be a metal or alloy thereof that conducts heat more efficiently. For example, the thermally conductive material is copper, for example. The method of filling the heat conductive material is, for example, electroplating.
Referring to fig. 1C and fig. 1D, a patterning process is performed on the remaining conductive layer to form a patterned circuit layer, wherein the remaining core layer 112 and the patterned circuit layer form a substrate 130. For example, the remaining first conductive layer 1141 and the remaining second conductive layer 1161 are patterned to form the first patterned circuit layer 114 and the second patterned circuit layer 116, respectively. In the present embodiment, the substrate 130 has a first surface 130a and a second surface 130b opposite to the first surface 130a, wherein the first surface 130a may be an exposed surface of the first patterned circuit layer 114, the second surface 130b may be an exposed surface of the second patterned circuit layer 116, and the heat slug 120 is embedded in the substrate 130. The heat slug 120 may penetrate through the substrate 130 to be exposed at the first surface 130 a. The patterning process is, for example, a photolithographic etching process.
On the other hand, the patterned circuit layer may have a plurality of openings to expose a portion of the core layer 112. For example, the first patterned circuit layer 114 may have a plurality of openings OP2, and the second patterned circuit layer 116 may have a plurality of openings OP3, respectively exposing portions of the core layer 112.
It should be noted that the substrate 130 of the present invention is not limited to the substrate 130 manufactured by the method for manufacturing the multi-layer board 10, and the substrate 130 is within the protection scope of the present invention as long as the first surface 130a and the second surface 130b of the substrate 130 have suitable conductive traces and the heat dissipation bumps 120 can be embedded in the substrate 130. The present invention is not limited to the method for forming the opening, and the opening may be formed by an appropriate method. For example, the opening may be formed by an etching process.
Referring to fig. 1E, to avoid the conductive traces on the first surface 130a and the second surface 130b of the substrate 130 from short-circuiting and oxidizing, a solder mask layer may be formed on the substrate 130 to cover the patterned trace layer and a portion of the solder mask layer may be located in the opening. For example, a first solder mask layer 1421 may be formed on the first surface 130a of the substrate 130 to cover the first patterned circuit layer 114 and a portion of the first solder mask layer 1421 is located in the opening OP2, and a second solder mask layer 1441 may be formed on the second surface 130b of the substrate 130 to cover a portion of the second solder mask layer 1441 of the second patterned circuit layer 116 is located in the opening OP 3. The material of the solder mask is, for example, green paint, but the invention is not limited thereto. The solder mask layer may be formed by a suitable method.
Referring to fig. 1E and fig. 1F, a patterning process is performed on the solder mask layer to form a patterned solder mask layer. For example, the first solder mask layer 1421 and the second solder mask layer 1441 are patterned to form the first patterned solder mask layer 142 and the second patterned solder mask layer 144, respectively. The patterned solder mask layer can have different patterns according to the actual design requirement. For example, the first patterned solder mask layer 142 may have at least one opening OP4, wherein the at least one opening OP4 may expose a portion of the first patterned circuit layer 114 and the top surface 120a of the heat slug 120, and the second patterned solder mask layer 144 may have a plurality of openings OP5, wherein the plurality of openings OP5 expose a portion of the second patterned circuit layer 116 and the bottom surface 120b of the heat slug 120. In this embodiment, a surface treatment (plating) is further performed on the electrical contacts exposed subsequently.
Referring to fig. 1G, the chip 150 is disposed on the first surface 130a, the chip 150 is electrically connected to the substrate 130, and the orthogonal projection of the chip 150 on the substrate 130 overlaps the heat dissipation block 120, so that the chip 150 can dissipate heat through the heat dissipation block 120 embedded in the substrate 130, and heat generated during the operation of the chip 150 is transferred from the first surface 130a to the second surface 130b of the substrate 130. In the embodiment, the chip 150 may be located in the opening OP4 of the first patterned solder mask 142, and the chip 150 may be disposed on the first surface 130a in a flip-chip bonding manner, so that the bump on the chip 150 having the heat dissipation or grounding function may directly contact the heat dissipation block 120 to shorten the heat dissipation path of the chip 150, but the invention is not limited thereto. The present invention is not limited to the type of the chip 150, and may be determined according to the actual design requirements.
Referring to fig. 1H, in order to prevent moisture or external foreign objects from entering and further affecting the semiconductor package structure 100, such as corrosion, short circuit or malfunction, an encapsulant 160 may be formed to encapsulate the chip 150. In the present embodiment, a portion of the encapsulant 160 may be filled into the opening OP4, and thus the encapsulant 160 may be in direct contact with a portion of the first patterned circuit layer 114, but the invention is not limited thereto. The material of the encapsulant 160 is, for example, Epoxy Molding Compound (EMC), and the encapsulant 160 is, for example, formed through a Molding process.
Referring to fig. 1I, in order to achieve a better heat dissipation effect, a heat dissipation module 172 may be selectively bonded to the heat dissipation block 120, wherein the heat dissipation block 120 and the heat dissipation module 172 form a heat dissipation assembly 170. For example, the heat dissipation module 172 may be located on the second surface 130b of the substrate 130, and the heat dissipation module 172 may be directly connected to the heat dissipation block 120 embedded in the substrate 130 to form the heat dissipation assembly 170. The orthogonal projection of the chip 150 on the substrate 130 overlaps the heat sink 170, and the heat sink 172 may be protruded on the first patterned circuit layer 114. The heat dissipation module 172 is, for example, a metal sheet, wherein the metal sheet can be connected to the heat dissipation block 120 through the heat dissipation adhesive 20, but the invention is not limited thereto. It should be noted that in other embodiments, the heat dissipation module 172 may have other different embodiments.
The heat dissipation element 170 embedded in the substrate 130 may form an effective heat dissipation path for the chip 150, as shown by the arrow in fig. 1I, so that heat generated during the operation of the chip 150 can be transferred from the first surface 130a to the second surface 130b of the substrate 130 via the heat dissipation element 170 to be dissipated, thereby effectively improving the heat dissipation efficiency of the semiconductor package structure 100, and further reducing the problem of performance degradation and even failure of the chip 150 in the semiconductor package structure 100 due to overheating.
With reference to fig. 1I, a plurality of conductive terminals 180 may be further formed on the second surface 130b, and the conductive terminals 180 are electrically connected to the substrate 130, wherein the conductive terminals 180 may be further connected to other components, such as a PCB. In the present embodiment, the plurality of conductive terminals 180 may surround the heat sink assembly 170. In other words, the conductive terminals 180 can be located on both sides of the heat sink assembly 170. The conductive terminals 180 may be solder balls, but the invention is not limited thereto. In one embodiment, the conductive terminal 180 may be reflowed to improve adhesion between the conductive terminal 180 and the substrate 130. The fabrication of the semiconductor package structure 100 of the present embodiment can be substantially completed through the above processes. It should be noted that the lower surface of the heat dissipation assembly 170 may selectively contact directly with an external component (e.g., a circuit board) to form a heat conduction heat dissipation path, or may also selectively maintain a distance from the external component to achieve heat dissipation by air circulation, whether contact or non-contact, and all fall within the scope of the present invention.
It should be noted that, in the following embodiments, the component numbers and part of the contents of the above embodiments are used, wherein the same or similar component numbers are used to indicate the same or similar components, and the descriptions of the same technical contents are omitted, and the description of the omitted parts can refer to the foregoing embodiments, and the descriptions of the following embodiments are not repeated.
Fig. 2 is a schematic partial cross-sectional view of a semiconductor package structure according to another embodiment of the invention. Referring to fig. 2, a semiconductor package structure 200 of the present embodiment is similar to the semiconductor package structure 100 of the previous embodiment, and the difference is: the chip 150 is disposed on the first surface 130a by wire bonding. For example, the chip 150 may be connected to the first patterned circuit layer 114 through a wire L to form an electrical connection. In the present embodiment, the height of the encapsulant 160 may be higher than the height of the wires L to completely cover the wires L.
Fig. 3 is a schematic partial cross-sectional view of a semiconductor package structure according to yet another embodiment of the invention. Referring to fig. 3, the semiconductor package structure 300 of the present embodiment is similar to the semiconductor package structure 100 of the previous embodiment, and the difference is: the semiconductor package structure 300 further includes a circuit board 390, and the heat dissipation module 372 may be a heat pipe. For example, the circuit board 390 is disposed on the heat dissipation assembly 370 and the plurality of conductive terminals 180, wherein the plurality of conductive terminals 180 and the heat dissipation assembly 370 can directly contact the circuit board 390, so that heat generated during the operation of the chip 150 can be further transmitted through the circuit board 390, thereby effectively improving the heat dissipation efficiency of the semiconductor package structure 300, and further reducing the problem of performance degradation and even failure of the chip 150 in the semiconductor package structure 300 due to overheating.
Fig. 4 is a partial cross-sectional view of a semiconductor package structure according to yet another embodiment of the invention. Referring to fig. 4, the semiconductor package structure 400 of the present embodiment is similar to the semiconductor package structure 300 of the previous embodiment, and the difference is: the heat dissipation module 472 in the heat dissipation assembly 470 may be a water-cooled heat sink. Here, the water-cooled heat sink achieves the heat dissipation effect through phase change, for example.
It should be noted that although the above embodiments only illustrate the heat dissipation module existing alone, such as the metal sheet shown in fig. 1I, the heat pipe shown in fig. 3, and the water-cooled heat sink shown in fig. 4, the invention is not limited thereto, and the heat dissipation module may be a combination of a plurality of heat dissipation members. For example, the heat dissipation module may be a combination of a metal sheet, a heat pipe, and a water-cooled heat sink.
Fig. 5 is a partial cross-sectional view of a semiconductor package structure according to yet another embodiment of the invention. Referring to fig. 5, the semiconductor package structure 500 of the present embodiment is similar to the semiconductor package structure 100 of the previous embodiment, and the difference is: the heat dissipation assembly 170 and the circuit board 390 may be connected by a heat dissipation material 592 (e.g., a thermal paste, a thermal spreader, or a solder paste), so as to further effectively improve the heat dissipation efficiency of the semiconductor package structure 500, and further reduce the problem of performance degradation or even failure of the chip 150 in the semiconductor package structure 500 due to overheating.
In summary, the heat dissipation assembly embedded in the substrate of the present invention can form an effective heat dissipation path for the chip, so that the heat generated during the operation of the chip can be transferred from the first surface to the second surface of the substrate to be dissipated through the heat dissipation assembly, thereby effectively improving the heat dissipation efficiency of the semiconductor package structure, and further reducing the problem of performance degradation and even failure of the chip in the semiconductor package structure due to overheating. In addition, the semiconductor packaging structure can further comprise a circuit board positioned on the heat dissipation assembly and the plurality of conductive terminals, and the heat dissipation module can have different embodiments, so that the heat dissipation efficiency of the semiconductor packaging structure is further effectively improved, and the problem of efficiency attenuation and even failure of a chip in the semiconductor packaging structure due to overheating is further reduced.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A semiconductor package structure, comprising:
a substrate having a first surface and a second surface opposite to the first surface;
the chip is positioned on the first surface and electrically connected with the substrate;
the packaging colloid encapsulates the chip;
the heat dissipation assembly is positioned on the second surface, and part of the heat dissipation assembly is embedded into the substrate, wherein the orthographic projection of the chip on the substrate is overlapped with the heat dissipation assembly; and
and the conductive terminals are positioned on the second surface and electrically connected with the substrate, wherein the conductive terminals surround the heat dissipation assembly.
2. The semiconductor package structure of claim 1, wherein the heat spreader comprises a slug and a heat spreader module bonded to the slug, the slug penetrates through the substrate and is exposed at the first surface, and the heat spreader module is protruded at the second surface.
3. The semiconductor package structure of claim 2, wherein the heat dissipation module comprises a metal sheet, a heat pipe, a water-cooled heat sink, or a combination thereof.
4. The semiconductor package of claim 1, further comprising a circuit board on the heat spreader component and the plurality of conductive terminals, wherein the plurality of conductive terminals are in direct contact with the circuit board.
5. The semiconductor package structure of claim 4, wherein the heat dissipation assembly is in direct contact with the circuit board.
6. The semiconductor package structure of claim 4, wherein the heat dissipation assembly is connected to the circuit board by a heat dissipation paste, a heat dissipation adhesive or a solder paste.
7. A method for manufacturing a semiconductor package structure, comprising:
providing a substrate, wherein the substrate has a first surface and a second surface opposite to the first surface;
configuring a chip on the first surface and electrically connected with the substrate;
forming a packaging colloid to package the chip;
forming a heat dissipation assembly on the second surface and embedding a portion of the heat dissipation assembly in the substrate, wherein an orthographic projection of the chip on the substrate overlaps the heat dissipation assembly; and
and forming a plurality of conductive terminals on the second surface and electrically connected with the substrate, wherein the plurality of conductive terminals surround the heat dissipation assembly.
8. The method of manufacturing a semiconductor package structure according to claim 7, further comprising:
providing a multilayer board, wherein the multilayer board comprises a core layer and a conductive layer formed on the core layer;
removing part of the core layer and part of the conductive layer to form an opening penetrating through the multilayer board;
filling a heat conduction material in the opening to form a heat dissipation block;
performing a patterning process on the remaining conductive layer to form a patterned circuit layer, wherein the remaining core layer and the patterned circuit layer constitute the substrate;
and the heat dissipation module is connected to the heat dissipation block and is convexly arranged on the patterned circuit layer, wherein the heat dissipation block and the heat dissipation module form the heat dissipation assembly.
9. The method of claim 8, wherein the thermally conductive material fills the opening.
10. The method as claimed in claim 7, wherein the chip is disposed on the first surface by flip-chip bonding or wire bonding.
CN202010348023.7A 2020-01-21 2020-04-28 Semiconductor package structure and manufacturing method thereof Pending CN113224014A (en)

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