CN113223947B - Method for forming gate oxide layer - Google Patents
Method for forming gate oxide layer Download PDFInfo
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- CN113223947B CN113223947B CN202110410686.1A CN202110410686A CN113223947B CN 113223947 B CN113223947 B CN 113223947B CN 202110410686 A CN202110410686 A CN 202110410686A CN 113223947 B CN113223947 B CN 113223947B
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- oxide layer
- gate oxide
- forming
- oxidation process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
Abstract
The application discloses a forming method of a gate oxide layer, and relates to the field of semiconductor manufacturing. The forming method of the gate oxide layer comprises the steps of forming a first oxide layer on the surface of a silicon substrate through a furnace tube wet oxidation process; forming a second oxide layer on the surface of the first oxide layer by a rapid thermal oxidation process, wherein the first oxide layer and the second oxide layer form a gate oxide layer; the problem of interface trapped charges of a gate oxide-silicon substrate interface easily caused in the manufacturing process of the conventional gate oxide is solved; the method achieves the effects of reducing the nitrogen content in the interface of the silicon substrate and the gate oxide layer and ensuring the performance of the device.
Description
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to a method for forming a gate oxide layer.
Background
In the manufacturing process of a semiconductor device, oxidation treatment is carried out on a silicon wafer, and an oxide layer is formed on the surface of the silicon wafer through an oxidation process. Gate oxide is an important structure in MOS devices.
In the deep submicron process, the thin gate oxide layer is grown by a furnace tube process. In the furnace tube gate oxide process, after wet oxidation is finished, a nitrogen annealing process is used to improve the quality of a gate oxide layer and reduce interface trap charges of a gate oxide layer-silicon interface.
In the actual generation process, after nitrogen annealing, nitrogen elements can be gathered at the gate oxide-silicon interface, so that the nitrogen element enrichment state of the interface can be caused, and the device performance can be influenced.
Disclosure of Invention
In order to solve the problems in the related art, the application provides a method for forming a gate oxide layer. The technical scheme is as follows:
in a first aspect, an embodiment of the present application provides a method for forming a gate oxide layer, where the method includes:
forming a first oxide layer on the surface of the silicon substrate through a furnace tube wet oxidation process;
and forming a second oxide layer on the surface of the first oxide layer by a rapid thermal oxidation process, wherein the first oxide layer and the second oxide layer form a gate oxide layer.
Optionally, in the process of forming the first oxide layer by a furnace tube wet oxidation process, the oxidation temperature is 720-800 ℃, and the oxidation time is 10-20 min.
Optionally, in the process of forming the first oxide layer by using a furnace tube wet oxidation process, the hydrogen flow is 1slm-7slm, and the oxygen flow is 1slm-7slm.
Optionally, the first oxide layer has a thickness of 20 angstroms to 50 angstroms.
Optionally, in the process of forming the second oxide layer by a rapid thermal oxidation process, the oxidation temperature is 900 ℃ to 1100 ℃ and the oxidation time is 5s to 60s.
Optionally, in the process of forming the second oxide layer by using a rapid thermal oxidation process, pure oxygen is used for oxidation, and the oxygen flow is 10slm to 30slm.
Optionally, the thickness of the second oxide layer is 5 angstroms to 20 angstroms.
The technical scheme at least comprises the following advantages:
forming a first oxide layer on the surface of the silicon substrate through a furnace tube wet oxidation process; forming a second oxide layer on the surface of the first oxide layer by a rapid thermal oxidation process, wherein the first oxide layer and the second oxide layer form a gate oxide layer; the problem of interface trapped charges of a gate oxide-silicon substrate interface easily caused in the manufacturing process of the conventional gate oxide is solved; the nitrogen content in the interface (Si-SiO 2 interface) of the silicon substrate and the gate oxide layer is reduced, and the performance of the device is ensured.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing a gate oxide layer according to an embodiment of the present application;
FIG. 2 is a device structure for fabricating a gate oxide layer according to an embodiment of the present application;
fig. 3 is a graph illustrating the variation of nitrogen concentration in a device with a gate oxide layer according to an embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a flow chart of a method for forming a gate oxide layer according to an embodiment of the present application is shown, the method including the following steps:
And putting the silicon wafer into a furnace tube, and forming a first oxide layer on the surface of the silicon wafer through a furnace tube wet oxidation process.
And 102, forming a second oxide layer on the surface of the first oxide layer through a rapid thermal oxidation process, wherein the first oxide layer and the second oxide layer form a gate oxide layer.
As shown in fig. 2, the silicon wafer 21 having the first oxide layer 22 formed thereon is subjected to rapid thermal oxidation treatment to form a second oxide layer 23 on the surface of the first oxide layer 22, and the first oxide layer 22 and the second oxide layer 23 form a gate oxide layer.
The material of the gate oxide layer is silicon dioxide.
According to the method for forming the gate oxide layer, in the process of forming the gate oxide layer, a rapid thermal oxidation process is used for replacing a nitrogen annealing process, so that the nitrogen content in an interface (Si-SiO 2 interface) between a silicon substrate and the gate oxide layer is reduced, and excessive nitrogen elements are prevented from being gathered at the interface between the silicon substrate and the gate oxide layer; the problem of interface trapped charges of a gate oxide-silicon substrate interface easily caused in the manufacturing process of the conventional gate oxide is solved.
In an alternative embodiment based on the embodiment shown in fig. 1, in the process of forming the first oxide layer by the furnace tube wet oxidation process, the oxidation temperature is 720-800 ℃, and the oxidation time is 10-20 min.
In the process of forming the first oxide layer by a furnace tube wet oxidation process, oxygen and hydrogen are used as reaction gases, wherein the hydrogen flow is 1slm-7slm, and the oxygen flow is 1slm-7slm.
Optionally, the first oxide layer is formed to a thickness of 20 angstroms to 50 angstroms.
In an alternative embodiment based on the embodiment shown in fig. 1, the oxidation temperature is 900-1100 ℃ and the oxidation time is 5-60 s during the formation of the second oxide layer by a rapid thermal oxidation process.
And in the process of forming the second oxide layer by a rapid thermal oxidation process, pure oxygen is adopted for oxidation, and the oxygen flow is 10slm-30slm.
Optionally, the second oxide layer is formed to a thickness of 5 to 20 angstroms.
In one example, a conventional wet oxidation process and pure nitrogen annealing are used to fabricate the gate oxide layer, specifically, a silicon wafer is wet-oxidized at 750 ℃ under normal pressure for 15min 2 :O 2 :N 2 The gas flow ratio of (1) is 2; the nitrogen content of the interface of the gate oxide (SiO 2) -silicon substrate (Si) on the silicon wafer is detected, the nitrogen concentration is detected to be about 1.1E19 atom/cc, and a curve 31 in figure 3 corresponds to the relationship between the nitrogen concentration and the depth in the device after the gate oxide is manufactured by adopting the prior art.
In another example, the method provided by the embodiment of the application is adopted to manufacture the gate oxide layer, specifically, a silicon wafer is firstly subjected to wet oxidation for 15min under the condition of 750 ℃ and normal pressure 2 :O 2 :N 2 The gas flow ratio of (1) is 2; detecting the nitrogen content of the interface of a gate oxide layer (SiO 2) -silicon substrate (Si) on a silicon wafer, and determining that the nitrogen concentration is about 1.3E18 atom/cc, wherein a curve 32 in figure 3 corresponds to the relationship between the nitrogen concentration and the depth in the device after the gate oxide layer is manufactured by adopting the method provided by the embodiment of the application.
It can be seen that by using the gate oxide layer forming method provided by the embodiment of the application, the nitrogen concentration of the gate oxide layer (SiO 2) -silicon substrate (Si) interface is reduced by 88%.
After the pure nitrogen annealing process in the prior art is replaced by the rapid thermal oxidation process under the pure oxygen condition, the manufacturing step of the gate oxide layer process is not required to be added, the process time for forming the second oxide layer by utilizing the rapid thermal oxidation process is shorter, the cost is not additionally increased, the nitrogen concentration of the interface of the gate oxide layer (SiO 2) -silicon substrate (Si) is reduced, and the performance of the device is ensured.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (6)
1. A method for forming a gate oxide layer, the method comprising:
forming a first oxide layer on the surface of the silicon substrate through a furnace tube wet oxidation process;
forming a second oxide layer on the surface of the first oxide layer by a rapid thermal oxidation process, wherein the first oxide layer and the second oxide layer form a gate oxide layer;
wherein, in the process of forming the first oxide layer by a furnace tube wet oxidation process, the oxidation temperature is 720-800 ℃, and the oxidation time is 10-20 min;
and in the process of forming the second oxide layer by a rapid thermal oxidation process, pure oxygen is adopted for oxidation, and the oxygen flow is 10slm-30slm.
2. The method of claim 1, wherein during the forming of the first oxide layer by a furnace tube wet oxidation process, a hydrogen flow rate is 1slm to 7slm and an oxygen flow rate is 1slm to 7slm.
3. The method of claim 1, wherein the first oxide layer has a thickness of 20 to 50 angstroms.
4. The method according to claim 1, wherein the oxidation temperature is 900-1100 ℃ and the oxidation time is 5-60 s during the formation of the second oxide layer by a rapid thermal oxidation process.
5. The method of claim 4, wherein the second oxide layer is formed by a rapid thermal oxidation process using pure oxygen oxidation at an oxygen flow rate of 10slm to 30slm.
6. The method of claim 1, wherein the second oxide layer has a thickness of 5 to 20 angstroms.
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| CN202110410686.1A CN113223947B (en) | 2021-04-14 | 2021-04-14 | Method for forming gate oxide layer |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5290718A (en) * | 1992-06-29 | 1994-03-01 | National Semiconductor Corporation | Simplified high reliability gate oxide process |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5290718A (en) * | 1992-06-29 | 1994-03-01 | National Semiconductor Corporation | Simplified high reliability gate oxide process |
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