CN113223583A - Method for rereading data in NAND Flash bad block, electronic equipment and storage medium - Google Patents
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
Abstract
The application relates to the technical field of data processing, in particular to a method for rereading data in a NAND Flash bad block, electronic equipment and a storage medium, wherein the method comprises the following steps: when the bad block is detected, adding the bad block into a bad block queue; when the real-time state of the main control chip is in an idle state, acquiring all rereading threshold voltages, and sequentially adopting the rereading threshold voltages to reread bad blocks in a bad block queue; and when the data in the bad block is successfully read or the real-time state of the main control chip is converted into a non-idle state, finishing the rereading of the current bad block. The method and the device have the effect of reducing damage and loss of the NAND Flash bad block data.
Description
Technical Field
The present application relates to the field of data processing technologies, and in particular, to a method for re-reading data in a bad block of NAND Flash, an electronic device, and a storage medium.
Background
The basic memory cell of Flash is a floating gate transistor. With the development of the NAND Flash technology, SLC/MLC/TLC NAND Flash appears, for Cell storage, MLC/TLC NAND Flash cells can store more Bit data (SLC stores one Bit per Cell, MLC stores two bits per Cell, TLC stores three bits per Cell), the more the number of bits stored in a unit Cell is, the more the whole storage capacity is doubled, but at the same time, because the more states to be represented in the Cell are, the more Bit jump is likely to occur under the influence of different environments.
The NAND Flash read operation is to add a read voltage to a Cell, represent different storage states through different threshold voltage conduction conditions, and further represent different data states in the Cell, and the threshold voltage can shift leftwards or rightwards integrally due to the influence of an operating temperature environment.
In order to solve the problem that error bits of Read data are increased due to threshold voltage offset, and data cannot be corrected, a NAND factory generally provides dozens of sets of Read retry parameters under different use scenes to form a retry parameter set for adjusting threshold offset re-reading and ensuring data correctness, but because the NAND Flash has different batch quality differences and an overproof high and low temperature use scene may exist, the retry parameter set provided by the factory cannot completely meet the requirement of ensuring data correctness of the high and low temperature use scene.
In the prior art, a small number of special retry parameter sets are added for high and low temperature use scenes to enhance the correct readability of the NAND Flash in various high and low temperature use scenes.
Along with the increase of the number of the retry parameter groups, the number of Read retry times is increased, which causes that the Read response time is prolonged and the Read performance is slowed, because the Host end of the intelligent terminal platform has a clear requirement on the Read timeout time, the number of the increased Read retry parameters is limited, the requirement on the correct readability of data in various scenes of NAND Flash cannot be met, and data blocks with retry failures can be set to be bad blocks, so that the data damage and loss are caused, and urgent solution is needed.
Disclosure of Invention
In order to reduce damage and loss of NAND Flash bad block data, the application provides a method for re-reading data in a NAND Flash bad block, electronic equipment and a storage medium.
In a first aspect, the method for rereading data in the NAND Flash bad block provided by the application adopts the following technical scheme:
the method for rereading the data in the NAND Flash bad block comprises the following steps:
when the bad block is detected, adding the bad block into a bad block queue;
when the real-time state of the main control chip is in an idle state, acquiring all rereading threshold voltages, and sequentially adopting the rereading threshold voltages to reread bad blocks in a bad block queue;
and when the data in the bad block is successfully read or the real-time state of the main control chip is converted into a non-idle state, finishing the rereading of the current bad block.
By adopting the technical scheme, all rereading threshold voltages are adopted to perform Read retry on the bad blocks in an idle state, so that the response time of normal use of Flash is not occupied, the damage and loss of data are reduced, and the reliability is improved.
Preferably, the step of adding the bad block into the bad block queue after detecting that the bad block occurs includes: when detecting that the flash memory block which can not Read data normally exists, performing Read retry on the flash memory block which can not Read data based on a preset retry parameter group;
if the flash block Read retry fails, the flash block is marked as a bad block and the bad block is added to the bad block queue.
By adopting the technical scheme, after the flash memory block which cannot be Read is detected, the Read retry is carried out on the bad block based on the preset retry parameter group, if the bad block fails, the bad block is added into the bad block queue, the bad block which can be rereaded in the allowed response time is marked as unrewritable, and therefore the reliability of data is improved, and the workload of rereading in the idle state is also reduced.
Preferably, all reread threshold voltages are obtained by: and taking the experience value selected from the rereading threshold voltage as a center, and traversing the periphery of the experience value to obtain the rereading threshold voltage.
By adopting the technical scheme, the experience value is preset, and when the threshold voltage is read again in a traversing manner, the experience value is taken as the initial threshold voltage for re-reading, so that the time for traversing to the correct threshold voltage for re-reading can be reduced, and the response time is shortened.
Preferably, the empirical values are selected in the following manner: firstly, re-reading the flash memory blocks which can not Read data based on a preset retry parameter group, and recording a group of retry parameters with least error data Bit after the flash memory blocks which can not Read data perform Read retry based on the preset retry parameter group as experience values.
By adopting the technical scheme, the parameters with the least errors are obtained by traversing and rereading the parameters in the original retry parameter group, and the method has the effect of improving the accuracy of rereading the threshold voltage.
Preferably, the obtaining of the rereading threshold voltage by shifting and traversing around the empirical value with the empirical value selected from the rereading threshold voltage as a center includes: and traversing in a left-right enumeration migration mode in a rereading threshold voltage parameter group by taking the empirical value as the initial rereading threshold voltage to obtain the rereading threshold voltage.
By adopting the technical scheme, the rereading threshold voltage close to the empirical value is gradually expanded outwards by using a left-right enumeration mode, the probability of obtaining the correct rereading threshold voltage is high, and the time can be effectively shortened.
Preferably, if the data reading is successful when the current bad block is reread, the acquired data is moved to other good flash memory blocks, and the current bad block is removed from the bad block queue.
By adopting the technical scheme, the data in the bad block is moved after the bad block is successfully read, so that the data can be correctly taken out when the data is read next time, and the reliability is improved.
In a second aspect, the present application provides an electronic device, which adopts the following technical solutions:
an electronic device comprising a memory and a processor, the memory having stored thereon a computer program that can be loaded by the processor and executed to perform any of the methods as described above.
In a third aspect, the present application provides a computer-readable storage medium, which adopts the following technical solutions:
a computer-readable storage medium storing a computer program that can be loaded by a processor and executed to perform a method according to any one of the preceding claims.
Drawings
FIG. 1 is a block diagram of a flow chart of a method for re-reading data in a bad block of a NAND Flash according to an embodiment of the present disclosure;
FIG. 2 is
An image that varies with temperature;
FIG. 3 is
Following
An image that varies with temperature;
FIG. 4 is a block diagram of a flow chart of a method for re-reading data in a bad block of a NAND Flash according to another embodiment of the present application;
FIG. 5 is a threshold voltage distribution diagram for the MLC-LP Retry;
FIG. 6 is a threshold voltage distribution diagram for the MLC-UP Retry.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described in detail below with reference to fig. 1-6 and the embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The embodiment of the application discloses a method for re-reading data in a NAND Flash bad block, wherein when the NAND Flash carries out reading operation, reading voltage is applied to a Cell, and the data state in the Cell is obtained according to the conduction conditions of different threshold voltages. In the case where the operating temperatures are different, the threshold voltage of the Cell may be shifted, resulting in an increase in read data errors.
Referring to fig. 1, the method for re-reading data in a bad block includes the following steps:
s1: and when the bad block is detected, adding the bad block into a bad block queue.
S2: and when the real-time state of the main control chip is in an idle state, acquiring all rereading threshold voltages, and sequentially adopting the rereading threshold voltages to reread bad blocks in a bad block queue.
S3: and when the data in the bad block is successfully read or the real-time state of the main control chip is converted into a non-idle state, finishing the rereading of the current bad block.
Setting, reading, and re-reading the threshold voltage, referring to fig. 2, at normal temperature (T =27 °),
threshold voltage
There are relatively large Read margins.
At high temperature (T =90 °), the Cell threshold distribution is generally left biased (voltage becomes low), and similarly, the Cell threshold distribution is left biased (voltage becomes low)
The Read margin of the threshold voltage becomes small, and the threshold voltage at a high temperature shifts, resulting in an increase in the probability of data errors.
At a low temperature (T-40 deg.), the overall Cell threshold distribution is right-biased (voltage becomes high), and the same applies to
The Read margin of the threshold voltage becomes smaller and the probability of data errors increases.
In order to solve the problem that the Read margin is reduced and the data errors are increased due to the fact that the re-reading threshold voltage distribution shifts under high and low temperatures, the Read margin is increased by adjusting the re-reading threshold voltage under different temperatures, so that the data errors are less, and the error correction can be carried out.
Referring to fig. 3, the Read-reread threshold voltage at high temperature needs to be shifted to the left, the Read-reread threshold voltage at low temperature needs to be shifted to the right, and when the reread threshold voltage is set, the NAND Flash is sampled and analyzed to add a plurality of sets of dedicated Read retry parameters.
The detection of bad blocks includes, but is not limited to, the following: 1. when the data is read and written normally, the data is read, and if the data cannot be read normally by a flash memory block, the flash memory block can be marked as a bad block; 2. when testing the reliability of the NAND Flash, quickly reading and writing data to the Flash memory block, and marking the Flash memory block as a bad block if the data of the Flash memory block cannot be read normally; 3. and when the NAND Flash is detected in a factory, marking the Flash memory block as a bad block according to the detection result. The abnormal reading is that when the flash memory block reads data, an error code is generated or the error rate exceeds the ECC check range.
When the NAND Flash reads data, if the bad block is detected, adding the bad block into a bad block queue. And when the NAND Flash is in an idle state, adopting all rereading threshold voltages, and sequentially rereading the bad pages in the bad blocks by adopting the rereading threshold voltages. The bad blocks are added into the bad block queue in advance, the bad blocks are read by traversing the re-reading threshold voltage after the idle state is reached, so that the data in the bad blocks are read, the response time of the NAND Flash in the non-idle state is shortened, and the damage and the loss of the data can be reduced.
And when the real-time state of the main control chip of the NAND Flash is converted into a non-idle state or the data in the bad block is successfully reread, finishing reread of the current bad block. If the real-time state of the main control chip of the NAND Flash is changed into a non-idle state, finishing re-reading the current bad block, and continuing to re-read the current bad block after the real-time state of the main control chip is changed into an idle state; if the data in the bad block is successfully reread, deleting the bad block from the bad block queue, and continuing to reread the next bad block.
Referring to fig. 4, alternatively, as another embodiment, the step S1 includes the following sub-steps:
s11: and when detecting that the flash memory block which can not Read data normally exists, performing Read retry on the bad block of the flash memory block which can not Read data based on a preset retry parameter group.
S12: if the flash block Read retry fails, the flash block is marked as a bad block and the bad block is added to the bad block queue.
In practical use, when data is Read, the flash memory block which cannot be Read normally is detected, and the preset retry parameter group for Read retry is used for rereading, wherein the parameter number of the retry parameter group is less than that of the preset rereading threshold voltage parameter group. If the data in the flash memory block which cannot be read normally by the threshold voltage in the retry parameter group is the data in the flash memory block, marking the flash memory block as a bad block, adding the bad block into a bad block queue, and reducing the possibility that the data which can be read again by the retry parameter group is added into the bad block queue, so that the data which can be read again is judged to be unreadable by mistake; but in other embodiments, the bad block may be added to the bad block queue as soon as the bad block is detected, to reduce response time.
Optionally, as another implementation, all rereading threshold voltages are obtained by:
and taking the experience value selected from the rereading threshold voltage as a center, and traversing the periphery of the experience value to obtain the rereading threshold voltage.
Specifically, the empirical value may be an optimal threshold voltage at the current operating temperature, but may also be other set values or values obtained through simple operations, and by setting the empirical value, when traversing and re-reading the threshold voltage, the probability of obtaining a correct re-reading threshold voltage is increased, and the traversing time is shortened.
And the rereading threshold voltage is obtained in a traversing mode, so that the problem that threshold voltage deviation cannot be covered by a retry parameter with a fixed number of groups can be solved, and the original data which cannot be corrected can be corrected correctly.
Optionally, as another embodiment, a manner of selecting the empirical value is as follows: firstly, re-reading the flash memory blocks which can not Read data based on a preset retry parameter group, and recording a group of retry parameters with least error data Bit after the flash memory blocks which can not Read data perform Read retry based on the preset retry parameter group as experience values.
When the real-time state of the main control chip is an idle state, the bad blocks in the bad block queue are obtained to be read in a traversing mode, all cells in the bad blocks are read based on parameters in a preset retry parameter group, a group of retry parameters with the least error data Bit is recorded as experience values, the experience values are used as a traversing center to traverse all around, and the retry time of the bad blocks can be effectively shortened.
Optionally, the time point of the empirical value acquisition may be: 1. when data is Read and written, detecting that a flash memory block can not Read data normally, performing Read retry on the flash memory block based on a preset retry parameter group, if the flash memory block can not be Read normally, taking a parameter with the minimum error bit number in the retry parameter group in the reading as an empirical value based on the fact that the parameter is the minimum error bit number in the retry parameter group in the reading, namely recording the empirical value while marking the flash memory block which can not Read data normally as a bad block; 2. under the condition that the main control chip is in an idle state, re-reading the bad block based on the threshold voltage in the retry parameter group, and taking the parameter with the minimum error bit number in the retry parameter group read this time as an empirical value.
Optionally, as another embodiment, taking an empirical value selected from the rereading threshold voltages as a center, shifting around the empirical value and traversing to obtain the rereading threshold voltages, includes: and traversing in a left-right enumeration migration mode in a rereading threshold voltage parameter group by taking the empirical value as the initial rereading threshold voltage to obtain the rereading threshold voltage.
The initial reread threshold voltage is the first threshold voltage to begin rereading bad blocks in the idle state.
In specific implementation, taking MLC particles as an example: one MLC WL consists of two pages LP and UP, and R1, R2, R3 represent three different read voltage register values (i.e., threshold voltages) of one Cell of MLC Flash, where LP read voltage threshold shift is associated with R2, UP read voltage threshold shift is associated with R1, R3, and each threshold voltage adjustable range is [ -128,127 ].
Referring to fig. 5, for the MLC LP, if the optimal threshold voltage offset R2 is-52 (data cannot be corrected, but the number of faulty bits is the minimum under all R2 threshold voltage values), then the point is taken as the center, 40 voltages are respectively traversed left and right through-72 to-32, the traversal mode is that R2-1, R2+1, R2-2, R2+2 … R2-20 and R2+20 are first, and retry is performed through alternate traversal until retry pass, data migration rewrite is immediately enabled, and it is ensured that data can be correctly read subsequently.
Referring to fig. 6, for MLC UP, assuming that the optimal threshold offset is (R1, R3) = (-203, -106), based on the optimal threshold offset point, R1, R3 are combined by ± 20, and then full-combining alternating traversal is performed with ([ -4043,0-3], [ -3036,104]), and the traversal is performed until retry pass, and data transfer rewrite is immediately enabled, ensuring that data can be correctly read subsequently.
Referring to fig. 4, optionally, as another embodiment, the method further includes the following steps:
s4: and if the data reading is successful when the current bad block is reread, the acquired data is moved to other good flash memory blocks, and the current bad block is removed from the bad block queue.
When the current bad block is reread, the data in the bad block is moved to other good Flash memory blocks if the reread is successful, so that the reread data are prevented from being lost for the second time, the bad block is deleted from the storage queue, the reliability of the NAND Flash is improved, and the situation that the data in the bad block cannot be read out again is reduced.
If the data cannot be read out after traversing all the rereading threshold voltages, marking the bad block as uncorrectable, and subsequently, performing enumeration traversal error correction on the bad block.
The embodiment also discloses an electronic device, which comprises a memory and a processor, wherein the memory is stored with a computer program which can be loaded by the processor and can execute the method.
The present embodiment also discloses a computer readable storage medium storing a computer program that can be loaded by a processor and execute the method as described above.
The above embodiments are preferred embodiments of the present application, and the protection scope of the present application is not limited by the above embodiments, so: all equivalent variations made according to the methods and principles of the present application should be covered by the protection scope of the present application.
Claims (8)
- The method for re-reading the data in the NAND Flash bad block is characterized by comprising the following steps of:when the bad block is detected, adding the bad block into a bad block queue;when the real-time state of the main control chip is in an idle state, acquiring all rereading threshold voltages, and sequentially adopting the rereading threshold voltages to reread bad blocks in a bad block queue;and when the data in the bad block is successfully read or the real-time state of the main control chip is converted into a non-idle state, finishing the rereading of the current bad block.
- 2. The method for re-reading the data in the NAND Flash bad block according to claim 1, wherein the step of adding the bad block to the bad block queue after detecting the bad block, comprises:when detecting that the flash memory block which can not Read data normally exists, performing Read retry on the flash memory block which can not Read data based on a preset retry parameter group;if the flash block Read retry fails, the flash block is marked as a bad block and the bad block is added to the bad block queue.
- 3. The method for re-reading the data in the NAND Flash bad block according to claim 1 or 2, wherein all re-reading threshold voltages are obtained by: and taking the experience value selected from the rereading threshold voltage as a center, and traversing the periphery of the experience value to obtain the rereading threshold voltage.
- 4. The method for rereading data in a NAND Flash bad block according to claim 3, wherein the empirical value is selected by: firstly, re-reading the flash memory blocks which can not Read data based on a preset retry parameter group, and recording a group of retry parameters with least error data Bit after the flash memory blocks which can not Read data perform Read retry based on the preset retry parameter group as experience values.
- 5. The method for re-reading the data in the NAND Flash bad block according to claim 4, wherein the step of obtaining the re-reading threshold voltage by shifting and traversing around the empirical value with the empirical value selected from the re-reading threshold voltage as a center comprises: and traversing in a left-right enumeration migration mode in a rereading threshold voltage parameter group by taking the empirical value as the initial rereading threshold voltage to obtain the rereading threshold voltage.
- 6. The method for rereading data in a NAND Flash bad block according to claim 1, further comprising the steps of:and if the data reading is successful when the current bad block is reread, the acquired data is moved to other good flash memory blocks, and the current bad block is removed from the bad block queue.
- 7. An electronic device comprising a memory and a processor, the memory having stored thereon a computer program that can be loaded by the processor and that executes the method according to any of claims 1 to 6.
- 8. A computer-readable storage medium, in which a computer program is stored which can be loaded by a processor and which executes the method of any one of claims 1 to 6.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113672178A (en) * | 2021-10-25 | 2021-11-19 | 珠海妙存科技有限公司 | nand flash rereading positioning method |
| CN114296645A (en) * | 2021-12-17 | 2022-04-08 | 合肥大唐存储科技有限公司 | Rereading method in Nand flash memory and solid state disk |
| CN117789808A (en) * | 2024-02-26 | 2024-03-29 | 合肥康芯威存储技术有限公司 | Memory and bad block error correction method thereof |
Citations (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060002096A1 (en) * | 2004-06-30 | 2006-01-05 | Kuang-Yu Wang | System and method for providing a flash memory assembly |
| KR100759590B1 (en) * | 2006-06-20 | 2007-09-18 | 경북대학교 산학협력단 | Method for initializing flash memory of mobile device and recording medium recorded program according to the method |
| US20070297226A1 (en) * | 2006-06-22 | 2007-12-27 | Nima Mokhlesi | Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages |
| CN101409111A (en) * | 2007-10-11 | 2009-04-15 | 智多星电子科技有限公司 | Method for formatting/testing general sequence bus device |
| US20110044101A1 (en) * | 2009-08-18 | 2011-02-24 | Skymed Corporation | Method and system of finding a read voltage for a flash memory |
| US20110066899A1 (en) * | 2009-09-17 | 2011-03-17 | Samsung Electronics Co., Ltd. | Nonvolatile memory system and related method of performing erase refresh operation |
| JP2011238346A (en) * | 2011-06-16 | 2011-11-24 | Sandisk Il Ltd | Method for restoration from error in flash memory |
| CN103914358A (en) * | 2014-04-03 | 2014-07-09 | 深圳市硅格半导体有限公司 | Flash memory rereading method and device |
| US20140215133A1 (en) * | 2013-01-29 | 2014-07-31 | Samsung Electronics Co., Ltd. | Memory system and related block management method |
| CN104091617A (en) * | 2014-06-17 | 2014-10-08 | 深圳市江波龙电子有限公司 | Flash memory equipment detection method and apparatus thereof |
| CN106502583A (en) * | 2016-10-12 | 2017-03-15 | 记忆科技(深圳)有限公司 | A kind of method for reducing solid state hard disc operating lag |
| US20170125090A1 (en) * | 2015-10-28 | 2017-05-04 | Lite-On Electronics (Guangzhou) Limited | Solid state storage device and reading control method thereof |
| CN106681936A (en) * | 2016-12-29 | 2017-05-17 | 记忆科技(深圳)有限公司 | Bad block management method for NANDFLASH |
| US9659664B1 (en) * | 2015-12-15 | 2017-05-23 | International Business Machines Corporation | Dynamically adjusting read voltage in a NAND flash memory |
| US20190304553A1 (en) * | 2018-03-28 | 2019-10-03 | SK Hynix Inc. | Memory device and operating method thereof |
| CN111200440A (en) * | 2018-11-19 | 2020-05-26 | 爱思开海力士有限公司 | LDPC decoder, semiconductor memory system and operating method thereof |
| US20210027845A1 (en) * | 2019-07-23 | 2021-01-28 | SK Hynix Inc. | Read retry threshold voltage selection |
| CN112530499A (en) * | 2020-12-09 | 2021-03-19 | 合肥康芯威存储技术有限公司 | Data reading method and computer readable storage device |
| CN112599177A (en) * | 2020-12-23 | 2021-04-02 | 深圳大普微电子科技有限公司 | Threshold voltage management method and method for reading flash memory data |
-
2021
- 2021-05-14 CN CN202110529537.7A patent/CN113223583A/en active Pending
Patent Citations (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060002096A1 (en) * | 2004-06-30 | 2006-01-05 | Kuang-Yu Wang | System and method for providing a flash memory assembly |
| KR100759590B1 (en) * | 2006-06-20 | 2007-09-18 | 경북대학교 산학협력단 | Method for initializing flash memory of mobile device and recording medium recorded program according to the method |
| US20070297226A1 (en) * | 2006-06-22 | 2007-12-27 | Nima Mokhlesi | Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages |
| CN101409111A (en) * | 2007-10-11 | 2009-04-15 | 智多星电子科技有限公司 | Method for formatting/testing general sequence bus device |
| US20110044101A1 (en) * | 2009-08-18 | 2011-02-24 | Skymed Corporation | Method and system of finding a read voltage for a flash memory |
| US20110066899A1 (en) * | 2009-09-17 | 2011-03-17 | Samsung Electronics Co., Ltd. | Nonvolatile memory system and related method of performing erase refresh operation |
| JP2011238346A (en) * | 2011-06-16 | 2011-11-24 | Sandisk Il Ltd | Method for restoration from error in flash memory |
| US20140215133A1 (en) * | 2013-01-29 | 2014-07-31 | Samsung Electronics Co., Ltd. | Memory system and related block management method |
| CN103914358A (en) * | 2014-04-03 | 2014-07-09 | 深圳市硅格半导体有限公司 | Flash memory rereading method and device |
| CN104091617A (en) * | 2014-06-17 | 2014-10-08 | 深圳市江波龙电子有限公司 | Flash memory equipment detection method and apparatus thereof |
| US20170125090A1 (en) * | 2015-10-28 | 2017-05-04 | Lite-On Electronics (Guangzhou) Limited | Solid state storage device and reading control method thereof |
| US9659664B1 (en) * | 2015-12-15 | 2017-05-23 | International Business Machines Corporation | Dynamically adjusting read voltage in a NAND flash memory |
| CN106502583A (en) * | 2016-10-12 | 2017-03-15 | 记忆科技(深圳)有限公司 | A kind of method for reducing solid state hard disc operating lag |
| CN106681936A (en) * | 2016-12-29 | 2017-05-17 | 记忆科技(深圳)有限公司 | Bad block management method for NANDFLASH |
| US20190304553A1 (en) * | 2018-03-28 | 2019-10-03 | SK Hynix Inc. | Memory device and operating method thereof |
| CN111200440A (en) * | 2018-11-19 | 2020-05-26 | 爱思开海力士有限公司 | LDPC decoder, semiconductor memory system and operating method thereof |
| US20210027845A1 (en) * | 2019-07-23 | 2021-01-28 | SK Hynix Inc. | Read retry threshold voltage selection |
| CN112530499A (en) * | 2020-12-09 | 2021-03-19 | 合肥康芯威存储技术有限公司 | Data reading method and computer readable storage device |
| CN112599177A (en) * | 2020-12-23 | 2021-04-02 | 深圳大普微电子科技有限公司 | Threshold voltage management method and method for reading flash memory data |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113672178A (en) * | 2021-10-25 | 2021-11-19 | 珠海妙存科技有限公司 | nand flash rereading positioning method |
| CN113672178B (en) * | 2021-10-25 | 2022-03-18 | 珠海妙存科技有限公司 | nand flash rereading positioning method |
| CN114296645A (en) * | 2021-12-17 | 2022-04-08 | 合肥大唐存储科技有限公司 | Rereading method in Nand flash memory and solid state disk |
| CN114296645B (en) * | 2021-12-17 | 2024-01-02 | 合肥大唐存储科技有限公司 | Rereading method in Nand flash memory and solid state disk |
| CN117789808A (en) * | 2024-02-26 | 2024-03-29 | 合肥康芯威存储技术有限公司 | Memory and bad block error correction method thereof |
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