CN113219799A - Wafer semiconductor product, mask and photoetching machine - Google Patents
Wafer semiconductor product, mask and photoetching machine Download PDFInfo
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- CN113219799A CN113219799A CN202110317708.XA CN202110317708A CN113219799A CN 113219799 A CN113219799 A CN 113219799A CN 202110317708 A CN202110317708 A CN 202110317708A CN 113219799 A CN113219799 A CN 113219799A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 111
- 238000001259 photo etching Methods 0.000 title abstract description 16
- 230000003287 optical effect Effects 0.000 claims abstract description 193
- 239000011159 matrix material Substances 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 238000001459 lithography Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 13
- 230000000694 effects Effects 0.000 description 4
- 239000002699 waste material Substances 0.000 description 4
- 230000003993 interaction Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
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- 239000000463 material Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000001143 conditioned effect Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
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- 238000000206 photolithography Methods 0.000 description 1
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7073—Alignment marks and their environment
- G03F9/7084—Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7073—Alignment marks and their environment
- G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
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Abstract
The invention provides a wafer semiconductor product, a mask plate and a photoetching machine, wherein the wafer semiconductor product comprises an optical alignment field and a plurality of tube core exposure fields; the optical alignment field includes at least one optical alignment target mark, at least one first fine alignment target mark, and a plurality of dies; wherein, the alignment precision of the optical alignment target mark is lower than that of the fine alignment target mark, and the distance between the die and the optical alignment target mark is not less than a preset safety distance. Because the effective tube cores are arranged in the blank area except the alignment target mark area in the optical alignment field, and the distance between the optical alignment target mark and the adjacent tube core is not less than a preset safety distance, the mutual influence of the tube cores and the optical alignment target mark is avoided, and the number of the effective tube cores is increased on the premise of ensuring the realization of the alignment function of the optical alignment field.
Description
Technical Field
The invention relates to the technical field of chip manufacturing processes, in particular to a wafer semiconductor product, a mask and a photoetching machine.
Background
Before the chip photoetching process of an Ultratech Stepper photoetching machine (stepping photoetching machine), the photoetching machine needs to be aligned with a wafer, and the general alignment steps are as follows: firstly, a wafer is rotated on a wafer worktable by a mechanical handle, the wafer is aligned with the wafer worktable, and Optical Alignment (OAT Alignment for short) is carried out by using a first mask plate through an Optical Alignment Target Mark (OAT Mark) on the first mask plate. The corresponding location on the wafer semiconductor product is the optical alignment field (OAT field), and there are usually two or more OAT fields on a wafer semiconductor product. After OAT alignment is carried out by a calibration system of the photoetching machine, rough calibration of X (X coordinate parameter)/Y (Y coordinate parameter)/theta (included angle parameter between X direction and Y direction) is carried out. And then, the stepper moves to the position of a preset first die exposure field, a second mask is used, fine alignment is carried out through a fine alignment target mark (AKmark) on the second mask, and after alignment, fine correction of X/Y/theta is carried out. And then, carrying out exposure operation on the current die exposure field, and moving to the next die exposure field step by step to carry out fine alignment (AK alignment) again.
In general, in order to perform OAT alignment, an optical alignment field must be set, and only an optical alignment target mark and no die are set in the optical alignment field, and the space area of the wafer semiconductor product is limited, which is wasteful.
Disclosure of Invention
The present invention aims to solve at least one of the above technical problems to at least some extent or to at least provide a useful commercial choice. One objective of the present invention is to provide a wafer semiconductor product, which can increase the number of effective dies in the same wafer area, and reduce the cost.
According to the invention, a wafer semiconductor product comprises an optical alignment field and a plurality of die exposure fields; the optical alignment field is formed by exposing a first mask, and the plurality of tube core exposure fields are arranged on the wafer semiconductor product in a dot matrix manner in the areas except the optical alignment field and are formed by sequentially exposing a second mask; wherein the optical alignment field comprises at least one optical alignment target mark, at least one first fine alignment target mark, and a plurality of dies, and none of the optical alignment target mark, the first fine alignment target mark, and the plurality of dies are disposed in an overlapping manner; wherein, the alignment precision of the optical alignment target mark is lower than that of the fine alignment target mark, and the distance between the die and the optical alignment target mark is not less than a preset safety distance.
The preset safety distance is not less than 50 microns; the distance between the optical alignment target mark and the adjacent die is 50-120 microns.
The optical alignment field is divided into a first region and a second region other than the first region; the optical alignment target mark is arranged in the first area; the first fine alignment target mark and the plurality of dies are disposed in the second area, and the dies are arranged in a matrix in the second area.
The second area also comprises at least one virtual die, the size of the virtual die is the same as that of the die in the second area, the virtual die and the plurality of dies in the second area are arranged together in a matrix, and the distance between two adjacent columns or rows of dies is equal; and no die is arranged at the virtual die, the first fine alignment target mark is arranged in the area corresponding to the virtual die, and the width of the first fine alignment target mark is larger than the distance between two adjacent columns or two rows of the dies.
More than two first fine alignment target marks are arranged in the virtual die, at least one of the at least two first fine alignment target marks is a convex mark, and at least one of the at least two first fine alignment target marks is a concave mark.
The distance between the first fine alignment target mark and the adjacent die is 50-300 microns.
Each die exposure field comprises a plurality of dies arranged in a matrix and second fine alignment target marks; the die and the second fine alignment target mark are arranged in a non-overlapping mode, and the distance between the die at the extreme edge of the optical alignment field and the die at the extreme edge of the die exposure field is 50-120 micrometers.
The optical alignment field is a complete field, and the optical alignment field is a rectangular area; the optical alignment field includes at least two optical alignment target marks disposed at two short side positions near the optical alignment field, respectively.
The invention also provides a mask plate for manufacturing the wafer semiconductor product, which comprises the following steps: an optical alignment target mark exposure pattern, a fine alignment target mark exposure pattern, and a plurality of die exposure patterns; the optical alignment target mark exposure pattern is used for exposing an optical alignment target mark of an optical alignment field formed on a wafer semiconductor product; the first fine alignment target mark exposure pattern for exposing a first fine alignment target mark of an optical alignment field formed on a wafer semiconductor product; the optical alignment target mark exposure pattern, the first fine alignment target mark exposure pattern and the plurality of die exposure patterns are arranged in a non-overlapping manner; the alignment precision of the optical alignment target mark pattern is lower than that of the first fine alignment target mark pattern; the distance between the die exposure pattern and the optical alignment target mark exposure pattern is not less than a preset safety distance.
The distance between the optical alignment target mark exposure pattern and the adjacent die exposure pattern is 50-120 microns. The distance between the first fine alignment target mark and the adjacent die is 60-300 microns.
The invention also provides a photoetching machine which comprises the mask as a first mask and is used for forming an optical alignment field of a wafer semiconductor product; the second mask, the alignment correction system and the exposure system; wherein the second mask is used for forming a die exposure field of the wafer semiconductor product; the alignment correction system carries out alignment correction according to the first mask or the second mask, and the exposure system carries out exposure by using the first mask or the second mask.
According to the wafer semiconductor product, the effective tube cores are arranged in the blank area except the alignment target mark area in the optical alignment field, and the distance between the optical alignment target mark and the adjacent tube cores is not less than a preset safety distance, so that the mutual influence of the tube cores and the optical alignment target mark is avoided, more tube cores can be arranged in the same area on the premise of ensuring the alignment function of the optical alignment field (OAT field), the number of the effective tube cores is increased, and the cost is reduced.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a schematic diagram of the structure of an OAT field and a die exposure field of a wafer semiconductor product according to one embodiment of the present invention;
FIG. 2 is a schematic view of a wafer semiconductor product according to another embodiment of the present invention;
FIG. 3 is a schematic diagram of the structure of the OAT field of a wafer semiconductor product according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating an embodiment of a die exposure field of the wafer semiconductor product shown in FIG. 2 according to the present invention;
FIG. 5 is a schematic diagram of a die exposure field of a wafer semiconductor product according to yet another embodiment of the present invention;
FIG. 6 is an enlarged schematic view of the embodiment of FIG. 5;
FIG. 7 is a schematic diagram of the structure of the OAT field and the die exposure field of a wafer semiconductor product according to yet another embodiment of the present invention;
FIG. 8 is a schematic diagram of the structure of the OAT field and the die exposure field of a wafer semiconductor product according to yet another embodiment of the present invention;
FIG. 9 is a schematic diagram of the structure of an OAT field of a wafer semiconductor product according to yet another embodiment of the present invention;
FIG. 10 is a schematic diagram of the structure of an OAT field of a wafer semiconductor product in accordance with still another embodiment of the present invention;
FIG. 11 is a schematic diagram of the structure of an OAT field of a wafer semiconductor product in accordance with yet another embodiment of the present invention;
FIG. 12 is a schematic diagram of the structure of an OAT field of a wafer semiconductor product according to yet another embodiment of the present invention;
FIG. 13 is a schematic diagram of the structure of the OAT field of a wafer semiconductor product according to yet another embodiment of the present invention.
Wherein: 10. an optical alignment field; 20. a die exposure field; 11. a first region; 12. a second region; 13. a virtual die; 101. optically aligning the target mark; 201. a die; 202. a first fine alignment target mark; 203. a second fine alignment target mark; 301. a first scribe lane; 302. a second scribe lane; 303. the mark scribe lanes are aligned.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
Compared with the traditional wafer semiconductor product, the wafer semiconductor product can increase the number of the tube cores under the same wafer area, thereby improving the production efficiency of the tube cores and reducing the cost.
Fig. 1 is a schematic structural diagram of an optical alignment field and a die exposure field of a wafer semiconductor product according to an embodiment of the present invention, and fig. 2 is a schematic structural diagram of a wafer semiconductor product according to the present invention. The invention provides a wafer semiconductor product, which is applied to a manufacturing process of a tube core of a wafer semiconductor product of a photoetching machine.
The wafer semiconductor product includes an optical alignment field 10(OAT field) and a plurality of die exposure fields 20. The optical alignment field 10(OAT field) is formed by exposure of a first reticle, i.e. the optical alignment field 10(OAT field) is formed on the wafer semiconductor product by photolithography exposure of the first reticle. The optical alignment field 10(OAT field) is at least one. The die exposure field 20 comprises a plurality of die regions which are arranged in a dot matrix on the wafer semiconductor product except the optical alignment field 10(OAT field), and the die exposure field 20 is formed by sequentially exposing the second mask. The die exposure field 20 is formed into a plurality of dies after a plurality of rounds of multiple exposures. It will be appreciated that the optical alignment field 10(OAT field) and the die exposure field 20 constitute the bulk structure on the wafer and occupy most of the area on the wafer. The size of the second mask is the same as that of the first mask. The optical alignment field 10(OAT field) in fig. 1 and 2 is a complete field, i.e. the optical alignment field 10(OAT field) is completely located in the wafer semiconductor product and does not partially expose the wafer semiconductor product; the optical alignment field 10(OAT field) is rectangular in shape.
At least one optical alignment target mark 101 is included in the optical alignment field 10(OAT field), as shown in fig. 2 and 3, two optical alignment target marks (OAT marks) 101 are included in the optical alignment field 10(OAT field), and the two optical alignment target marks are respectively disposed at two short side positions of the optical alignment field. The optical alignment target mark 101 is applied to rough alignment of the alignment system of the lithography machine, the size of the optical alignment target mark 101 is generally larger, and in this embodiment, the optical alignment target mark 101 is in a cross shape of 4mm × 4 mm. In other embodiments, the optical alignment target mark 101 may have other shapes with other sizes, and may be specifically configured according to actual requirements. If the first optical alignment target mark 101 does not pass the OAT alignment, the optical alignment target mark can be moved to the second optical alignment target mark 101 for the second OAT alignment. If not, the alignment of the OAT field is not passed, and then the next OAT field is moved to perform the next OAT alignment.
To further increase the die layout area and reduce the waste of die layout area, the die may be placed in an empty position within the optical alignment field 10(OAT field). In a specific implementation, referring to fig. 3, the optical alignment field 10(OAT field) is divided into a first region 11 including an optical alignment target mark 101 and a second region 12 excluding the first region 11, wherein the second region 12 has a plurality of dies 201 disposed therein, and the first fine alignment target mark 202 is disposed within the second region 12. None of the optical alignment target mark 101, the first fine alignment target mark 202, and the plurality of dies 201 are disposed in an overlapping manner.
Specifically, the optical alignment field 10(OAT field) is composed of a first area 11 and a second area 12, both the first area 11 and the second area 12 are disposed in the optical alignment field 10(OAT field), and the first area 11 and the second area 12 do not coincide, where the first area 11 is used to dispose the optical alignment target mark 101, and the second area 12 is used to dispose the plurality of dies 201 and the first fine alignment target mark 202.
In order to better optically identify the optical alignment target mark and avoid the mutual influence between the die and the OAT mark, in an optical alignment field 10(OAT field), a safety distance is set between the optical alignment target mark and the adjacent die, and the distance between the die and the optical alignment target mark is not less than the preset safety distance. I.e., the dies can be placed beyond a safety distance around the 4mm by 4mm square area of the optical alignment target mark. The safety distance can be set at a specific value of 50-120 microns, such as 60 microns, which can ensure the optical recognition effect of the optical alignment target mark, avoid wasting too much space, and arrange more dies.
According to the wafer semiconductor product, the optical alignment field 10(OAT field) is divided into the first area 11 and the second area 12, the OAT mark is filled in the first area 11, and the plurality of dies 201 are filled in the second area 12, so that on the premise that the alignment function of the optical alignment field 10(OAT field) is realized, the area on the wafer semiconductor product is not wasted, the layout number of the effective dies 201 on the wafer semiconductor product is increased, and the cost is further saved. An optical alignment field 10 is typically about 30 x 12mm in size, and the OAT mark may occupy 4 x 4mm in area, with the normal die being full except at the location of the OAT mark.
Each die exposure field 20 is formed by covering a plurality of dies 201 which are orderly and regularly arranged, and the plurality of dies 201 occupy most of the space of the die exposure field 20; as shown in fig. 4, a second fine alignment target mark 203 is further disposed in the die exposure field 20, the second fine alignment target mark 203 generally includes a plurality of second fine alignment target marks, the alignment accuracy of the second fine alignment target mark 203 is higher than the alignment accuracy of the optical alignment target mark 101, and the size of the second fine alignment target mark 203 is smaller than that of the optical alignment target mark 101, in this embodiment, the second fine alignment target mark 203 is in a cross shape of 200 × 200 um; in other embodiments, the second fine alignment target mark 203 may have other shapes with other sizes, and may be set according to actual requirements.
Correspondingly, the invention also provides a photoetching machine for manufacturing the wafer semiconductor product with the structure, wherein the photoetching machine comprises: a first mask for forming an optical alignment field (OAT field) of the wafer semiconductor product; the second mask is used for forming a die exposure field of the wafer semiconductor product; an alignment correction system; and an exposure system. The alignment correction system carries out alignment correction according to the first mask or the second mask; and the exposure system uses the first mask or the second mask to carry out exposure.
The first mask and the second mask need to change patterns corresponding to the structure of the wafer semiconductor product. Correspondingly, the first mask comprises: an optical alignment target mark exposure pattern, a fine alignment target mark exposure pattern, and a plurality of die exposure patterns (not shown in the drawings). An optical alignment target mark exposure pattern for exposing an optical alignment target mark of an optical alignment field formed on a wafer semiconductor product. A fine alignment target mark exposure pattern for exposing a fine alignment target mark of an optical alignment field formed on a wafer semiconductor product. And a plurality of die exposure patterns for exposing a plurality of dies of an optical alignment field formed on the wafer semiconductor product. The remaining alignment correction systems and exposure systems are prior art and will not be described herein.
The first fine alignment target marks 202(AK marks) disposed in the optical alignment field 10 may be two groups, disposed in pairs within the second region. Specifically, the first region may be symmetrically disposed at both left and right end edges of the second region. The distance between the first fine alignment target mark 202 located at the left edge of the second region and the first fine alignment target mark 202 located at the right edge of the second region is in the range of (3.5-14.9) × 2 mm.
In a specific implementation, the second region 12 further includes at least one dummy die 13, the size of the dummy die 13 is the same as that of the die 201, and the dummy die 13 and the plurality of dies 201 in the second region 12 are arranged in a matrix and are distributed over the second region. The spacing between every two adjacent rows or columns of die 201 is equal; the dummy die 13 is not provided with the die 201, the first fine alignment target mark 202 is arranged in the corresponding area of the dummy die 13, and the width of the first fine alignment target mark 202 is larger than the distance between two adjacent columns or two rows of the die 201.
Specifically, there are two first regions 11 of the optical alignment field 10(OAT field), which are respectively disposed at the lower left corner and the lower right corner of the optical alignment field 10(OAT field), and the size of each first region 11 is consistent with the size of the corresponding OAT mark, so as to identify the OAT mark. The second region 12, excluding the first region, is in the shape of a convex letter and includes a plurality of dies 201 and at least one dummy die 13 (two dummy dies 13 are shown in the figure). The size of the virtual die 13 is the same as that of each die 201, the virtual die 13 is not overlapped with the die 201 in the second region 12, no die is arranged at the virtual die, and the virtual die is a region without die, which is not provided with a die but has the same size and position arrangement as other dies. The dummy die 13 and the plurality of dies 201 in the second area are arranged in a matrix, and the spacing between two adjacent columns or rows of dies is equal. Die 201 is not disposed at dummy die 13, and dummy die 13 is dedicated to disposing first fine alignment target mark 202.
Correspondingly, as shown in fig. 4, the die exposure field is also provided with at least one dummy die 13 and a plurality of dies 201. The virtual die 13 and the die 201 have the same size, the virtual die 13 and the rest of the dies 201 in the exposure field of the die are arranged in a matrix, and the spaces between every two adjacent rows or columns of dies 201 are equal; the die 201 is not disposed at the position of the virtual die 13, the second fine alignment target mark 203 is disposed in a region corresponding to the virtual die 13, and the width of the second fine alignment target mark 203 is greater than the distance between two adjacent columns or rows of the die 201 (i.e., the width of the scribe lane).
In the optical alignment field 10 or the die exposure field 20, two dummy dies 13 may be symmetrically disposed in a first row of the plurality of dies arranged in a matrix. The distance between two dummy dies 13 (i.e., between two first fine alignment target marks 202 or between two second fine alignment target marks 203) may be set as far as possible, for example, at the first die position at the extreme edges of both ends, so as to reduce the possibility of interaction effects as much as possible, and avoid the occurrence of a situation where the distance between two first fine alignment target marks 202 or second fine alignment target marks 203 interferes too closely within one optical alignment field 10 or die exposure field 20, resulting in alignment failure if one first fine alignment target mark 202 or second fine alignment target mark 203 is not clearly aligned, and the other first fine alignment target mark 202 or second fine alignment target mark 203 is not clearly aligned.
However, if the dummy die (i.e., the first fine alignment target mark 202 or the second fine alignment target mark 203) is disposed at the first die position at the extreme edge of the two ends of the matrix arrangement, the risk of overlap between the adjacent die exposure fields or optical alignment fields increases, and the overlap may cause the pattern of the first fine alignment target mark 202 or the second fine alignment target mark 203 to be unclear and unrecognizable. The present application thus places the dummy die at the location of its second column of dies from the edges at both of its two long sides (as shown in fig. 3, 4). In this way, the possibility that the distances between two first fine alignment target marks 202 or between two second fine alignment target marks 203 are too close to each other is avoided as much as possible, and the risk of pattern ambiguity due to overlapping with an adjacent die exposure field or optical alignment field is reduced.
And a certain distance is reserved between any two adjacent dies 201 to form a scribing channel with a certain width. The die 201 is formed by dicing the wafer semiconductor product along the dicing streets. The first fine alignment target mark 202 or the second fine alignment target mark 203 is disposed in a region corresponding to the dummy die, and a width of the first fine alignment target mark 202 or the second fine alignment target mark 203 is greater than a pitch (i.e., a width of a scribe lane) between two adjacent columns or rows of dies.
Since the first fine alignment target mark 202 or the second fine alignment target mark 203 occupies a larger space than the width of the scribe lane that can be minimized, one or two dummy dies 13 are reserved exclusively, no die is disposed at the dummy die 13, the first fine alignment target mark 202 or the second fine alignment target mark 203 is disposed exclusively, that is, the first fine alignment target mark 202 or the second fine alignment target mark 203 is not disposed on the scribe lane between two adjacent columns or rows of dies 201, the first fine alignment target mark 202 or the second fine alignment target mark 203 is disposed at the dummy die 13 in a concentrated manner, the width of the scribe lane at which the first fine alignment target mark 202 or the second fine alignment target mark 203 is disposed is further reduced with respect to a scheme in which the first fine alignment target mark 202 or the second fine alignment target mark 203 is disposed within the scribe lane, the first fine alignment target mark 202 or the second fine alignment target mark 203 is not required to be arranged at other positions of the wafer semiconductor product, so that the layout area of the effective die 201 can be increased, and the effective layout area and the number of the effective dies 201 on the wafer semiconductor product can be enlarged.
The first fine alignment target mark 202 or the second fine alignment target mark 203 may be both disposed in the region of the dummy die 13, i.e., the distance between the first fine alignment target mark 202 or the second fine alignment target mark 203 and the adjacent die may be greater than the pitch between the adjacent two columns or rows of dies, such as 60-300 microns. Of course, the first fine alignment target mark 202 or the second fine alignment target mark 203 may also extend beyond the area of the virtual die 13, and the extended portion is disposed in the scribe lane between the virtual die 13 and the adjacent die, which does not affect the layout of the first fine alignment target mark 202 or the second fine alignment target mark 203, and does not affect the layout of the normal effective die, and further, as many first fine alignment target marks 202 or second fine alignment target marks 203 as possible can be placed, so that the space is more effectively utilized.
And because the dummy die 13 is arranged, the first fine alignment target mark 202 or the second fine alignment target mark 203 does not need to occupy the distance between the dies, the distance between the dies at the edge of the optical alignment field and the adjacent die exposure field can be further reduced, and the distance between the die at the extreme edge of the optical alignment field and the die at the extreme edge of the die exposure field can be below 200 micrometers, even 50 micrometers-120 micrometers.
Correspondingly, the distance between the optical alignment target mark exposure pattern in the first mask and the adjacent die exposure pattern is 50 micrometers-120 micrometers, and the distance between the fine alignment target mark and the adjacent die is 60 micrometers-300 micrometers.
More than two first fine alignment target marks 202 or second fine alignment target marks 203 may be provided in one dummy die 13. As in both fig. 3 and 4, two dummy dies 13 are provided, and 3 first fine alignment target marks 202 or second fine alignment target marks 203(AK marks) are provided in each dummy die 13. At least one of the at least 2 first fine alignment target marks 202 or second fine alignment target marks 203 is a convex mark, and at least one is a concave mark. According to the wafer semiconductor product, the first fine alignment target marks 202 in the virtual die 13 are set to be at least one convex mark and at least one groove mark, so that the problem that multiple times of photoetching possibly have different influence degrees on the convex mark and the groove mark, for example, the convex mark is obviously influenced and is not easy to capture and observe, the influence of the groove mark is small, normal identification can be realized, and higher alignment success probability is facilitated is avoided.
Of course, more first fine alignment target marks 202 or second fine alignment target marks 203(AK marks) may be disposed in the dummy die 13 on each side. As a specific embodiment, even the area corresponding to the virtual die 13 may be covered with the first fine alignment target mark 202 or the second fine alignment target mark 203 which are uniformly distributed, that is, in one virtual die 13, on the premise that the safety distance between the adjacent first fine alignment target mark 202 and/or second fine alignment target mark 203 is satisfied, the first fine alignment target mark 202 or second fine alignment target mark 203 may be set next to each other to the maximum extent. Even if one dummy die 13 has insufficient space, two or more adjacent dummy dies 13 may be occupied, and as many first fine alignment target marks 202 or second fine alignment target marks 203 may be laid out as necessary.
Of course, the wafer semiconductor product may not be provided with a dummy die, and the first fine alignment target mark 202 or the second fine alignment target mark 203 in the optical alignment field and the die exposure field may not be provided in the dummy die but directly provided in a widened "scribe lane". As shown in fig. 5 and 6, the scribe lane includes a plurality of first scribe lanes 301 and second scribe lanes 302; the first scribing channel 301 is formed between two adjacent rows of dies 201, and the second scribing channel 302 is formed between two adjacent columns of dies 201; the width of the fine alignment target mark 202 is greater than the width of the first and second scribe streets 301 and 302. The scribe lanes further include at least one alignment mark scribe lane 303, and the alignment mark scribe lane 303 may be disposed only one to two, and only between two rows or two columns of adjacent dies 201. The second fine alignment target mark 203 in the die exposure field 20 is not disposed in the first scribe lane 301 or the second scribe lane 302 but is disposed only in the alignment mark scribe lane 303. The width of the alignment mark scribe lane 303 (e.g., 200um) is larger than the width of the first scribe lane 301 and/or the second scribe lane 302 (e.g., 60 um).
In an implementation, the position of the optical alignment field 10(OAT field) may be set at any position on the wafer semiconductor product, for example, the position may be set at the upper left corner or the center position or the edge position of the wafer semiconductor product. The optical alignment field of the wafer semiconductor product of the present invention may be located in the central region of the wafer semiconductor product, which is the complete field as shown in fig. 1 and 2; the central region of the wafer semiconductor product is located in the geometric central position region, that is, the center position of the circular wafer semiconductor product and the peripheral position adjacent to the center position. For example, the wafer semiconductor products are divided into 16 parts according to the wafer diameter and arranged in four rows and four columns (4 × 4) at equal intervals, and then the wafer semiconductor products are located in a rectangular area from the second row to the third row, namely, the rectangular area is regarded as the central area of the wafer semiconductor products. Still further preferably, referring to fig. 1, the optical alignment field 10(OAT field) is located at a center position of the wafer semiconductor product, i.e. the center position of the wafer semiconductor product is located within said optical alignment field 10(OAT field). Because the manufacturing conditions such as the flatness of the edge area of the wafer semiconductor product are not as good as the manufacturing conditions of the central area of the wafer semiconductor product, the quality of the die manufactured in the edge area of the wafer semiconductor product is relatively better than that in the central area of the die. The optical alignment field 10(OAT field) is set to be a complete field completely located in the central region of the wafer semiconductor product, so that the optical alignment field 10(OAT field) can be set in a better condition region, the exposure and alignment effects are better, and the probability of alignment error is reduced as much as possible. The central region also enables the fabrication of better quality dies, and therefore the dies are also disposed in a second region of the OAT field disposed in the central region, which not only results in a higher recognition rate of the OAT mark of the optical alignment field 10; nor does it waste too much area on which good die can be placed by locating the OAT mark in the central region.
Of course the optical alignment field may also be a partial field as shown in figure 7. The wafer semiconductor product may include a plurality of optical alignment fields 10, for example, in fig. 7, there are 4 optical alignment fields 10, and all of the optical alignment fields 10 are located at the edge of the wafer semiconductor product, and a portion of the optical alignment fields 10(OAT field) is located on the wafer semiconductor product, and another portion of the optical alignment fields (OAT field) is exposed out of the wafer semiconductor product, and cannot leave patterns on the wafer semiconductor product, and are incomplete fields. Under the same area, the die exposure field can produce more dies than the optical alignment field, and the production conditions such as the flatness of the edge area of the wafer semiconductor product are not as good as the production conditions of the central area of the wafer semiconductor product, so that the quality of the die produced in the edge area of the wafer semiconductor product relative to the central area of the die is relatively better. The optical alignment target mark has lower requirements on optical performance than the die, and the optical alignment target mark exposed under the same conditions can be normally recognized, but the exposed die can not meet the requirements on device characteristics. Thus, positioning the optical alignment fields at the location of the incomplete fields at the edge of the wafer semiconductor product allows more die exposure fields to be placed in more conditioned areas, thereby increasing the layout area and number of higher quality dies, improving the average quality of the dies, and reducing costs. In the OAT field of the incomplete field, a second area except the OAT mark may be left for arranging the dies, and the number of the arranged dies of the wafer semiconductor product can be further increased by additionally arranging the dies in the OAT field of the incomplete field.
And more than two optical alignment fields are arranged, so that the probability that the OAT mark cannot be successfully identified due to the optical alignment fields arranged at the incomplete field at the edge is reduced, and even if the OAT mark in one OAT field cannot be normally identified, the OAT mark in the other OAT field can be exchanged for identification and alignment. Although the conditions at the edge locations are worse, they can be compensated for with more OAT marks, reducing waste.
Of course, the optical alignment field 10 is not set too much, and may not exceed 4. As shown in fig. 7, there are 4 optical alignment fields 10, and all of the 4 optical alignment fields 10 are incomplete fields and are respectively disposed in the upper left corner, the lower left corner, the upper right corner and the lower right corner of the wafer semiconductor product in an axisymmetric manner. The 4 optical alignment fields 10 are independently spaced apart, at least 1 at the left lower edge of the wafer semiconductor product, at least 1 at the left upper edge of the wafer semiconductor product, at least 1 at the right lower edge of the wafer semiconductor product, and at least 1 at the right upper edge of the wafer semiconductor product. The optical alignment target mark 101 is disposed at an angular position of the optical alignment field 10 on the wafer semiconductor product, and the optical alignment target mark 101 is disposed adjacent to the angular position. The four OAT fields are symmetrically arranged about the central axis of the wafer semiconductor product, the number of the OAT fields is large, and the distances between the four OAT fields are as far as possible, so that the distance between the optical alignment fields 10 (the OAT fields) can be ensured to be as far as possible, the interaction influence can be reduced as far as possible, and the phenomenon that the optical alignment target marks 101 of two optical alignment fields are too close to each other to interfere with each other, so that if one optical alignment target mark 101 is not clear and cannot be aligned, the other optical alignment target mark is not clear and cannot be aligned can be avoided.
Moreover, the OAT fields arranged at the four angular positions ensure that in case that the wafer semiconductor product is deviated due to inaccurate alignment of the photoetching machine during exposure, no matter which direction the photoetching machine deviates during exposure, a part of OAT marks fall outside the wafer semiconductor product, and at least one of the OAT marks at the other three corners can fall on the wafer semiconductor product, thereby ensuring the reliability of OAT alignment.
Of course, only two optical alignment target marks 101 may be disposed in one optical alignment field of the incomplete field, as shown in fig. 7, the optical alignment field 10 has a rectangular shape, only one corner or two corners of the rectangular optical alignment field 10 located in the incomplete field are disposed on the wafer semiconductor product, the rectangular optical alignment field 10 is disposed at an edge position of the wafer semiconductor product, and the other three corners or two corners thereof are exposed from the wafer semiconductor product, and the optical alignment target marks 101 are disposed at the corner positions. Typically, the optical alignment target mark 101 is disposed adjacent to the angular position.
Correspondingly, four OAT marks (as shown in fig. 8) may be provided in one optical alignment field 10(OAT field), and the four OAT marks are respectively located at four angular positions of the optical alignment field 10(OAT field). Thus, the patterns of the masks corresponding to the OAT fields at the four angular positions can be the same, and the four optical alignment fields can share one first mask. The method comprises the steps of carrying out first blind exposure on the OAT field at four corresponding angular positions of a wafer semiconductor product, enabling the OAT mark to be formed on the OAT field, facilitating subsequent OAT alignment, using the same first mask plate, aligning the four optical alignment fields by the same mask plate, and not needing to replace different first mask plates, so that the cost of the mask plates is saved, and the process time is also saved.
Of course, it is also possible to directly use a reticle having the same pattern of optical alignment fields of the two patterns of optical alignment target marks 101. Even the optical alignment field 10(OAT field) can set not only 2 or 4 OAT MARKs but also the number and positions of the OAT MARKs flexibly as needed. As shown in fig. 9, the number of OAT marks is only 1, and is set in the central region of an OAT field. The central region is an OAT field geometric central position region, i.e. the central position of the wafer semiconductor product in a rectangular shape and the peripheral position adjacent to the central position. For example, the wafer semiconductor products are divided into four equal-distance parts according to the length and the width, and arranged in four rows and four columns (4 × 4), and then located in a rectangular region from the second row to the third row, i.e., the rectangular region is regarded as the central region. Furthermore, the OAT MARK can directly cover the central position of the optical alignment field 10, i.e. the central position of the optical alignment field 10 is located within the OAT MARK, and the optical performance is optimal at this position, so that the probability of identifying the optical alignment target MARK 101(OAT MARK) can be greatly improved, the alignment effect is optimal, and the probability of identification error is further reduced.
Of course, the optical alignment target MARK 101(OAT MARK) may be disposed at the upper part of the rectangular region, two groups of AK MARKs are disposed at the two ends of the first row of dies, and the OAT MARK is disposed at the midpoint of the top, as shown in fig. 10. Alternatively, the OAT MARK is disposed at one of the other two angular positions where the AK MARK is not disposed, as shown in fig. 11, to avoid interfering with the AK MARK, and the middle position of the OAT field may be left for disposing the die 100, so as to avoid the problem that the quality of the die 10 formed by exposing the lower left corner and the lower right corner of the OAT field is poor due to the deformation of the optical lens.
Of course, the number of the OAT marks may also be 2, and the OAT marks are respectively arranged at the central line positions of two AK marks, and each OAT mark is equidistant from two groups of AK marks, as shown in fig. 12. Even more OAT MARKs may be provided in the optical alignment field 10(OAT field), as shown in fig. 13, and the OAT MARKs may be 3, respectively provided in two angular positions on the same side of the OAT field and in a central region on the opposite side. Even two optical alignment target marks 101 can be arranged, but the two optical alignment target marks are respectively arranged at two angular positions of the diagonal line of the OAT field, so that the distance between the at least two optical alignment target marks 101 in the optical alignment field 10(OAT field) can be ensured to be as far as possible, the interaction influence between the two optical alignment target marks can be reduced as far as possible, and the situation that the two optical alignment target marks 101 are too close to each other to interfere with each other, so that if one optical alignment target mark 101 is not aligned clearly, the other optical alignment target mark is also aligned poorly can be avoided. The dies can be arranged in all the rest positions in the OAT field as far as possible, so that the layout area of the dies is increased as far as possible, and the waste of the layout area of the dies is reduced.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made in the above embodiments by those of ordinary skill in the art without departing from the principle and spirit of the present invention.
Claims (10)
1. A wafer semiconductor product, comprising:
the optical alignment field is formed by exposure of a first mask; and
a plurality of tube core exposure fields which are arranged on the wafer semiconductor product in a dot matrix manner except for the optical alignment field and are formed by sequentially exposing a second mask;
wherein the optical alignment field comprises:
at least one optical alignment target mark, at least one first fine alignment target mark, and a plurality of dies, wherein the optical alignment target mark, the first fine alignment target mark, and the plurality of dies are arranged in a non-overlapping manner;
wherein, the alignment precision of the optical alignment target mark is lower than that of the fine alignment target mark, and the distance between the die and the optical alignment target mark is not less than a preset safety distance.
2. The wafer semiconductor product according to claim 1, wherein the predetermined safety distance is not less than 50 μm; the distance between the optical alignment target mark and the adjacent die is 50-120 microns.
3. The wafer semiconductor product according to claim 1, wherein the optical alignment field is divided into a first region and a second region other than the first region; the optical alignment target mark is arranged in the first area; the first fine alignment target mark and the plurality of dies are disposed in the second area, and the dies are arranged in a matrix in the second area.
4. The wafer semiconductor product of claim 3, wherein the second area further comprises at least one dummy die, the dummy die being the same size as the dies in the second area, the dummy die being arranged in a matrix with the plurality of dies in the second area, the spacing between two adjacent columns or rows of dies being equal;
and no die is arranged at the virtual die, the first fine alignment target mark is arranged in the area corresponding to the virtual die, and the width of the first fine alignment target mark is larger than the distance between two adjacent columns or two rows of the dies.
5. The wafer semiconductor product according to claim 4, wherein two or more of the first fine alignment target marks are provided in the one dummy die, at least one of the at least two first fine alignment target marks being a bump mark and at least one being a groove mark.
6. The wafer semiconductor product of claim 1, in which a distance between the first fine alignment target mark and the adjacent die is 50-300 microns.
7. The wafer semiconductor product of claim 1, wherein each of the die exposure fields comprises:
a plurality of die arranged in a matrix; and
a second fine alignment target mark;
the die and the second fine alignment target mark are arranged in a non-overlapping mode, and the distance between the die at the extreme edge of the optical alignment field and the die at the extreme edge of the die exposure field is 50-120 micrometers.
8. The wafer semiconductor product of claim 1, wherein the optical alignment field is a full field, the optical alignment field being a rectangular area; the optical alignment field includes at least two optical alignment target marks disposed at two short side positions near the optical alignment field, respectively.
9. A reticle for use in the fabrication of a wafer semiconductor product according to any one of claims 1 to 8, the reticle comprising:
an optical alignment target mark exposure pattern for exposing an optical alignment target mark of an optical alignment field formed on a wafer semiconductor product;
a first fine alignment target mark exposure pattern for exposing a first fine alignment target mark of an optical alignment field formed on a wafer semiconductor product;
and a plurality of die exposure patterns for exposing a plurality of dies of an optical alignment field formed on the wafer semiconductor product;
wherein the optical alignment target mark exposure pattern, the first fine alignment target mark exposure pattern, and the plurality of die exposure patterns are arranged in a non-overlapping manner; the alignment precision of the optical alignment target mark pattern is lower than that of the first fine alignment target mark pattern; the distance between the die exposure pattern and the optical alignment target mark exposure pattern is not less than a preset safety distance.
10. A lithography machine, comprising:
the reticle of claim 9 as a first reticle for forming an optical alignment field of a wafer semiconductor product;
the second mask is used for forming a die exposure field of the wafer semiconductor product;
the alignment correction system is used for carrying out alignment correction according to the first mask or the second mask; and
and the exposure system is used for carrying out exposure by using the first mask or the second mask.
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