CN115291484A - Photoetching registration method and chip manufacturing method - Google Patents

Photoetching registration method and chip manufacturing method Download PDF

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Publication number
CN115291484A
CN115291484A CN202210976828.5A CN202210976828A CN115291484A CN 115291484 A CN115291484 A CN 115291484A CN 202210976828 A CN202210976828 A CN 202210976828A CN 115291484 A CN115291484 A CN 115291484A
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China
Prior art keywords
wafer
photoetching
registration
reticle
alignment mark
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Pending
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CN202210976828.5A
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Chinese (zh)
Inventor
李京兵
石晓宇
王国峰
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Beihai Huike Semiconductor Technology Co Ltd
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Beihai Huike Semiconductor Technology Co Ltd
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Priority to CN202210976828.5A priority Critical patent/CN115291484A/en
Publication of CN115291484A publication Critical patent/CN115291484A/en
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7003—Alignment type or strategy, e.g. leveling, global alignment
    • G03F9/7046—Strategy, e.g. mark, sensor or wavelength selection
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/682—Mask-wafer alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

Abstract

The application is suitable for the technical field of chip manufacturing, and provides a photoetching registration method, which comprises the following steps: the wafer is placed on a carrying platform of a photoetching machine, a photoetching plate is placed on a carrying disc of the photoetching machine, the wafer comprises a plurality of exposure areas, a first alignment mark is arranged in each exposure area, and a registration mark is arranged on the photoetching plate; roughly aligning the photoetching plate with the wafer; moving the reticle to finely align the registration marks with the first alignment marks; and moving the photoetching plate by a first preset distance, wherein the first alignment mark and the registration mark are staggered, so that photoetching is carried out on the wafer by utilizing the photoetching plate. The photoetching registration method can realize the registration of the multilayer pattern layers, save chips occupied by the marks and improve the production quantity of the chips. The application also provides a chip manufacturing method.

Description

Photoetching registration method and chip manufacturing method
Technical Field
The present disclosure relates to the field of chip manufacturing technologies, and in particular, to a photolithography alignment method and a chip manufacturing method.
Background
A photolithography machine (lithography) is a core equipment for manufacturing a chip, and prints a fine pattern on a reticle onto the chip by exposure of light. Because the chip needs to make multilayer film layers in the manufacturing process, and for part of photoetching machines, the mark can be identified only by transmitting information through the reflected wave, and then the registration between layers is realized.
At present, the existing photoetching machine for identifying the mark by using the reflected wave seriously depends on the shape and the size of the mark, the shape and the size of the mark need to meet the requirements of the photoetching machine on transverse and vertical scanning, and the mark cannot be reused. For large-size chips, the scanning range of the lithography machine is limited, the required marks can be placed in insufficient positions within the scanning range, two chips have to be sacrificed in each exposure area (block) to set alignment marks, and the loss rate of the chips is increased.
Disclosure of Invention
In view of this, the present application provides a photolithography alignment method and a chip manufacturing method to save chips occupied by marks, reduce the loss rate of chips, and improve the throughput.
Embodiments of a first aspect of the present application provide a lithographic registration method, including:
placing a wafer on a carrying platform of a photoetching machine, and placing a photoetching plate on a carrying disc of the photoetching machine, wherein the wafer comprises a plurality of exposure areas, a first alignment mark is arranged in each exposure area, and a registration mark is arranged on the photoetching plate;
roughly aligning the photoetching plate with the wafer;
moving the reticle to fine align the registration marks with the first alignment marks;
moving the photoetching plate by a first preset distance, wherein the first alignment mark and the registration mark are staggered so as to carry out photoetching on the wafer by using the photoetching plate;
each exposure area is also internally provided with a plurality of tube cores arranged in an array, a plurality of first scribing channels and a plurality of second scribing channels, the first scribing channels are arranged between two adjacent rows of the tube cores, the second scribing channels are arranged between two adjacent columns of the tube cores, the first counterpoint mark is arranged at the intersection point of the first scribing channels and the second scribing channels, the number of layers of the pattern layer to be formed by the tube cores is N, N is a positive integer greater than 0, the photoetching machine is used for identifying the first counterpoint mark through reflected waves, the photoetching machine is provided with an identifiable area, the number of the intersection points of the first scribing channels and the second scribing channels in the identifiable area is M, M is a positive integer greater than 0, and M and N meet the following conditions: m is less than 2N.
In some embodiments, the alignment mark is shifted by a second preset distance from an original design position, where the original design position is a projection position of the first alignment mark on the reticle when the wafer is aligned with the edge of the reticle and in an alignment state, and the second preset distance is equal to the first preset distance.
In some embodiments, the step of moving the reticle by a first preset distance includes: and moving the photoetching plate by the first preset distance along a first direction, wherein the first direction is the row direction and the column direction of the tube core arrangement or the diagonal direction of the tube core.
In some embodiments, let the length of the die in the row direction be L1, the length in the column direction be L2, and the length in the diagonal direction of the die be L3; setting the width of the first scribing channel as W1, the width of the second scribing channel as W2, the length of a diagonal line at the intersection of the first scribing channel and the second scribing channel as W3, and setting the first preset distance as D;
when the first direction is a row direction, D = P1 × (L1 + W2);
when the first direction is a column direction, D = P2 × (L2 + W1);
when the first direction is a diagonal direction of the die, D = P3 (L3 + W3), P1, P2, P3 are all positive integers greater than 0.
In some embodiments, each of the exposure regions further has a second alignment mark, and after the step of roughly aligning the reticle with the wafer, the photolithography alignment method further includes:
determining whether the first alignment mark can be identified;
when the first alignment mark is not recognizable, the reticle is moved to finely align the registration mark with the second alignment mark.
In some embodiments, when N > 5, each of the exposure regions further has a second alignment mark, and after the step of roughly aligning the reticle with the wafer, the photolithography alignment method further includes:
judging whether the number of the photoetching pattern layers on the tube core is greater than Q, wherein Q is a positive integer which is greater than 1 and less than N;
and when the number of the photoetched pattern layers on the tube core is more than Q, moving the photoetching plate to finely align the registration mark with the second alignment mark.
In some embodiments, the exposed region has a length of 30000um and a width of 14900um; the length of the tube core in the row direction or the column direction is 1500 um-6000 um.
In some embodiments, the reticle is used in any one of a plurality of photolithography processes in a semiconductor manufacturing process of a chip, and the plurality of photolithography processes use the first alignment mark to align the corresponding reticle with the wafer.
A second aspect of the present application provides a chip manufacturing method, including:
aligning the wafer with the photolithography mask by using the photolithography alignment method of the first aspect;
photoetching the wafer by using the photoetching plate to form a pattern layer;
and repeating the steps of alignment and photoetching, aligning the plurality of photoetching plates with the wafer in sequence and forming a plurality of pattern layers on the wafer in sequence.
In some embodiments, a photoresist layer is disposed on the wafer, and the performing photolithography on the wafer by using the reticle includes:
exposing the photoresist layer on the wafer by using the photoetching plate;
etching the wafer by taking the exposed photoresist layer as a mask to obtain a pattern layer on the wafer, wherein the first alignment mark is not etched;
and removing the photoresist layer.
In the photoetching registration method, a photoetching plate and a wafer are roughly aligned, then a first alignment mark and a registration mark are finely aligned, then the photoetching plate is moved by a first preset distance to enable the photoetching plate to move to a preset exposure position, and further the photoetching plate is used for photoetching the wafer, at the moment, the registration mark and the first alignment mark are arranged in a staggered mode, the wafer position corresponding to the registration mark is exposed and etched, and the first alignment mark is not etched, so that the first alignment mark can be repeatedly applied to multiple times of registration and photoetching processes. The photoetching registration method provided by the application realizes registration and exposure at different positions, can repeatedly utilize the first alignment mark on the wafer to realize registration between layers, does not need to make marks on each layer of film, saves the tube core occupied by the marks, reduces the loss rate of chips and improves the production capacity.
In the chip manufacturing method provided by the application, the alignment is realized by adopting a photoetching alignment method, then photoetching is carried out, a pattern layer is formed, and the steps of alignment and photoetching can be repeated to form a plurality of pattern layers. Because the first alignment mark is adopted in the multiple registration processes, the layers are aligned; in addition, the first alignment mark can be repeatedly used, a new alignment mark formed on the wafer during each photoetching is not needed, so that a tube core occupied by the mark is saved, the loss rate of a chip is reduced, and the production capacity is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a flow chart of a lithographic registration method provided herein;
fig. 2 is a schematic view of a wafer according to an embodiment of the present disclosure;
FIG. 3 is a schematic view of an exposure area in a wafer according to an embodiment of the present disclosure;
FIG. 4 is a schematic illustration of a process of photolithography registration provided by an embodiment of the present application;
FIG. 5 is a schematic view of an exposure area in a wafer according to another embodiment of the present application;
fig. 6 is a flowchart of a chip manufacturing method according to an embodiment of the present application.
The designations in the figures mean:
10. a wafer; 101. an exposure area; 11. a die; 121. a first scribe lane; 122. a second scribe lane; 13. a first alignment mark; 14. a second alignment mark; 21. and (6) registering the marks.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly or indirectly secured to the other element. When an element is referred to as being "connected to" another element, it can be directly or indirectly connected to the other element. The terms "first", "second" and "first" are used merely for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features. The meaning of "plurality" is two or more unless specifically limited otherwise.
It should be noted that, in the embodiments of the present application, the same reference numerals are used to refer to the same components or parts, and for the same parts in the embodiments of the present application, only one of the components or parts may be used as an example to refer to the reference numeral, and it should be understood that, for other similar components or parts, the reference numerals are also used.
In order to explain the technical solution of the present application, the following description is made with reference to the specific drawings and examples.
Embodiments of the first aspect of the present disclosure provide a lithography registration method, which can align a wafer 10 to be lithographed with a reticle 20 on a lithography machine, so as to achieve registration between patterns on each layer of the wafer 10. As shown in fig. 1, the photolithography registration method includes the following steps.
Step S110: the wafer 10 is placed on a stage of a lithography machine, and the reticle 20 is placed on a carrier plate of the lithography machine.
Referring to fig. 2 to 4, the wafer 10 is used for manufacturing a plurality of chips. The wafer 10 includes a plurality of exposure regions 101, and each exposure region 101 has a first alignment mark 13 disposed therein.
Each exposure area 101 is further provided with a plurality of die 11 arranged in an array, a plurality of first scribe lanes 121 and a plurality of second scribe lanes 122, the first scribe lanes 121 are disposed between two adjacent rows of die 11, the second scribe lanes 122 are disposed between two adjacent columns of die 11, and the first alignment mark 13 is disposed at an intersection of the first scribe lanes 121 and the second scribe lanes 122. In order to meet the requirement of the lateral and vertical scanning of the lithography machine, the first contrast mark 11 includes a portion extending along the X direction and a portion extending along the Y direction, for example, the first contrast mark 11 is cross-shaped.
The number of layers of the die 11 to be patterned is N, where N is a positive integer greater than 0. The photoetching machine is used for identifying the first alignment mark 13 through reflected waves, and the photoetching machine is provided with an identifiable region, the number of intersection points of the first scribing channel 121 and the second scribing channel 122 in the identifiable region is M, M is a positive integer greater than 0, and M and N satisfy the following conditions: m is less than 2N.
Specifically, since the lithography machine has a requirement on the size of the first alignment mark 13, the first alignment mark needs to be placed at the intersection of the first scribe lane 121 and the second scribe lane 122.
An optical scanning mechanism in the photoetching machine scans the left side and the right side of the exposure area 101 at the same time, and the recognizable area of the photoetching machine is divided into a first sub-area and a second sub-area which respectively scan the left side and the right side of the exposure area 101; the left and right sides of each exposure area 101 are respectively provided with a first alignment mark 11 for the photolithography machine to identify simultaneously. For example, N =5,m =8, the above condition M < 2N is satisfied.
When the above conditions are met, if the existing alignment method is adopted, 2N alignment marks need to be set in the exposure area 101, however, only M positions in the recognizable area of the lithography machine can be set with alignment marks, and therefore, the die 11 needs to be additionally occupied to place the remaining alignment marks, whereas the method provided by the present application does not need to set alignment marks on the die 11.
Referring to fig. 4, the reticle 20 is a photomask (MASK), and the reticle 20 may be a reticle 20 used in any one of a plurality of photolithography processes in the semiconductor manufacturing process of the wafer 10, and has a pattern thereon. The reticle 20 is provided with a registration mark 21, and the registration mark 21 is used for aligning with the first alignment mark 13. The photolithography mask 20 is placed on a carrying plate, and the carrying plate can drive the photolithography mask 20 to move so as to complete the subsequent alignment action.
Step S120: the reticle 20 is coarsely aligned with the wafer 10.
Referring to fig. 4, (a) in fig. 4 is a schematic diagram of the rough alignment between the reticle 20 and the wafer 10. Coarse alignment is achieved by widely moving the reticle 20 such that the reticle 20 is moved above the wafer 10. After the rough alignment, the first alignment mark 13 is offset from the registration mark 21, and the two are not overlapped or have a small overlapping ratio.
The present application is not limited to the specific means of coarse alignment, for example, the reticle 20 may be roughly aligned with respect to the wafer 10, or the reticle 20 may be roughly aligned with respect to the lithography machine. After the coarse alignment, the reticle 20 is brought close to the predetermined exposure position.
Step S130: reticle 20 is moved to fine align registration marks 21 with first registration marks 13.
Specifically, referring to fig. 4 (b), the carrier drives the reticle 20 to move until the registration mark 21 on the reticle 20 is precisely aligned with the first alignment mark 13 on the wafer 10, so as to achieve precise alignment between the reticle 20 and the wafer 10. During fine alignment, the projection of the registration mark on the wafer 10 completely overlaps the first alignment mark 13. When the registration mark 21 and the first alignment mark 13 are plural, each registration mark 21 is finely aligned with the corresponding first alignment mark 13. It will be appreciated that the boat may be moved relative to the lithographic apparatus using a mechanical adjustment system on the lithographic apparatus.
Step S140: the reticle 20 is moved a first predetermined distance, and the first alignment mark 13 is offset from the registration mark 21, so as to perform photolithography on the wafer 10 by using the reticle 20.
Referring to fig. 4 (c), after the precise alignment, the reticle 20 is moved by a first predetermined distance to stagger the alignment mark 21 and the corresponding first alignment mark 13 without overlapping, and then the wafer 10 is etched by using the moved reticle 20. "photolithography" includes processes such as exposure and etching, and can form a pattern layer on the wafer 10, which is the same as the lithographic pattern on the reticle 20.
When the wafer 10 is photo-etched by using the reticle 20, since the alignment mark on the reticle 20 is offset from the first alignment mark 13, the first alignment mark 13 is not etched, so that the first alignment mark 13 can remain on the wafer 10 for alignment of the next layer. When the next alignment is performed on the wafer 10, the above steps S110 to S140 are repeated and the first alignment mark 13 is used for alignment. Thus, the first alignment mark 13 can be reused.
In the photolithography registration method provided by the application, firstly, the reticle 20 and the wafer 10 are roughly aligned, then the first registration mark 13 and the registration mark 21 are finely aligned, then, the reticle 20 is moved by a first preset distance, the reticle 20 is moved to a preset exposure position, and then the wafer 10 is subjected to photolithography by using the reticle 20, at this time, the registration mark 21 and the first registration mark 13 are arranged in a staggered manner, the position of the wafer 10 corresponding to the registration mark 21 is exposed and etched, and the first registration mark 13 is not etched, so that the first registration mark 13 can be repeatedly applied to a plurality of times of registration and photolithography processes. The photoetching registration method provided by the application realizes registration and exposure at different positions, can repeatedly utilize the first alignment mark on the wafer 10 to realize registration between layers, does not need to make marks on each layer of film, saves the tube cores occupied by the marks, reduces the loss rate of chips and improves the production capacity.
The photoetching registration method can be used for chip manufacturing process, and can obviously reduce the loss rate of chips for large-size chips. For a product with a size of 138mil as an example, 24 dies can be arranged in one exposure area 101, in the prior art, 2 chips need to be occupied by alignment marks, and the chip loss rate is 8.3%; by adopting the method provided by the application, the tube core occupied by the alignment mark is saved, and the waste amount can be saved by 8.3%.
Taking fig. 3 as an example, the length of the exposure region 101 is 30000um, the width is 14000um, and the length of the die 11 is 3500um, n =6, m = 6. A total of 24 dies 11 are disposed in the exposure area 101, 6 pattern layers need to be formed on the dies 11, and 6 photolithography processes are required.
If the prior art is adopted, in the left 4 rows of dies 11 in fig. 3, the intersections of the three first scribe lanes 121 and the three second scribe lanes 122 are located in the scannable region of the lithography machine, and in the right 4 rows of dies 11, the intersections of the three first scribe lanes 121 and the three second scribe lanes 122 are located in the scannable region of the lithography machine, so that only 3 alignment marks can be placed on both the left and right sides of the exposure region, which can be used for 3 lithography processes, and therefore, the left and right sides respectively occupy one die 11 to place the alignment marks required in the remaining 3 lithography processes.
By adopting the technical scheme provided by the application, the alignment requirements in 6 photo-etching processes can be met only by respectively placing 1 first alignment mark 13 on the left side and the right side, and compared with the prior art, the embodiment reduces the waste amount by 8.3% by taking fig. 3 as an example.
It will be appreciated that the size of the die 11, and the number of dies 11 within the exposure area, may be adjusted according to design requirements.
In one embodiment, the alignment mark 21 is offset from the original design position, which is the projection position of the first alignment mark 13 on the reticle 20 when the wafer 10 is aligned with the edge of the reticle 20 and in the alignment state, by a second predetermined distance, which is equal to the first predetermined distance. It can be seen that the moving distance of the reticle 20 in step S140 is preset to be equal to the offset distance of the registration marks 21.
It will be appreciated that the reticle 20 has a predetermined lithographic pattern (layout) to be lithographically patterned onto the wafer 10, and the registration marks 21 are positioned differently with respect to the lithographic pattern than the first alignment marks 13. After exposure and etching, a lithographic pattern on the reticle 20 may be formed on the wafer 10.
By adopting the above technical solution, the registration mark 21 has an offset distance (second preset distance) with respect to the original design position and the first alignment mark 13, and after the fine alignment is implemented in step S130, the reticle 20 is moved by the same distance (first preset distance), so that the lithographic pattern on the reticle 20 can be formed on the wafer 10. Therefore, the moving distance of the reticle 20 in step S140 can be precisely controlled, and the alignment precision is ensured. It can be understood that the first preset distance and the second preset distance can be set according to product requirements.
In one embodiment, the step of moving the reticle 20 by the first predetermined distance includes: the reticle 20 is moved a first predetermined distance in a first direction, which is a row direction, a column direction, or a diagonal direction of the die 11 in which the die 11 is arranged.
By adopting the above technical solution, the reticle 20 can be moved, so that the registration mark 21 of the reticle 20 is offset from the first alignment mark 13, and the exposure position corresponding to the registration mark 21 is still located at the intersection of the first scribe lane 121 and the second scribe lane 122.
In one embodiment, the length of the die 11 along the row direction is L1, the length along the column direction is L2, and the length along the diagonal direction of the die 11 is L3; setting the width of the first scribing way 121 as W1, the width of the second scribing way 122 as W2, the length of a diagonal line at the intersection of the first scribing way 121 and the second scribing way 122 as W3, and setting the first preset distance as D;
when the first direction is a row direction, D = P1 × (L1 + W2);
when the first direction is the column direction, D = P2 × (L2 + W1);
when the first direction is a diagonal direction of the die 11, D = P3 × (L3 + W3), P1, P2, P3 are all positive integers greater than 0.
By adopting the above technical scheme, the moving distance of the photolithography mask 20 can be accurately controlled, and it is ensured that the exposure position corresponding to the registration mark 21 of the photolithography mask 20 is still located at the intersection point of the first scribing street 121 and the second scribing street 122 after the photolithography mask 20 moves.
Referring to FIG. 5, in one embodiment, when N > 5, a second alignment mark 14 is further disposed in each exposure area 101. The second alignment mark 14 is located at the intersection of the first scribe lane 121 and the second scribe lane 122. The second alignment mark 14 may be formed simultaneously with the first alignment mark 13, or may be formed in any step of the wafer 10 that is performed by photolithography using the first alignment mark 13. The second alignment mark 14 may have the same shape as the first alignment mark 13 or a different shape.
A certain photolithography process on the wafer 10 can select the first alignment mark 13 or the second alignment mark 14 for registration; alternatively, the second registration mark 14 is selected to be registered when the sharpness of the first registration mark 13 is degraded.
In one embodiment, after the step of coarsely aligning the reticle 20 with the wafer 10, the photolithography registration method further includes:
determining whether the first alignment mark 13 can be recognized;
when the first alignment mark 13 is not recognized, the reticle 20 is moved to finely align the registration mark 21 with the second alignment mark 14.
By adopting the above technical scheme, the second alignment mark 14 can utilize an empty scribe lane and does not occupy the die 11, and the registration method provided by this embodiment can perform registration by using the second alignment mark 14 when the first alignment mark 13 cannot be identified, and can also solve the problem that the alignment mark needs to occupy the die 11.
In another embodiment, after the step of coarsely aligning the reticle 20 with the wafer 10, the photolithography registration method further includes:
judging whether the number of the photoetching pattern layers on the tube core 11 is greater than Q, wherein Q is a positive integer which is greater than 1 and less than N;
when the number of patterned layers on the die 11 is greater than Q, the reticle 20 is moved to finely align the registration marks 21 with the second alignment marks 14.
For example, N =6,q =4, after rough alignment, it is determined whether the number of patterned layers that have been lithographically patterned on the die 11 is greater than 4; if yes, finely aligning the registration mark 21 with the second alignment mark 14; if not, the process continues to step S130, and the registration mark 21 and the first alignment mark 13 are still finely aligned.
By adopting the above technical solution, the second alignment mark 14 can utilize a spare scribe lane and does not occupy the die 11, and the registration method provided in this embodiment can use the second alignment mark 14 to perform registration after the first alignment mark 13 is used for multiple times, and can also solve the problem that the alignment mark needs to occupy the die 11.
In one embodiment, the length of the exposure region 101 is 30000um and the width is 14900um; the length of the die 11 in the row or column direction is 1500um to 6000um.
Therefore, the method is suitable for large-size chips, the die 11 is not required to be occupied to set the alignment marks, the production quantity of the chips can be obviously improved, and waste is avoided. It will be appreciated that the above-described photolithographic registration method can also avoid occupying the dies 11 for small and medium-sized chips, but the number of dies 11 in the exposure area 101 is smaller for large-sized chips, so that the effect of saving the dies 11 is significant.
In one embodiment, the first alignment mark 13 is a convex pattern or a concave pattern. In the prior art, after alignment and photolithography, the convex pattern or the concave pattern is etched away, but with the method of the present application, the first alignment mark 13 is not etched and can be reused. If the first alignment mark 13 is a bump pattern, after the film is deposited on the first alignment mark 13, the bump pattern is raised because the film is not etched, and the bump pattern is still a bump pattern after the photolithography process; if the first alignment mark 13 is a recessed pattern, such as a groove or a slit, the first alignment mark 13 remains a recessed pattern after the photolithography process after the film is deposited thereon. The first alignment mark 13 is not etched in the photolithography process, so that the first alignment mark 13 can maintain sufficient definition.
In one embodiment, the first alignment mark 13 has a cross shape, and the registration mark 21 is a light-transmitting portion of the cross shape provided on the reticle 20. In fig. 3, four squares on the periphery of the alignment mark 21 are opaque parts, and a cross-shaped transparent part is formed between the four squares.
In the present embodiment, the first alignment mark 13 and the registration mark 21 are arranged in a cross shape, and alignment in the X and Y directions can be achieved at the same time. It is understood that the shapes of the first alignment mark 13 and the registration mark 21 are not limited thereto, for example, the first alignment mark 13 includes a first bar-shaped portion along the X direction and a second bar-shaped portion along the Y direction, and the first bar-shaped portion and the second bar-shaped portion are spaced apart; as another example, the first alignment mark 13 may have a circular shape or a polygonal shape.
The registration mark 21 and the first registration mark 13 may be the same size or different sizes, for example, the registration mark 21 has a cross shape but the length of each branch may be greater than the length of the first registration mark 13.
In the photolithography registration method provided by the present application, the reticle 20 is used in any one of a plurality of photolithography processes in a semiconductor manufacturing process of a chip, and the plurality of photolithography processes all use the first alignment mark 13 to align the reticle 20 with the wafer 10.
Referring to fig. 6, a second aspect of the present application provides a method for manufacturing a chip, including the following steps.
Step S510: the wafer 10 is aligned with the reticle 20 using a lithographic registration method as in the first aspect.
As in the first aspect, after alignment, the exposure position of the reticle 20 avoids the first registration mark 13.
Step S520: photolithography is performed on the wafer 10 using a photolithography mask 20 to form a pattern layer.
After the photolithography, the patterned layer formed on the wafer 10 is the same as the photolithography pattern on the reticle 20, and the first alignment mark 13 is not etched, so as to remain on the wafer 10.
Step S530: the above alignment and photolithography steps are repeated, and a plurality of reticles 20 are sequentially aligned with the wafer 10 and sequentially form a plurality of patterned layers on the wafer 10.
The number of the pattern layers on the wafer 10 can be set according to the requirement, and each pattern layer is aligned by using the first alignment mark 13.
According to the chip manufacturing method, the photoetching registration method is adopted to realize registration, then photoetching is carried out, pattern layers are formed, the steps of registration and photoetching can be repeated to form a plurality of pattern layers, and due to the fact that the first alignment mark 13 is adopted in the multiple registration processes, alignment is realized between layers, the corresponding relation of each pattern layer is ensured, and the registration precision is improved; in addition, the first alignment mark 13 can be reused, and a new alignment mark formed on the wafer 10 during each photolithography process is not needed, so that dies occupied by the mark are saved, the chip loss rate is reduced, and the production capacity is improved.
Optionally, the first alignment mark 13 is disposed in the first film layer on the wafer 10, and when the second and third film layers are manufactured, the alignment between the first alignment mark 11 and the corresponding reticle 20 can be achieved, so that the alignment between the film layers is achieved.
In an embodiment, a photoresist layer is disposed on the wafer 10, and the step S520 of performing photolithography on the wafer 10 by using the reticle 20 includes: exposing the photoresist layer on the wafer by using a photolithography mask 20; etching the wafer 10 by using the exposed photoresist layer as a mask to obtain a pattern layer on the wafer 10, wherein the first alignment mark 13 is not etched; and removing the photoresist layer.
The photoresist layer may be a positive photoresist or a negative photoresist, for example, a positive photoresist covering the surface of the wafer 10; the photoresist layer is exposed by using the photolithography mask 20, the first alignment mark 13 is staggered from the registration mark 21, and the first alignment mark 13 corresponds to a non-light-transmitting portion on the photolithography mask 20, so that the first alignment mark 13 is not exposed, after development, the photoresist on the first alignment mark 13 remains on the wafer 10, and the first alignment mark 13 below is protected during etching, and therefore, the first alignment mark 13 is not etched. The principle of negative photoresists is similar and will not be described in detail.
In one embodiment, in the process of aligning the plurality of reticles 20 with the wafer 10 in sequence, the first predetermined distances moved by the reticles 20 after precise alignment are all equal. The first predetermined distance is equal to a second predetermined distance by which the registration mark 21 is shifted from the original design position. Thus, the chip manufacturing method can accurately control the moving distance of the reticle 20.
In a third aspect of the present application, a chip is provided, which is manufactured by using the chip manufacturing method provided in the second aspect.
The chip manufactured by the chip manufacturing method comprises a plurality of pattern layers, and the layers are aligned, so that the corresponding relation among the plurality of pattern layers is ensured, and the performance is better.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims (10)

1. A method of lithographic registration, comprising:
placing a wafer on a carrying platform of a photoetching machine, and placing a photoetching plate on a carrying disc of the photoetching machine, wherein the wafer comprises a plurality of exposure areas, a first alignment mark is arranged in each exposure area, and a registration mark is arranged on the photoetching plate;
roughly aligning the photoetching plate with the wafer;
moving the reticle to fine align the registration marks with the first alignment marks;
moving the photoetching plate by a first preset distance, wherein the first alignment mark and the registration mark are staggered so as to carry out photoetching on the wafer by using the photoetching plate;
each exposure area is also internally provided with a plurality of tube cores arranged in an array, a plurality of first scribing channels and a plurality of second scribing channels, the first scribing channels are arranged between two adjacent rows of the tube cores, the second scribing channels are arranged between two adjacent columns of the tube cores, the first counterpoint mark is arranged at the intersection point of the first scribing channels and the second scribing channels, the number of layers of the pattern layer to be formed by the tube cores is N, N is a positive integer greater than 0, the photoetching machine is used for identifying the first counterpoint mark through reflected waves, the photoetching machine is provided with an identifiable area, the number of the intersection points of the first scribing channels and the second scribing channels in the identifiable area is M, M is a positive integer greater than 0, and M and N meet the following conditions: m is less than 2N.
2. The lithographic registration method of claim 1, wherein the registration mark is offset from an original design position, which is a projection position of the first alignment mark on the reticle when the wafer is aligned with an edge of the reticle and in an aligned state, by a second predetermined distance, which is equal to the first predetermined distance.
3. The lithographic registration method of claim 1,
in the step of moving the reticle by a first preset distance, the method includes: and moving the photoetching plate by the first preset distance along a first direction, wherein the first direction is the row direction and the column direction of the tube core arrangement or the diagonal direction of the tube core.
4. The lithographic registration method of claim 3, wherein the length of the die in the row direction is L1, the length in the column direction is L2, and the length in the diagonal direction of the die is L3; setting the width of the first scribing channel as W1, the width of the second scribing channel as W2, the length of a diagonal line at the intersection of the first scribing channel and the second scribing channel as W3, and setting the first preset distance as D;
when the first direction is a row direction, D = P1 × (L1 + W2);
when the first direction is a column direction, D = P2 × (L2 + W1);
when the first direction is a diagonal direction of the die, D = P3 (L3 + W3), P1, P2, P3 are all positive integers greater than 0.
5. The photolithography registration method of claim 1, wherein each of the exposure regions further comprises a second alignment mark, and wherein after the step of coarsely aligning the reticle with the wafer, the photolithography registration method further comprises:
determining whether the first alignment mark can be identified;
when the first alignment mark is not recognizable, the reticle is moved to finely align the registration mark with the second alignment mark.
6. The lithographic registration method of claim 1, wherein when N > 5, each of the exposure regions further has a second alignment mark disposed therein, and after the step of coarsely aligning the reticle with the wafer, the lithographic registration method further comprises:
judging whether the number of the photoetched pattern layers on the tube core is greater than Q, wherein Q is a positive integer greater than 1 and less than N;
and when the number of the photoetched pattern layers on the tube core is more than Q, moving the photoetching plate to finely align the registration mark and the second alignment mark.
7. The lithographic registration method of any of claims 1-6, wherein the exposed area has a length of 30000um and a width of 14900um; the length of the tube core in the row direction or the column direction is 1500 um-6000 um.
8. The method of claim 1, wherein the reticle is used in any one of a plurality of photolithography processes in a semiconductor manufacturing process of a chip, and the plurality of photolithography processes use the first alignment mark to align the corresponding reticle with the wafer.
9. A method of fabricating a chip, comprising:
aligning the wafer with the reticle using the lithographic registration method of any one of claims 1-8;
photoetching the wafer by using the photoetching plate to form a pattern layer;
and repeating the steps of aligning and photoetching, aligning the plurality of photoetching plates with the wafer in sequence and forming a plurality of pattern layers on the wafer in sequence.
10. The method for manufacturing a chip according to claim 9, wherein a photoresist layer is formed on the wafer, and the performing the photolithography on the wafer by using the reticle comprises:
exposing the photoresist layer on the wafer by using the photoetching plate;
etching the wafer by taking the exposed photoresist layer as a mask to obtain a pattern layer on the wafer, wherein the first alignment mark is not etched;
and removing the photoresist layer.
CN202210976828.5A 2022-08-15 2022-08-15 Photoetching registration method and chip manufacturing method Pending CN115291484A (en)

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CN202210976828.5A CN115291484A (en) 2022-08-15 2022-08-15 Photoetching registration method and chip manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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