CN113206099B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN113206099B CN113206099B CN202110492158.5A CN202110492158A CN113206099B CN 113206099 B CN113206099 B CN 113206099B CN 202110492158 A CN202110492158 A CN 202110492158A CN 113206099 B CN113206099 B CN 113206099B
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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Abstract
The present invention provides a semiconductor device including: the peripheral circuit chips of the first substrate, the device layer and the first bonding layer are sequentially stacked, the device layer comprises a controller and a plurality of drivers, the second bonding layer, the storage array layer and the storage array chips of the second substrate are sequentially stacked, the storage array layer comprises a plurality of storage arrays corresponding to each driver, the storage array chips are electrically connected with the peripheral circuit chips through the first bonding layer and the second bonding layer, the controller controls the plurality of storage arrays corresponding to the plurality of drivers to perform read-write operation through controlling the plurality of drivers and the first bonding layer and the second bonding layer, and the controller and the plurality of drivers are formed on the same chip, so that the communication speed between the plurality of storage arrays is improved through improving the communication speed between the controller and the plurality of drivers effectively, and meanwhile, the manufacturing cost of the semiconductor device is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
As technology advances, the semiconductor industry continues to seek new ways to produce such that each memory die in a memory device has a greater number of memory cells. In order to further increase the storage density of the memory, a three-dimensional structure of a memory device has been developed, the three-dimensional memory includes a plurality of memory cells stacked in a vertical direction, the integration level can be doubly increased on a wafer per unit area, and the cost can be reduced. Among nonvolatile memories, 3D NAND Flash (three-dimensional NAND Flash) memories having 32 layers, 64 layers, and even higher layers have been designed.
In the prior art, a phase change Memory (PHASE CHANGE Memory, PCM) is generally used as a buffer of the 3D NAND Flash Memory to improve the speed and performance of the 3D NAND Flash Memory. The hybrid memory with the design is provided with two controllers (a PCM controller and a NAND controller) which are respectively used for controlling the phase change memory and the 3D NAND Flash memory. In general, after the PCM controller of the hybrid memory receives data transmitted by an external host, the PCM controller selects to send the data to the phase change memory or the NAND controller according to a scenario in which the data is used. After the data is sent to the NAND controller, the NAND controller sends the data to the 3D NAND Flash memory.
However, in the conventional design, since the phase change memory array and the NAND memory array are controlled by different drivers, the different drivers are controlled by different controllers, and data is selectively sent to the PCM controller and the NAND controller through the external circuit, when the memory is to be changed, the operation steps and the operation time are increased, and the phase change memory array (and the controller thereof) and the NAND memory array (and the controller thereof) are usually manufactured on two chips in a motherboard, and the two chips are in data communication through the wiring on the motherboard, so that the problem that the data communication between the different memory arrays is slow occurs, and meanwhile, the problem that the semiconductor device has high manufacturing cost is also brought.
Disclosure of Invention
The invention provides a semiconductor device and a preparation method thereof, which are used for solving the problems of higher manufacturing cost and slower data communication among different storage arrays of the semiconductor device because drivers of different storage arrays in the semiconductor device are controlled by different controllers.
In order to solve the above-described problems, the present invention provides a semiconductor device including:
the peripheral circuit chip comprises a first substrate, a device layer and a first bonding layer which are sequentially stacked, wherein the device layer comprises a controller and a plurality of drivers;
The memory array chip comprises a second bonding layer, a memory array layer and a second substrate which are sequentially stacked, wherein the memory array layer comprises a plurality of memory arrays corresponding to each driver, and the memory array chip is electrically connected with the peripheral circuit chip through the second bonding layer and the first bonding layer;
the controller is used for controlling the plurality of drivers to perform read-write operations on the plurality of storage arrays corresponding to the plurality of drivers through the first bonding layer and the second bonding layer.
Further preferably, the plurality of drivers includes a first driver and a second driver, the storage array layer includes a first storage array and a second storage array, the first storage array and the first driver together form a first memory, the second storage array and the second driver together form a second memory, wherein the second memory has a faster read-write operation speed than the first memory, and the second memory is used for storing data when a programming program runs.
Further preferably, the controller is configured to write the data stored in the second memory into the first memory.
Further preferably, the first memory array is a NAND memory array, the second memory array is a phase change memory array, and the phase change memory array is located on a side of the NAND memory array away from the second substrate.
Further preferably, the NAND memory array includes a memory region and a stair region, the phase change memory array being located below a longitudinal projection of the stair region.
Further preferably, the first memory array includes at least one NAND array stack, each of the NAND array stacks includes a stack layer, a plurality of channel pillars vertically penetrating the stack layer, a plurality of first word lines, and a plurality of first bit lines, and each of the NAND array stacks is electrically connected with the first driver in the peripheral circuit chip through the plurality of first word lines and the plurality of first bit lines.
Further preferably, the second memory array includes at least one phase change memory array stack, each of the phase change memory array stacks includes a plurality of second word lines, a plurality of second bit lines, and a plurality of second memory cells disposed at intersections of the plurality of second word lines and the plurality of second bit lines, and each of the phase change memory array stacks is electrically connected with the second driver in the peripheral circuit chip through the plurality of second word lines and the plurality of second bit lines.
Further preferably, the peripheral circuit chip further includes a first interconnect layer covering the device layer, the first interconnect layer being configured to electrically connect the device layer and the first bonding layer.
Further preferably, the semiconductor device further includes a first insulating layer disposed on a side of the first substrate opposite to the device layer, and a first extraction structure disposed in the first insulating layer, the first extraction structure including a first pad and a first vertical extraction contact, the first pad being configured to electrically connect to an external circuit, the first interconnect layer including a first vertical interconnect contact, the first vertical extraction contact being electrically connected to the first vertical interconnect contact.
Further preferably, the memory array chip further includes a second interconnect layer covering the memory array layer, the second interconnect layer being configured to electrically connect the plurality of memory arrays in the memory array layer and the second bonding layer.
Further preferably, the semiconductor device further includes a second insulating layer disposed on a side of the second substrate opposite to the memory array layer, and a second extraction structure disposed in the second insulating layer, the second extraction structure including a second pad and a second vertical extraction contact, the second pad being for electrically connecting an external circuit, the second interconnect layer including a second vertical interconnect contact, the second vertical extraction contact being electrically connected with the second vertical interconnect contact.
In another aspect, the present invention further provides a method for preparing a semiconductor device, including:
providing a first substrate, and sequentially forming a device layer and a first bonding layer on the first substrate to form a peripheral circuit wafer, wherein the device layer comprises a controller and a plurality of drivers;
providing a second substrate, and sequentially forming a storage array layer and a second bonding layer on the second substrate to form a storage array wafer, wherein the storage array layer comprises a plurality of storage arrays corresponding to each driver;
Turning over the storage array wafer, and bonding the peripheral circuit wafer and the storage array wafer through the first bonding layer and the second bonding layer;
the controller is used for controlling the plurality of drivers to perform read-write operations on the plurality of storage arrays corresponding to the plurality of drivers through the first bonding layer and the second bonding layer.
Further preferably, the preparation method further comprises:
Forming a first interconnect layer overlying the device layer on the first substrate;
Wherein the first interconnect layer is to electrically connect the device layer and the first bonding layer.
Further preferably, the preparation method further comprises:
Forming a second interconnect layer overlying the memory array layer on the second substrate;
Wherein the second interconnect layer is configured to electrically connect the memory array and the second bonding layer in the memory array layer.
Further preferably, the preparation method further comprises:
Forming an insulating layer on the second substrate;
forming an extraction structure in the insulating layer;
the lead-out structure comprises a bonding pad and a vertical lead-out contact, the bonding pad is used for being electrically connected with an external circuit, the second interconnection layer comprises a vertical interconnection contact, and the vertical lead-out contact is electrically connected with the vertical interconnection contact.
The beneficial effects of the invention are as follows: the present invention provides a semiconductor device including: the peripheral circuit chips of the first substrate, the device layer and the first bonding layer are sequentially stacked, the device layer comprises a controller and a plurality of drivers, the second bonding layer, the storage array layer and the storage array chips of the second substrate are sequentially stacked, the storage array layer comprises a plurality of storage arrays corresponding to each driver, the storage array chips are electrically connected with the peripheral circuit chips through the first bonding layer and the second bonding layer, the controller is used for controlling the plurality of drivers and controlling the plurality of storage arrays corresponding to the plurality of drivers to perform read-write operation through the first bonding layer and the second bonding layer, and the controller and the plurality of drivers are formed on the same chip, so that the data communication speed between the plurality of storage arrays is improved through improving the communication speed between the controller and the plurality of drivers, and meanwhile, the manufacturing cost of the semiconductor device is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the present invention, the drawings that are needed in the description of the embodiments according to the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural view of a semiconductor device according to an embodiment of the present invention.
Fig. 2 is a further schematic structural view of a semiconductor device according to an embodiment of the present invention.
Fig. 3 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 4 a-4 j are schematic process flow diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.
The invention aims at the problems of higher manufacturing cost and slower data communication among different storage arrays of the semiconductor device because drivers of different storage arrays in the semiconductor device are controlled by different controllers in the conventional semiconductor device.
Referring to fig. 1, fig. 1 shows a schematic structure of a semiconductor device 100 according to an embodiment of the present invention, and the components of the embodiment according to the present invention and the relative positional relationship of the components can be seen in a visual manner.
As shown in fig. 1, the semiconductor device 100 includes a peripheral circuit chip 110 and a memory array chip 120, wherein:
The peripheral circuit chip 110 includes a first substrate 111, a device layer 112, and a first bonding layer 113, which are sequentially stacked, wherein the device layer 112 includes a first driver 1121, a second driver 1122, and a controller 1123;
The memory array chip 120 includes a second bonding layer 121, a memory array layer 122 and a second substrate 123 stacked in sequence, and the memory array chip 120 is disposed above the peripheral circuit chip 110 and electrically connected to the peripheral circuit chip 110 through the first bonding layer 113 and the second bonding layer 121, wherein the memory array layer 122 includes a plurality of memory arrays, i.e. a first memory array 1221 and a second memory array 1222.
Note that, the first driver 1121 is configured to drive the first storage array 1221 to perform a read/write operation, the second driver 1122 is configured to drive the second storage array 1222 to perform a read/write operation, and the controller 1123 is configured to control the first driver 1121 and the second driver 1122. Further, since the controller 1123 is located on the peripheral circuit chip 110, the first memory array 1221 and the second memory array 1222 are located on the memory array chip 120, the controller 1123 controls the first memory array 1221 by controlling the first driver 1121 through the first bonding layer 113 and the second bonding layer 121, and the controller 1123 controls the second memory array 1222 by controlling the second driver 1122 through the first bonding layer 113 and the second bonding layer 121.
Further, the first storage array 1221 and the first driver 1121 together form a first memory (not shown in the figure), and the second storage array 1222 and the second driver 1122 together form a second memory (not shown in the figure), which has a faster read/write operation speed than the first memory. Specifically, when the external host electrically connected to the semiconductor device 100 runs the programming program, the generated data is sent to the controller 1123 of the semiconductor device 100, the controller 1123 controls the second memory to store the data, and then selectively writes the data stored in the second memory into the first memory according to the usage scenario of the data.
Referring to fig. 2, fig. 2 is a schematic diagram showing a further structure of a semiconductor device 100 according to an embodiment of the present invention, and the components of the embodiment according to the present invention and the relative positional relationship of the components can be seen in a visual manner.
As shown in fig. 2, in the present embodiment, the first memory array 1221 is a NAND memory array, the second memory array 1222 is a phase change memory array, and the second memory array 1222 and the first memory array 1221 are sequentially stacked above the second bonding layer 121 (actually stacked on the second substrate 123 and then flipped) for finished product viewing, that is, the second memory array 1222 is located on a side of the first memory array 1221 away from the second substrate 123, the first driver 1121 is a NAND memory array driver, and the second driver 1122 is a phase change memory array driver. In another modification of the present invention, the first memory array 1221 (NAND memory array) and the second memory array 1222 (phase change memory array) may be sequentially stacked above the second bonding layer 121; the first memory array 1221 (NAND memory array) and the second memory array 1222 (phase change memory array) may be stacked on the second bonding layer 121 on the same horizontal plane.
Further, in the present embodiment, the first driver 1121, the second driver 1122, and the controller 1123 are located at the device layer 112 and are located at the same layer in the horizontal plane direction. In other variations of the present invention, the device layer 112 may include at least one sub-device layer, and the first driver 1121, the second driver 1122, and the controller 1123 may be located in one of the at least one sub-device layers, for example, the device layer 112 includes a first sub-device layer and a second sub-device layer, the first driver 1121 is located in the first sub-device layer, the second driver 1122, and the controller 1123 are located in the second sub-device layer, and the first sub-device layer and the second sub-device layer are located in different layers in a horizontal direction.
Further, in the present embodiment, data that is frequently accessed can be stored in the phase change memory constituted by the phase change memory array and the phase change memory array driver together, because the phase change memory has a faster read-write speed than the flash memory, so that the semiconductor device 100 can perform random access and high-speed access. And less-used data can be stored in the NAND flash memory constituted by the NAND memory array driver together, since the read/write speed of the NAND flash memory is slower than that of the phase change memory, but the storage density of the NAND flash memory is higher, and less-used data is stored in the NAND flash memory, an increase in the storage speed and a reduction in the manufacturing cost of the semiconductor device 100 can be achieved while the storage capacity of the semiconductor device 100 is increased.
With continued reference to fig. 2, the peripheral circuit chip 110 includes, in addition to the first substrate 111, the device layer 112, and the first bonding layer 113 that are sequentially stacked, a first interconnect layer 115 that covers the device layer 112.
The first substrate 111 may be a semiconductor substrate including, but not limited to, silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. Further, an isolation structure 1111 and a doped structure 1112 are formed in the first substrate 111, and the isolation structure 1111 may be a shallow trench isolation structure (STI, shallow Trench Isolation).
The device layer 112 is disposed above the first substrate 111, and the device layer 112 includes a first driver 1121, a second driver 1122, and a controller 1123 formed on the first substrate 111, wherein the first driver 1121, the second driver 1122, and the controller 1123 include a plurality of transistors 1124, respectively. Further, the doped structure 1112 in the first substrate 111 may be a source region and a drain region of the transistor 1124.
The first interconnect layer 115 serves to electrically connect the device layer 112 and the first bonding layer 113. Further, the first interconnect layer 115 includes a plurality of first lateral interconnect lines 1151 and a plurality of first vertical via contacts 1152. Note that the first interconnect layer 115 may further include one or more interlayer dielectric layers (not shown) (INTER LEVEL DIELECTRIC, ILD, also referred to as "inter-metal dielectric layer (INTER METAL DIELECTRIC, IMD)") in which the first lateral interconnect line 1151 and the first vertical via contact 1152 may also be formed, and the first interconnect layer 115 may include the first lateral interconnect line 1151 and the first vertical via contact 1152 in the plurality of interlayer dielectric layers. Specifically, the material of the first lateral interconnect line 1151 and the first vertical via contact 1152 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or a combination thereof, and the interlayer dielectric layer in the first interconnect layer 115 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or a combination thereof.
The first bonding layer 113 is disposed above the first interconnection layer 115, and includes a plurality of first bonding contacts 1131 and a dielectric (not shown) electrically isolating the plurality of first bonding contacts 1131, where the first bonding contacts 1131 penetrate the first bonding layer 113 and are electrically connected to the first interconnection layer 115. Specifically, the material of the first bonding contact 1131 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or a combination thereof. Further, in the first bonding layer 113, portions other than the plurality of first bonding contacts 1131 may be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or combinations thereof.
With continued reference to fig. 2, the memory array chip 120 includes, in addition to the second bonding layer 121, the second memory array 1222, the first memory array 1221, and the second substrate 123, which are sequentially stacked, a second interconnect layer 125 covering the first memory array 1221 and the second memory array 1222.
The second bonding layer 121 is disposed above the first bonding layer 113 of the peripheral circuit chip 110, and includes a plurality of second bonding contacts 1211 and a dielectric (not shown) electrically isolating the plurality of second bonding contacts 1211, and the second bonding contacts 1211 penetrate the second bonding layer 121 and are electrically connected to the second interconnection layer 125. Specifically, the material of the second bonding contact 1211 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or a combination thereof. Further, in the second bonding layer 121, portions other than the plurality of second bonding contacts 1211 may be formed with a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or a combination thereof.
The second Memory array 1222 is disposed above the second bonding layer 121, and in this embodiment, the second Memory array 1222 is a phase change Memory array (PHASE CHANGE Memory, PCM) including a plurality of second Word Lines (WL) 12221, a plurality of second Bit Lines (BL) 12222, and a plurality of second Memory cells 12223 (phase change Memory cells) disposed at intersections of the plurality of second Word lines 12221 and the plurality of second Bit lines 12222. The second word line 12221 and the second bit line 12222 are conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or combinations thereof. The second memory array 1222 (phase change memory array) stores data through a difference in resistance exhibited when the phase change material in the second memory cell 12223 is transformed between crystalline and amorphous states. In particular, the material of the second memory cell 12223 includes a chalcogenide-based alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy, or any other suitable phase change material, resistive oxide material, or conductive bridge material.
In this embodiment, the second memory array 1222 includes two phase change memory array stacks, but in other variations of the present invention, the second memory array 1222 may include only one layer of phase change memory array or more than two layers of phase change memory array stacks, each phase change memory array stack includes a plurality of second word lines, a plurality of second bit lines, and a plurality of second memory cells disposed at intersections of the plurality of second word lines and the plurality of second bit lines, and each phase change memory array stack is electrically connected to the peripheral circuit chip 110 through the plurality of second word lines and the plurality of second bit lines. For example, in one possible modification, the second memory array 1222 includes a first phase-change memory array stack and a second phase-change memory array stack sequentially stacked above the second bonding layer 121, wherein the first phase-change memory array stack includes a plurality of first word lines, a plurality of first bit lines, and a plurality of first phase-change memory cells disposed at intersections of the plurality of first word lines and the plurality of first bit lines, and the first phase-change memory array stack is electrically connected to the second driver 1122 in the peripheral circuit chip 110 through the plurality of first word lines and the plurality of first bit lines, so that the second driver 1122 can drive the first phase-change memory cells to perform a read/write operation; the second phase-change memory array stack includes a plurality of second word lines, a plurality of second bit lines, and a plurality of second phase-change memory cells disposed at intersections of the plurality of second word lines and the plurality of second bit lines, and is electrically connected to the second driver 1122 in the peripheral circuit chip 110 through the plurality of second word lines and the plurality of second bit lines, so that the second driver 1122 can drive the second phase-change memory cells to perform read/write operations.
The first memory array 1221 is disposed above the second memory array 1222, and in this embodiment, the first memory array 1221 is a NAND memory array, and includes a stacked layer 12211 and a plurality of channel pillars vertically penetrating the stacked layer 12211.
Note that, the first storage array 1221 includes a storage area and a step area, and in order to prevent the read/write of the first storage array 1221 and the second storage array 1222 from interfering with each other, in this embodiment, the second storage array 1222 is disposed below the longitudinal projection of the step area of the first storage array 1221.
Wherein the stacked layer 12211 is formed by alternately stacking the insulating layer 122111 and the gate layer 122112, the insulating layer 122111 is made of an insulating material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or a combination of the above, and the gate layer 122112 is made of a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (AL), doped silicon, silicide, or a combination of the above. Further, the stacked layer 12211 includes a bottom selection tube layer (not shown in the drawing) including 2 insulating layers 122111 and 2 gate layers 122112 alternately stacked, wherein the number of gate layers 122112 of the bottom selection tube layer is at least 1, but may be 2, 3, or other numbers.
Further, the plurality of channel pillars vertically penetrating the stack layer 12211 may include a plurality of memory channel pillars 122121, a plurality of dummy channel pillars 122122, and a plurality of transition channel pillars (not shown) disposed between the plurality of memory channel pillars 122121 and the plurality of dummy channel pillars 122122. Note that in this embodiment, each memory channel pillar 122121 is a NAND memory string of the "charge trapping" type, and a functional layer 1221211 and a channel layer 1221212 are sequentially formed on the inner wall of each memory channel pillar 122121, and the functional layer 1221211 includes a tunneling layer, a storage layer (also referred to as "charge trapping layer"), and a blocking layer stacked in this order from the inside of the memory channel pillar 122121 to the outside surface of the memory channel pillar 122121. Exemplary materials for the tunneling layer may include silicon oxide, silicon oxynitride, or a combination thereof, exemplary materials for the storage layer may include silicon nitride, silicon oxynitride, silicon, or a combination thereof, exemplary materials for the blocking layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or a combination thereof, and exemplary materials for the channel layer 1221212 may include amorphous silicon, polycrystalline silicon, or single-crystal silicon.
Further, memory channel pillar 122121 also includes a plurality of control gates, in this embodiment, each gate layer 122112 in stack layer 12211 acts as a control gate for each memory cell in memory channel pillar 122121.
Further, each memory channel pillar 122121 also includes an epitaxial layer 1221213 and a plug 1221214, the epitaxial layer 1221213 is used as a channel for the source select gate control of the memory channel pillar 122121, the epitaxial layer 1221213 is disposed on the memory channel pillar 122121 near the end of the second substrate 123 and contacts the channel layer 1221212 of the memory channel pillar 122121, the plug 1221214 is used as a drain of the memory channel pillar 122121, and in this embodiment, the plug 1221214 is also used as an etch stop layer of the memory channel pillar 122121 to prevent etching of dielectrics (e.g., silicon oxide and silicon nitride) filled in the memory Chu Goudao pillar 122121. Further, exemplary materials of epitaxial layer 1221213 may include semiconductor material epitaxially grown from second substrate 123, such as monocrystalline silicon, and exemplary materials of plug 1221214 may include polycrystalline silicon.
It should be noted that in other embodiments resulting from the present invention, the memory channel pillars 122121 may also be "floating gate" type NAND memory strings. It should be appreciated that there may be multiple stacked layers 12211 in the memory array chip 120, and that a memory array chip 120 having multiple stacked layers 12211 may have inter-layer plugs located between different stacked layers 12211 to make electrical connection to memory channel pillars 122121 in different stacked layers 12211.
Note that in this embodiment, the first memory array 1221 includes only one layer of NAND memory array, and in other variations of the present invention, the first memory array 1221 may include a plurality of NAND array stacks, each of which includes a stack layer, a plurality of channel pillars vertically penetrating the stack layer, a plurality of first word lines, and a plurality of first bit lines, and each of which is electrically connected to the peripheral circuit chip 110 through the plurality of first word lines and the plurality of first bit lines. For example, in one possible modification, the first memory array 1221 includes a first NAND array stack layer and a second NAND array stack layer sequentially stacked over the second memory array 1222, wherein the first NAND array stack layer includes a first stacked layer, a plurality of first memory channel pillars vertically penetrating the first stacked layer, a plurality of third word lines, and a plurality of third bit lines, and the first NAND array stack layer is electrically connected to the first driver 1121 in the peripheral circuit chip 110 through the plurality of third word lines and the plurality of third bit lines, so that the first driver 1121 can drive the memory cells in the first memory channel pillars to perform read/write operations; the second NAND array stack includes a second stack layer, a plurality of second memory channel pillars vertically penetrating the second stack layer, a plurality of fourth word lines, and a plurality of fourth bit lines, and is electrically connected to the first driver 1121 in the peripheral circuit chip 110 through the plurality of fourth word lines and the plurality of fourth bit lines, so that the first driver 1121 can drive the memory cells in the second memory channel pillars to perform read and write operations.
The second interconnect layer 125 is used to electrically connect the first memory array 1221 and the second bonding layer 121, and to electrically connect the second memory array 1222 and the second bonding layer 121. Further, the second interconnect layer 125 includes a plurality of second lateral interconnect lines 1251 and a plurality of second vertical via contacts 1252. It should be noted that the second interconnect layer 125 may further include one or more interlayer dielectric layers (not shown in the drawings) (INTER LEVEL DIELECTRIC, ILD, also referred to as "inter-metal dielectric layer (INTER METAL DIELECTRIC, IMD)") in which the second lateral interconnect line 1251 and the second vertical via contact 1252 may also be formed, and the second interconnect layer 125 may include the second lateral interconnect line 1251 and the second vertical via contact 1252 in the plurality of interlayer dielectric layers. Specifically, the material of the second lateral interconnect line 1251 and the second vertical via contact 1252 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or a combination of the above, and the interlayer dielectric layer in the second interconnect layer 125 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or a combination of the above.
The second substrate 123 is disposed on the first memory array 1221 and may be a semiconductor substrate, specifically including at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.
Further, referring to fig. 2, in the present embodiment, the semiconductor device 100 further includes a second insulating layer 130 disposed on a side of the second substrate 123 opposite to the memory array layer 122, and a second extraction structure 131 disposed in the second insulating layer 130. Specifically, the second lead-out structure 131 includes a second pad 1311 and a second vertical lead-out contact 1312, the second pad 1311 is used to electrically connect an external circuit to transmit an electrical signal between the semiconductor device 100 and the external circuit, and the second interconnect layer 125 includes at least one second vertical interconnect contact 1253, and the second vertical lead-out contact 1312 is electrically connected with the second vertical interconnect contact 1253.
In other modifications of the present invention, the second insulating layer 130 may be disposed on a side of the first substrate 111 opposite to the device layer 112, or a first insulating layer and a first lead-out structure (not shown) that are functional as the second insulating layer 130 and the second lead-out structure 131 disposed in the second insulating layer 130 may be disposed on the side, where the first lead-out structure disposed in the first insulating layer includes a first pad and a first vertical lead-out contact, the first pad is electrically connected to an external circuit for transmitting an electrical signal between the semiconductor device 100 and the external circuit, and the first interconnect layer 115 includes at least one first vertical interconnect contact (not shown) and the first vertical lead-out contact is electrically connected to the first vertical interconnect contact.
In this embodiment, the first driver 1121, the second driver 1122, and the controller 1123 may be electrically connected to the first storage array 1221 and the second storage array 1222 through a first lateral interconnect line 1151, a first vertical via contact 1152, a first bonding contact 1131, a second bonding contact 1211, a second lateral interconnect line 1251, and a second vertical via contact 1252.
Unlike the prior art, the present invention provides a semiconductor device 100 including: the peripheral circuit chip 110 in which the first substrate 111, the device layer 112 and the first bonding layer 113 are sequentially stacked, the device layer 112 includes the first driver 1121, the second driver 1122 and the controller 1123, the second bonding layer 121, the second memory array 1222, the first memory array 1221 and the memory array chip 120 of the second substrate 123 are sequentially stacked, and the memory array chip 120 is disposed above the peripheral circuit chip 110 and electrically connected to the peripheral circuit chip 110 through the first bonding layer 113 and the second bonding layer 121, wherein the controller 1123 is configured to control the first memory array 1221 and the second memory array 1222 by controlling the first driver 1121 and the second driver 1122 and by controlling the first bonding layer 113 and the second bonding layer 121, and to effectively reduce the manufacturing cost of the semiconductor device 1222 by increasing the communication speed between the controller 1123 and the first driver 1121 and the second driver 1122 and by increasing the communication speed between the first memory array 1221 and the second driver 1122.
Referring to fig. 3 and fig. 4a to fig. 4j, fig. 3 is a schematic flow chart of a method for manufacturing a semiconductor device 200 according to an embodiment of the invention, and fig. 4a to fig. 4j are schematic flow charts of a method for manufacturing a semiconductor device 200 according to an embodiment of the invention.
As shown in fig. 3, the method for manufacturing the semiconductor device 200 specifically includes:
Peripheral circuit wafer formation step S101: a first substrate 211 is provided, and a device layer 212 and a first bonding layer 213 are sequentially formed on the first substrate 211 to form a peripheral circuit wafer 210, wherein the device layer 212 includes a first driver 2121, a second driver 2122, and a controller 2123.
Specifically, referring to fig. 4a, in the present embodiment, the first substrate 211 may be a semiconductor substrate including, but not limited to, silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon On Insulator (SOI), or any other suitable material, and the isolation structures 2111 and the doping structures 2112 are formed in the first substrate 211, and the isolation structures 2111 may be shallow trench isolation structures (STI, shallow Trench Isolation).
The device layer 212 is disposed over the first substrate 211, and the device layer 212 includes a first driver 2121, a second driver 2122, and a controller 2123 formed over the first substrate 211, wherein the first driver 2121, the second driver 2122, and the controller 2123 include a plurality of transistors 2124, respectively. Further, the doped structure 2112 in the first substrate 211 may be a source region and a drain region of the transistor 2124.
It will be readily appreciated that in this embodiment, the transistor 2124 can be formed by a variety of processes including, but not limited to, photolithography, dry/wet etching, thin film deposition, thermal growth, implantation, chemical Mechanical Polishing (CMP), and any other suitable process; the doping structure 1112 may be formed in the first substrate 211 by ion implantation and/or thermal diffusion; the isolation structures 2111 may be formed in the first substrate 211 by wet/dry etching and thin film deposition.
Note that, since the peripheral circuit wafer 210 further includes the first interconnect layer 215 for electrically connecting the device layer 212 and the first bonding layer 213, the peripheral circuit wafer forming step S101 further includes:
a first interconnect layer 215 is formed on the first substrate 211 overlying the device layer 212.
Specifically, referring to fig. 4b, the first interconnect layer 215 includes a plurality of first lateral interconnect lines 2151 and a plurality of first vertical via contacts 2152. It should be noted that the first interconnect layer 215 may further include one or more interlayer dielectric layers (not shown) (INTER LEVEL DIELECTRIC, ILD, also referred to as "inter-metal dielectric layer (INTER METAL DIELECTRIC, IMD)") in which the first lateral interconnect line 2151 and the first vertical via contact 2152 may also be formed, and the first interconnect layer 215 may include the first lateral interconnect line 2151 and the first vertical via contact 2152 in the plurality of interlayer dielectric layers. Specifically, the material of the first lateral interconnect lines 2151 and the first vertical via contacts 2152 include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or combinations thereof, and the interlayer dielectric layer in the first interconnect layer 215 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or combinations thereof.
It is readily understood that in the present embodiment, the plurality of first lateral interconnect lines 2151 and the plurality of first vertical via contacts 2152 in the first interconnect layer 215 may comprise an electrically conductive material deposited by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapour Deposition, PVD), atomic layer deposition (Atomic Layer Deposition, ALD), electroplating, electroless plating, or any combination thereof. The fabrication process for forming the interconnect may also include photolithography, chemical Mechanical Polishing (CMP), wet/dry etching, or any other suitable process. The interlayer dielectric layer (ILD layer) described above may comprise a dielectric material deposited by one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof.
Further, referring to fig. 4c, the first bonding layer 213 is disposed above the first interconnection layer 215, and includes a plurality of first bonding contacts 2131 and a dielectric (not shown) electrically isolating the plurality of first bonding contacts 2131, wherein the first bonding contacts 2131 penetrate the first bonding layer 213 and are electrically connected to the first interconnection layer 215. Specifically, the material of the first bonding contact 2131 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or a combination thereof. Further, in the first bonding layer 213, portions other than the plurality of first bonding contacts 2131 may be formed with a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or a combination thereof.
It is readily understood that in this embodiment, a dielectric layer may be deposited on the top surface of the first interconnect layer 215 by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof. Then, by first patterning a first contact hole (not shown in the drawing) through the dielectric layer using a patterning process (e.g., photolithography and dry/wet etching of the dielectric material in the dielectric layer), a first contact hole may be formed through the dielectric layer and in contact with the first lateral interconnect line 2151 and the first vertical via contact 2152 in the first interconnect layer 115, and a conductor (e.g., copper) may be filled in the first contact hole to form the first bonding contact 2131. In some embodiments, the process step of filling the first contact hole further comprises depositing a barrier layer, an adhesion layer and/or a seed layer prior to depositing the conductor.
Memory array wafer forming step S102: a second substrate 223 is provided, and a first memory array 2221, a second memory array 2222, and a second bonding layer 221 are sequentially formed on the second substrate 223 to form a memory array wafer 220.
Specifically, referring to FIG. 4d, in the present embodiment, the second substrate 223 may be a semiconductor substrate, specifically including at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.
The first memory array 2221 is disposed on the second substrate 223, and in this embodiment, the first memory array 2221 is a NAND memory array, and includes a stacked layer 22211 and a plurality of channel pillars vertically penetrating the stacked layer 22211. The stacked layer 22211 is formed by alternately stacking insulating layers 222111 and sacrificial layers, and after forming a plurality of channel columns, the sacrificial layers are replaced with the gate layers 222112. Specifically, the insulating layer 222111 is made of an insulating material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and the gate layer 222112 is made of a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (AL), doped silicon, silicide, or a combination thereof.
It is readily understood that the alternating layers of insulating layers 222111 and sacrificial layers may be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof. And the replacement step of the sacrificial layer with the gate layer 222112 may be formed by a gate replacement process, for example, wet/dry etching the sacrificial layer to form a recess, and then filling the resulting recess with a conductive material to replace the sacrificial layer with the gate layer 222112. And the process of forming the plurality of channel pillars may include: a channel hole (not shown) is formed vertically through the stacked layer 22211 and into the second substrate 223 using dry etching and/or wet etching, such as deep reactive ion etching (DeepReaction Ion Etching, DRIE), and then an epitaxial layer 2221213 is epitaxially grown from the second substrate 223 in a lower portion of the channel hole. In this embodiment, the manufacturing process for forming the NAND memory array further includes: filling the channel holes with a plurality of layers (functional layer 2221211 and channel layer 2221212) using a thin film deposition process such as ALD, CVD, PVD or any combination thereof; and the manufacturing process for forming the NAND memory array further comprises: the plug 2221214 is formed in the upper portion of the channel hole by etching a recess at the upper end of the channel pillar 22212 and filling the recess with semiconductor material using a thin film deposition process such as ALD, CVD, PVD or any combination thereof.
Specifically, referring to fig. 4e, in the present embodiment, the second Memory array 2222 is a phase change Memory array (PHASE CHANGE Memory, PCM) and includes a plurality of second Word lines (Word lines, WL) 22221, a plurality of second Bit lines (Bit lines, BL) 22222, and a plurality of second Memory cells 22223 (phase change Memory cells) disposed at intersections of the plurality of second Word lines 22221 and the plurality of second Bit lines 22222. The second word line 22221 and the second bit line 22222 are conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or a combination thereof. The second memory array 2222 (phase change memory array) stores data through a difference in conductivity exhibited when the phase change material in the second memory cell 22223 is converted between the crystalline state and the amorphous state. Specifically, the material of the second memory cell 22223 includes a chalcogenide-based alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy, or any other suitable phase change material, resistive oxide material, or conductive bridge material.
It is to be readily appreciated that second memory cell 22223 (phase change memory cell) may be formed by a variety of processes including, but not limited to, photolithography, dry/wet etching, thin film deposition, thermal growth, implantation, chemical Mechanical Polishing (CMP), and any other suitable process.
It should be noted that, the storage array wafer 210 further includes a second interconnect layer 225 covering the first storage array 2221 and the second storage array 2222, and in the memory Chu Zhenlie wafer forming step S102, further includes:
a second interconnect layer 225 covering the first memory array 2221 and the second memory array 2222 is formed on the second substrate 223.
Specifically, referring to fig. 4f, the second interconnect layer 225 is configured to electrically connect the first memory array 2221 and the second bonding layer 221, and electrically connect the second memory array 2222 and the second bonding layer 221. Further, the second interconnect layer 225 includes a plurality of second lateral interconnect lines 2251 and a plurality of second vertical via contacts 2252. It should be noted that the second interconnect layer 225 may further include one or more interlayer dielectric layers (not shown) (INTER LEVEL DIELECTRIC, ILD, also referred to as "inter-metal dielectric layer (INTER METAL DIELECTRIC, IMD)") in which the second lateral interconnect line 2251 and the second vertical via contact 2252 may also be formed, and the second interconnect layer 225 may include the second lateral interconnect line 2251 and the second vertical via contact 2252 in the plurality of interlayer dielectric layers. Specifically, the material of the second lateral interconnect line 2251 and the second vertical via contact 2252 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or a combination of the above, and the interlayer dielectric layer in the second interconnect layer 225 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or a combination of the above.
It is readily understood that in the present embodiment, the plurality of second lateral interconnect lines 2251 and the plurality of second vertical via contacts 2252 in the second interconnect layer 225 may comprise an electrically conductive material deposited by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapour Deposition, PVD), atomic layer deposition (Atomic Layer Deposition, ALD), electroplating, electroless plating, or any combination thereof. The fabrication process for forming the interconnect may also include photolithography, chemical Mechanical Polishing (CMP), wet/dry etching, or any other suitable process. The interlayer dielectric layer (ILD layer) described above may comprise a dielectric material deposited by one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof.
Further, referring to fig. 4g, the second bonding layer 221 includes a plurality of second bonding contacts 2211 and a dielectric (not shown) electrically isolating the plurality of second bonding contacts 2211, and the second bonding contacts 2211 penetrate through the second bonding layer 221 and are electrically connected to the second interconnection layer 225. Specifically, the material of the second bonding contact 2211 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or a combination thereof. Further, in the second bonding layer 221, portions other than the plurality of second bonding contacts 2211 may be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or combinations thereof.
It is readily understood that in this embodiment, a dielectric layer may be deposited on the top surface of the first interconnect layer 215 by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof. Then, by first patterning a first contact hole (not shown in the drawings) through the dielectric layer using a patterning process (e.g., photolithography and dry/wet etching of the dielectric material in the dielectric layer), a first contact hole may be formed through the dielectric layer and in contact with the first lateral interconnect line 2151 and the first vertical via contact 2152 in the first interconnect layer 215, and a conductor (e.g., copper) may be filled in the first contact hole to form the first bonding contact 1131. In some embodiments, the process step of filling the first contact hole further comprises depositing a barrier layer, an adhesion layer and/or a seed layer prior to depositing the conductor.
Bonding step S103: the memory array wafer 220 is flipped over and the peripheral circuit wafer 210 and the memory array wafer 220 are bonded via the first bonding layer 213 and the second bonding layer 221.
Specifically, referring to fig. 4 h-4 i, the first bonding contacts 2131 in the first bonding layer 213 are in one-to-one correspondence with the second bonding contacts 2211 in the second bonding layer 221.
In order to enable transmission of an electrical signal between the semiconductor device 200 and an external circuit, after the bonding step S103, the method further includes:
forming an insulating layer 230 on the second substrate 223;
An extraction structure 231 is formed in the insulating layer 230.
Specifically, referring to fig. 4j, the lead-out structure 231 includes a second pad 2311 and a second vertical lead-out contact 2312, the second pad 2311 is used for electrically connecting to an external circuit to transmit an electrical signal between the semiconductor device 200 and the external circuit, and the second interconnect layer 225 includes at least one second vertical interconnect contact 2253, and the second vertical lead-out contact 2312 is electrically connected to the second vertical interconnect contact 2253.
It is readily appreciated that in this embodiment, the first driver 2121, the second driver 2122, and the controller 2123 may be electrically connected to the first storage array 2221 and the second storage array 2222 through a first lateral interconnect line 2151, a first vertical via contact 2152, a first bonding contact 2131, a second bonding contact 2211, a second lateral interconnect line 2251, and a second vertical via contact 2252.
Unlike the prior art, the present invention provides a method for manufacturing a semiconductor device 200, comprising: providing a first substrate 211, and sequentially forming a device layer 212 and a first bonding layer 213 on the first substrate 211 to form a peripheral circuit wafer 210, wherein the device layer 212 comprises a first driver 2121, a second driver 2122 and a controller 2123, providing a second substrate 223, sequentially forming a first memory array 2221, a second memory array 2222 and a second bonding layer 221 on the second substrate 223 to form a memory array wafer 220, and then flipping the memory array wafer 220 and bonding the peripheral circuit wafer 210 and the memory array wafer 220 through the first bonding layer 213 and the second bonding layer 221, wherein the memory array wafer 220 is electrically connected to the peripheral circuit wafer 210 through the first bonding layer 213 and the second bonding layer 221, wherein the controller 2123 is configured to control the first driver 2121 and the second driver 2122 through the first bonding layer 213 and the second bonding layer 221, and control the first memory array 2121 and the second memory array 2122 through the first bonding layer 213 and the second bonding layer 221, and simultaneously drive the second memory array 2122 through the first driver 2121 and the second bonding layer 2122, thereby improving the speed of the semiconductor array memory device to be manufactured and simultaneously with the second driver 2122, and simultaneously improving the speed of the semiconductor array memory device chip communication between the first driver 2121 and the second driver 2122 and the semiconductor array 2122.
In addition to the embodiments described above, other embodiments of the invention are possible. All technical schemes adopting equivalent replacement or equivalent replacement fall within the protection scope of the invention.
In summary, although the preferred embodiments of the present invention have been described above, the above preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various modifications and adaptations without departing from the spirit and scope of the present invention, so that the scope of the present invention is defined by the claims.
Claims (15)
1. A semiconductor device, the semiconductor device comprising:
the peripheral circuit chip comprises a first substrate, a device layer and a first bonding layer which are sequentially stacked, wherein the device layer comprises a controller and a plurality of drivers;
The memory array chip comprises a second bonding layer, a memory array layer and a second substrate which are sequentially stacked, wherein the memory array layer comprises a plurality of memory arrays corresponding to each driver, and the memory array chip is electrically connected with the peripheral circuit chip through the second bonding layer and the first bonding layer;
The controller is used for controlling the plurality of storage arrays corresponding to the plurality of drivers to perform read-write operation by controlling the plurality of drivers and through the first bonding layer and the second bonding layer;
The plurality of drivers includes a first driver and a second driver, the memory array layer includes a first memory array connected with the first driver and a second memory array connected with the second driver, and the second memory array is located on a side of the first memory array away from the second substrate.
2. The semiconductor device of claim 1, wherein the first memory array and the first driver together comprise a first memory, the second memory array and the second driver together comprise a second memory, wherein the second memory has a faster read and write operation speed than the first memory, and the second memory is configured to store data during program operation.
3. The semiconductor device according to claim 2, wherein the controller is configured to write the data held by the second memory to the first memory.
4. The semiconductor device of claim 2, wherein the first memory array is a NAND memory array and the second memory array is a phase change memory array.
5. The semiconductor device of claim 4, wherein the NAND memory array comprises a memory region and a stair region, the phase change memory array being located below a longitudinal projection of the stair region.
6. The semiconductor device of claim 4, wherein the first memory array comprises at least one NAND array stack, each NAND array stack comprises a stack layer, a plurality of channel pillars vertically penetrating the stack layer, a plurality of first word lines, and a plurality of first bit lines, and each NAND array stack is electrically connected to the first driver in the peripheral circuit chip through the plurality of first word lines and the plurality of first bit lines.
7. The semiconductor device of claim 4, wherein the second memory array comprises at least one phase change memory array stack, each phase change memory array stack comprises a plurality of second word lines, a plurality of second bit lines, and a plurality of second memory cells disposed at intersections of the plurality of second word lines and the plurality of second bit lines, and each phase change memory array stack is electrically connected to the second driver in the peripheral circuit chip through the plurality of second word lines and the plurality of second bit lines.
8. The semiconductor device of claim 1, wherein the peripheral circuit chip further comprises a first interconnect layer overlying the device layer, the first interconnect layer to electrically connect the device layer and the first bonding layer.
9. The semiconductor device of claim 8, further comprising a first insulating layer disposed on a side of the first substrate opposite the device layer, and a first extraction structure disposed in the first insulating layer, the first extraction structure comprising a first pad and a first vertical extraction contact, the first pad to electrically connect an external circuit, the first interconnect layer comprising a first vertical interconnect contact, the first vertical extraction contact electrically connected with the first vertical interconnect contact.
10. The semiconductor device of claim 1, wherein the memory array chip further comprises a second interconnect layer overlying the memory array layer, the second interconnect layer to electrically connect the plurality of memory arrays in the memory array layer and the second bonding layer.
11. The semiconductor device of claim 10, further comprising a second insulating layer disposed on a side of the second substrate opposite the memory array layer, and a second extraction structure disposed in the second insulating layer, the second extraction structure including a second pad and a second vertical extraction contact, the second pad to electrically connect an external circuit, the second interconnect layer including a second vertical interconnect contact, the second vertical extraction contact electrically connected with the second vertical interconnect contact.
12. A method of manufacturing a semiconductor device, the method comprising:
providing a first substrate, and sequentially forming a device layer and a first bonding layer on the first substrate to form a peripheral circuit wafer, wherein the device layer comprises a controller and a plurality of drivers;
providing a second substrate, and sequentially forming a storage array layer and a second bonding layer on the second substrate to form a storage array wafer, wherein the storage array layer comprises a plurality of storage arrays corresponding to each driver;
Turning over the storage array wafer, and bonding the peripheral circuit wafer and the storage array wafer through the first bonding layer and the second bonding layer;
The controller is used for controlling the plurality of storage arrays corresponding to the plurality of drivers to perform read-write operation by controlling the plurality of drivers and through the first bonding layer and the second bonding layer;
The plurality of drivers includes a first driver and a second driver, the memory array layer includes a first memory array connected with the first driver and a second memory array connected with the second driver, and the second memory array is located on a side of the first memory array away from the second substrate.
13. The method of manufacturing according to claim 12, characterized in that the method of manufacturing further comprises:
Forming a first interconnect layer overlying the device layer on the first substrate;
Wherein the first interconnect layer is to electrically connect the device layer and the first bonding layer.
14. The method of manufacturing according to claim 12, characterized in that the method of manufacturing further comprises:
Forming a second interconnect layer overlying the memory array layer on the second substrate;
Wherein the second interconnect layer is configured to electrically connect the memory array and the second bonding layer in the memory array layer.
15. The method of manufacturing according to claim 14, further comprising:
Forming an insulating layer on the second substrate;
forming an extraction structure in the insulating layer;
the lead-out structure comprises a bonding pad and a vertical lead-out contact, the bonding pad is used for being electrically connected with an external circuit, the second interconnection layer comprises a vertical interconnection contact, and the vertical lead-out contact is electrically connected with the vertical interconnection contact.
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