CN113206099A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
Abstract
The present invention provides a semiconductor device, including: a peripheral circuit chip sequentially stacked with a first substrate, a device layer and a first bonding layer, the device layer including a controller and a plurality of drivers, a memory array chip sequentially stacked with a second bonding layer, a memory array layer and a second substrate, the memory array layer including a plurality of memory arrays corresponding to each driver, and the memory array chip is electrically connected with the peripheral circuit chip through the first bonding layer and the second bonding layer, wherein the controller controls the plurality of drivers via the first bonding layer and the second bonding layer, and control a plurality of memory arrays corresponding to a plurality of drivers to perform read and write operations, and since the controller and the plurality of drivers are formed on the same chip, therefore, the communication speed between the plurality of memory arrays is effectively improved by improving the communication speed between the controller and the plurality of drivers, and meanwhile, the manufacturing cost of the semiconductor device is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
As technology develops, the semiconductor industry continues to seek new ways to produce such that each memory die in a memory device has a greater number of memory cells. In order to further increase the storage density of the memory, a memory device of a three-dimensional structure including a plurality of memory cells stacked in a vertical direction has been developed, the integration can be increased by times on a unit area of a wafer, and the cost can be reduced. Among the nonvolatile memories, 3D NAND Flash (three-dimensional NAND Flash memory) memories having 32 layers, 64 layers, and even higher layers have been designed.
In the prior art, Phase Change Memory (PCM) is generally used as a buffer of a 3D NAND Flash Memory to improve the speed and performance of the 3D NAND Flash Memory. The hybrid memory in this design has two controllers (PCM controller and NAND controller) for controlling the phase change memory and the 3D NAND Flash memory, respectively. Generally, after receiving data transmitted from an external host, a PCM controller of a hybrid memory selects to send the data to a phase change memory or a NAND controller according to a scenario of use of the data. And when the data is sent to the NAND controller, the NAND controller sends the data to the 3D NAND Flash memory.
However, in the conventional design, since the phase change memory array and the NAND memory array are controlled by different drivers respectively, the different drivers are controlled by different controllers, and data is selected to be sent to the PCM controller and the NAND controller through an external circuit, when a memory is to be changed, the memory needs to be transferred through the external circuit and the different controllers, which increases operation steps and operation time, and the phase change memory array (and the controller thereof) and the NAND memory array (and the controller thereof) are usually manufactured on two chips in one motherboard respectively, and data communication is performed between the two chips through traces on the motherboard, thereby resulting in a problem that data communication between the different memory arrays is slow, and simultaneously, a problem that a semiconductor device has high manufacturing cost is also brought.
Disclosure of Invention
The invention provides a semiconductor device and a preparation method thereof, which are used for solving the problems that the manufacturing cost of the semiconductor device is higher and the data communication between different storage arrays is slower because drivers of different storage arrays in the semiconductor device are controlled by different controllers.
In order to solve the above problem, the present invention provides a semiconductor device including:
the peripheral circuit chip comprises a first substrate, a device layer and a first bonding layer which are sequentially stacked, wherein the device layer comprises a controller and a plurality of drivers;
the storage array chip comprises a second bonding layer, a storage array layer and a second substrate which are sequentially stacked, the storage array layer comprises a plurality of storage arrays corresponding to each driver, and the storage array chip is electrically connected with the peripheral circuit chip through the second bonding layer and the first bonding layer;
the controller is configured to control the plurality of drivers and control the plurality of memory arrays corresponding to the plurality of drivers to perform read and write operations through the first bonding layer and the second bonding layer.
Further preferably, the plurality of drivers include a first driver and a second driver, the storage array layer includes a first storage array and a second storage array, the first storage array and the first driver together form a first memory, and the second storage array and the second driver together form a second memory, where the second memory has a faster read/write speed than the first memory, and the second memory is used to store data when the program runs.
Further preferably, the controller is configured to write the data stored in the second memory into the first memory.
Further preferably, the first memory array is a NAND memory array, the second memory array is a phase change memory array, and the phase change memory array is located on a side of the NAND memory array away from the second substrate.
Further preferably, the NAND memory array includes a memory area and a staircase area, and the phase change memory array is located below a longitudinal projection of the staircase area.
Further preferably, the first memory array includes at least one NAND array stack, each of the NAND array stacks includes a stack layer, a plurality of channel pillars vertically penetrating the stack layer, a plurality of first word lines, and a plurality of first bit lines, and each of the NAND array stacks is electrically connected to the first driver in the peripheral circuit chip through the plurality of first word lines and the plurality of first bit lines.
Further preferably, the second memory array includes at least one phase change memory array stack, each of the phase change memory array stacks includes a plurality of second word lines, a plurality of second bit lines, and a plurality of second memory cells disposed at intersections of the plurality of second word lines and the plurality of second bit lines, and each of the phase change memory array stacks is electrically connected to the second driver in the peripheral circuit chip through the plurality of second word lines and the plurality of second bit lines.
Further preferably, the peripheral circuit chip further includes a first interconnection layer covering the device layer, and the first interconnection layer is configured to electrically connect the device layer and the first bonding layer.
Further preferably, the semiconductor device further includes a first insulating layer disposed on a side of the first substrate opposite to the device layer, and a first lead-out structure disposed in the first insulating layer, the first lead-out structure includes a first pad and a first vertical lead-out contact, the first pad is configured to be electrically connected to an external circuit, the first interconnect layer includes a first vertical interconnect contact, and the first vertical lead-out contact is electrically connected to the first vertical interconnect contact.
Further preferably, the memory array chip further includes a second interconnection layer covering the memory array layer, and the second interconnection layer is configured to electrically connect the plurality of memory arrays in the memory array layer and the second bonding layer.
Further preferably, the semiconductor device further includes a second insulating layer disposed on a side of the second substrate opposite to the memory array layer, and a second lead-out structure disposed in the second insulating layer, where the second lead-out structure includes a second pad and a second vertical lead-out contact, the second pad is used to electrically connect an external circuit, the second interconnect layer includes a second vertical interconnect contact, and the second vertical lead-out contact is electrically connected to the second vertical interconnect contact.
In another aspect, the present invention further provides a method for manufacturing a semiconductor device, including:
providing a first substrate, and sequentially forming a device layer and a first bonding layer on the first substrate to form a peripheral circuit wafer, wherein the device layer comprises a controller and a plurality of drivers;
providing a second substrate, and sequentially forming a storage array layer and a second bonding layer on the second substrate to form a storage array wafer, wherein the storage array layer comprises a plurality of storage arrays corresponding to each driver;
turning over the storage array wafer, and bonding the peripheral circuit wafer and the storage array wafer through the first bonding layer and the second bonding layer;
the controller is configured to control the plurality of drivers and control the plurality of memory arrays corresponding to the plurality of drivers to perform read and write operations through the first bonding layer and the second bonding layer.
Further preferably, the preparation method further comprises:
forming a first interconnect layer overlying the device layer on the first substrate;
wherein the first interconnect layer is to electrically connect the device layer and the first bonding layer.
Further preferably, the preparation method further comprises:
forming a second interconnect layer overlying the memory array layer on the second substrate;
wherein the second interconnect layer is configured to electrically connect the memory array in the memory array layer and the second bonding layer.
Further preferably, the preparation method further comprises:
forming an insulating layer on the second substrate;
forming an extraction structure in the insulating layer;
the lead-out structure comprises a bonding pad and a vertical lead-out contact, the bonding pad is used for being electrically connected with an external circuit, the second interconnection layer comprises a vertical interconnection contact, and the vertical lead-out contact is electrically connected with the vertical interconnection contact.
The invention has the beneficial effects that: the present invention provides a semiconductor device, including: the peripheral circuit chip is sequentially stacked with a first substrate, a device layer and a first bonding layer, the device layer comprises a controller and a plurality of drivers, and the storage array chip is sequentially stacked with a second bonding layer, a storage array layer and a second substrate, the storage array layer comprises a plurality of storage arrays corresponding to each driver, and the storage array chip is electrically connected with the peripheral circuit chip through the first bonding layer and the second bonding layer, wherein the controller is used for controlling the plurality of drivers and controlling the plurality of storage arrays corresponding to the plurality of drivers to carry out read-write operation through the first bonding layer and the second bonding layer, and the controller and the plurality of drivers are formed on the same chip, so that the data communication speed between the plurality of storage arrays is effectively improved by improving the communication speed between the controller and the plurality of drivers, meanwhile, the manufacturing cost of the semiconductor device is reduced.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the description of the embodiments according to the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without inventive effort.
Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.
Fig. 2 is a further schematic structural diagram of a semiconductor device provided in accordance with an embodiment of the present invention.
Fig. 3 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 4 a-4 j are schematic process flow diagrams of methods for fabricating semiconductor devices according to embodiments of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
The invention aims at the problems that the manufacturing cost of the semiconductor device is higher and the data communication between different storage arrays is slower because drivers of different storage arrays in the semiconductor device are controlled by different controllers in the conventional semiconductor device.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a semiconductor device 100 according to an embodiment of the present invention, in which components and relative positions of the components can be visually seen.
As shown in fig. 1, the semiconductor device 100 includes a peripheral circuit chip 110 and a memory array chip 120, wherein:
the peripheral circuit chip 110 includes a first substrate 111, a device layer 112, and a first bonding layer 113 sequentially stacked, where the device layer 112 includes a first driver 1121, a second driver 1122, and a controller 1123;
the memory array chip 120 includes a second bonding layer 121, a memory array layer 122 and a second substrate 123 stacked in sequence, and the memory array chip 120 is disposed above the peripheral circuit chip 110 and electrically connected to the peripheral circuit chip 110 through the first bonding layer 113 and the second bonding layer 121, and wherein the memory array layer 122 includes a plurality of memory arrays, i.e., a first memory array 1221 and a second memory array 1222.
It should be noted that the first driver 1121 is configured to drive the first storage array 1221 for read and write operations, the second driver 1122 is configured to drive the second storage array 1222 for read and write operations, and the controller 1123 is configured to control the first driver 1121 and the second driver 1122. Further, since the controller 1123 is located on the peripheral circuit chip 110 and the first and second memory arrays 1221 and 1222 are located on the memory array chip 120, the controller 1123 controls the first memory array 1221 through the first and second bonding layers 113 and 121 by controlling the first driver 1121, and the controller 1123 controls the second memory array 1222 through the first and second bonding layers 113 and 121 by controlling the second driver 1122.
Further, the first storage array 1221 and the first driver 1121 together form a first memory (not shown), and the second storage array 1222 and the second driver 1122 together form a second memory (not shown), wherein the second memory has a faster read/write operation speed than the first memory. Specifically, when the external host electrically connected to the semiconductor device 100 runs the programming program, the generated data is sent to the controller 1123 of the semiconductor device 100, and the controller 1123 controls the second memory to store the data, and then selectively writes the data stored in the second memory into the first memory according to the usage scenario of the data.
Referring to fig. 2, fig. 2 is a schematic diagram illustrating a further structure of the semiconductor device 100 according to the embodiment of the present invention, in which the components and the relative positions of the components can be seen visually.
As shown in fig. 2, in the present embodiment, the first memory array 1221 is a NAND memory array, the second memory array 1222 is a phase change memory array, and the second memory array 1222 and the first memory array 1221 are stacked above the second bonding layer 121 (actually stacked on the second substrate 123 and then flipped) in sequence as viewed from the finished product, that is, the second memory array 1222 is located on a side of the first memory array 1221 away from the second substrate 123, the first driver 1121 is a NAND memory array driver, and the second driver 1122 is a phase change memory array driver. In another modification of the present invention, the first memory array 1221(NAND memory array) and the second memory array 1222 (phase change memory array) may be sequentially stacked above the second bonding layer 121; the first memory array 1221(NAND memory array) and the second memory array 1222 (phase change memory array) may be located at the same level and stacked above the second bonding layer 121.
Further, in the present embodiment, the first driver 1121, the second driver 1122, and the controller 1123 are located on the device layer 112 and are located on the same layer in the horizontal plane direction. It should be noted that in other variations formed by the present invention, the device layer 112 may include at least one sub-device layer, and the first driver 1121, the second driver 1122 and the controller 1123 may be respectively located in one of the at least one sub-device layer, for example, the device layer 112 includes a first sub-device layer and a second sub-device layer, the first driver 1121 is located in the first sub-device layer, and the second driver 1122 and the controller 1123 are located in the second sub-device layer, and the first sub-device layer and the second sub-device layer are located in different layers in the horizontal plane direction.
Further, in the present embodiment, frequently accessed data can be stored in the phase change memory constituted by the phase change memory array and the phase change memory array driver in common, because the phase change memory has a faster read and write speed than the flash memory, so that the semiconductor device 100 can perform random access and high-speed access. And less used data can be stored in the NAND flash memory configured in common with the NAND memory array driver because the NAND flash memory has a slower read and write speed than the phase change memory, but the NAND flash memory has a higher storage density, and less used data is stored in the NAND flash memory, so that the increase in the storage speed and the reduction in the manufacturing cost of the semiconductor device 100 can be realized on the premise of increasing the storage capacity of the semiconductor device 100.
With reference to fig. 2, the peripheral circuit chip 110 includes a first interconnection layer 115 covering the device layer 112, in addition to the first substrate 111, the device layer 112 and the first bonding layer 113 which are stacked in sequence.
The first substrate 111 may be a semiconductor substrate including, but not limited to, silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. Further, an Isolation structure 1111 and a doped structure 1112 are formed in the first substrate 111, and the Isolation structure 1111 may be a Shallow Trench Isolation (STI) structure.
The device layer 112 is disposed above the first substrate 111, and the device layer 112 includes a first driver 1121, a second driver 1122, and a controller 1123 formed on the first substrate 111, wherein the first driver 1121, the second driver 1122, and the controller 1123 respectively include a plurality of transistors 1124. Further, the doped structures 1112 in the first substrate 111 may be source and drain regions of the transistor 1124.
The first interconnect layer 115 is used to electrically connect the device layer 112 and the first bonding layer 113. Further, the first interconnect layer 115 includes a plurality of first lateral interconnect lines 1151 and a plurality of first vertical via contacts 1152. It should be noted that the first interconnect layer 115 may further include one or more interlayer Dielectric layers (not shown in the drawings) (Inter Level Dielectric, ILD, also referred to as "Inter Metal Dielectric (IMD)"), in which the first lateral interconnect line 1151 and the first vertical via contact 1152 may also be formed, and the first interconnect layer 115 may include the first lateral interconnect line 1151 and the first vertical via contact 1152 in the plurality of interlayer Dielectric layers. Specifically, the material of the first lateral interconnect lines 1151 and the first vertical via contacts 1152 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or combinations thereof, and the interlayer dielectric layer in the first interconnect layer 115 may include a dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or combinations thereof.
The first bonding layer 113 is disposed above the first interconnection layer 115, and includes a plurality of first bonding contacts 1131 and a dielectric (not shown) electrically isolating the plurality of first bonding contacts 1131, wherein the first bonding contacts 1131 penetrate through the first bonding layer 113 and are electrically connected to the first interconnection layer 115. Specifically, the material of the first bonding contact 1131 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or a combination thereof. Further, in the first bonding layer 113, portions other than the plurality of first bonding contacts 1131 may be formed with a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or a combination thereof.
With continued reference to fig. 2, the memory array chip 120 includes a second interconnection layer 125 covering the first memory array 1221 and the second memory array 1222, in addition to the second bonding layer 121, the second memory array 1222, the first memory array 1221 and the second substrate 123 which are sequentially stacked.
The second bonding layer 121 is disposed above the first bonding layer 113 of the peripheral circuit chip 110, and includes a plurality of second bonding contacts 1211 and a dielectric (not shown) electrically isolating the plurality of second bonding contacts 1211, wherein the second bonding contacts 1211 penetrate through the second bonding layer 121 and are electrically connected to the second interconnection layer 125. Specifically, the material of second bonding contact 1211 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or combinations thereof. Further, in the second bonding layer 121, portions other than the plurality of second bonding contacts 1211 may be formed with a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or a combination thereof.
The second Memory array 1222 is disposed above the second bonding layer 121, and in the present embodiment, the second Memory array 1222 is a Phase Change Memory (PCM) array including a plurality of second Word Lines (WL) 12221, a plurality of second Bit Lines (BL) 12222, and a plurality of second Memory cells 12223 (Phase Change Memory cells) disposed at intersections of the plurality of second Word lines 12221 and the plurality of second Bit lines 12222. The second word lines 12221 and the second bit lines 12222 are made of a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or a combination thereof. The second memory array 1222 (phase change memory array) stores data by the difference in resistance exhibited by the phase change material in the second memory cell 12223 when it is transformed between a crystalline state and an amorphous state. Specifically, the material of the second memory cell 12223 includes a chalcogenide-based alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy, or any other suitable phase change material, resistive oxide material, or conductive bridge material.
It should be noted that, in this embodiment, the second memory array 1222 includes two phase change memory array stacks, but in other variations formed by the present invention, the second memory array 1222 may include only one phase change memory array or more than two phase change memory array stacks, each phase change memory array stack includes a plurality of second word lines, a plurality of second bit lines, and a plurality of second memory cells disposed at intersections of the plurality of second word lines and the plurality of second bit lines, and each phase change memory array stack is electrically connected to the peripheral circuit chip 110 through the plurality of second word lines and the plurality of second bit lines. For example, in one possible modification, the second memory array 1222 includes a first phase change memory array stack and a second phase change memory array stack sequentially stacked and disposed above the second bonding layer 121, where the first phase change memory array stack includes a plurality of first word lines, a plurality of first bit lines, and a plurality of first phase change memory cells disposed at intersections of the plurality of first word lines and the plurality of first bit lines, and the first phase change memory array stack is electrically connected to the second driver 1122 in the peripheral circuit chip 110 through the plurality of first word lines and the plurality of first bit lines, so that the second driver 1122 may drive the first phase change memory cells to perform read and write operations; the second phase change memory array stack includes a plurality of second word lines, a plurality of second bit lines, and a plurality of second phase change memory cells disposed at intersections of the plurality of second word lines and the plurality of second bit lines, and the second phase change memory array stack is electrically connected to the second driver 1122 in the peripheral circuit chip 110 through the plurality of second word lines and the plurality of second bit lines, so that the second driver 1122 can drive the second phase change memory cells to perform read and write operations.
The first memory array 1221 is disposed above the second memory array 1222, and in the present embodiment, the first memory array 1221 is a NAND memory array, and includes a stack layer 12211 and a plurality of channel pillars vertically penetrating through the stack layer 12211.
It should be noted that the first memory array 1221 includes memory areas and a ladder area, and in order to prevent the read/write between the first memory array 1221 and the second memory array 1222 from interfering with each other, in this embodiment, the second memory array 1222 is disposed below the longitudinal projection of the ladder area of the first memory array 1221.
The stacked layer 12211 is formed by alternately stacking the insulating layers 122111 and the gate layer 122112, the insulating layer 122111 is made of an insulating material including, but not limited to, silicon oxide, silicon nitride, or silicon oxynitride, or a combination thereof, and the gate layer 122112 is made of a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), Aluminum (AL), doped silicon, or silicide, or a combination thereof. Further, the stacked layer 12211 includes a bottom selection pipe layer (not shown in the figure), which includes 2 insulating layers 122111 and 2 gate layers 122112 stacked alternately, wherein the number of the gate layers 122112 of the bottom selection pipe layer is at least 1, and may also be 2 or 3 or other numbers.
Further, the plurality of channel pillars vertically penetrating the stacked layer 12211 may include a plurality of storage channel pillars 122121, a plurality of dummy channel pillars 122122, and a plurality of transition channel pillars (not shown) disposed between the plurality of storage channel pillars 122121 and the plurality of dummy channel pillars 122122. It should be noted that, in the present embodiment, each memory channel pillar 122121 is a NAND memory string of "charge trapping" type, and a functional layer 1221211 and a channel layer 1221212 are sequentially formed on the inner wall of each memory channel pillar 122121, and the functional layer 1221211 sequentially includes a stacked tunneling layer, a storage layer (also referred to as "charge trapping layer"), and a blocking layer from the inside of the memory channel pillar 122121 to the outer surface of the memory channel pillar 122121. Exemplary materials of the tunneling layer may include silicon oxide, silicon oxynitride, or combinations thereof, exemplary materials of the storage layer may include silicon nitride, silicon oxynitride, silicon, or combinations thereof, exemplary materials of the blocking layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or combinations thereof, and exemplary materials of the channel layer 1221212 may include amorphous silicon, polycrystalline silicon, or monocrystalline silicon, among others.
Further, the memory channel pillar 122121 also includes a plurality of control gates, and in this embodiment, each gate layer 122112 in the stack 12211 serves as a control gate for each memory cell in the memory channel pillar 122121.
Further, each of the memory channel pillars 122121 further includes an epitaxial layer 1221213 and a plug 1221214, the epitaxial layer 1221213 is used as a source select gate controlled channel of the memory channel pillar 122121, the epitaxial layer 1221213 is disposed at an end of the memory channel pillar 122121 near the second substrate 123 and is in contact with the channel layer 1221212 of the memory channel pillar 122121, the plug 1221214 is used as a drain of the memory channel pillar 122121, and in the present embodiment, the plug 1221214 is also used as an etch stop layer of the memory channel pillar 122121 to prevent etching of dielectrics (e.g., silicon oxide and silicon nitride) filled in the memory channel pillar 122121. Further, exemplary materials of epitaxial layer 1221213 may include semiconductor materials epitaxially grown from second substrate 123, such as single crystal silicon, and exemplary materials of plugs 1221214 may include polysilicon.
It should be noted that in other embodiments consistent with the present invention, the storage channel pillar 122121 may also be a "floating gate" type NAND memory string. It should be understood that the memory array chip 120 may have multiple stacked layers 12211, and the memory array chip 120 with multiple stacked layers 12211 may have interlayer plugs between different stacked layers 12211 to electrically connect the memory channel pillars 122121 in different stacked layers 12211.
It should be noted that, in the present embodiment, the first memory array 1221 includes only one layer of NAND memory array, but in other variations of the present invention, the first memory array 1221 may include a plurality of NAND array stacks, each of the NAND array stacks respectively includes a stack layer, a plurality of channel pillars vertically penetrating through the stack layer, a plurality of first word lines, and a plurality of first bit lines, and each of the NAND array stacks is electrically connected to the peripheral circuit chip 110 through the plurality of first word lines and the plurality of first bit lines. For example, in one possible modification, the first memory array 1221 includes a first NAND array stack and a second NAND array stack sequentially stacked over the second memory array 1222, wherein the first NAND array stack includes a first stack layer, a plurality of first memory channel pillars vertically penetrating the first stack layer, a plurality of third word lines, and a plurality of third bit lines, and the first NAND array stack is electrically connected to the first driver 1121 in the peripheral circuit chip 110 through the plurality of third word lines and the plurality of third bit lines, so that the first driver 1121 may drive the memory cells in the first memory channel pillars for read and write operations; the second NAND array stack includes a second stack layer, a plurality of second storage channel pillars vertically penetrating the second stack layer, a plurality of fourth word lines, and a plurality of fourth bit lines, and the second NAND array stack is electrically connected to the first driver 1121 in the peripheral circuit chip 110 through the plurality of fourth word lines and the plurality of fourth bit lines, so that the first driver 1121 can drive the storage units in the second storage channel pillars for read and write operations.
The second interconnect layer 125 is used to electrically connect the first memory array 1221 and the second bonding layer 121, and to electrically connect the second memory array 1222 and the second bonding layer 121. Further, the second interconnect layer 125 includes a plurality of second lateral interconnect lines 1251 and a plurality of second vertical via contacts 1252. It should be noted that the second interconnect layer 125 may further include one or more interlayer Dielectric layers (not shown in the drawings) (Inter Level Dielectric, ILD, also referred to as "Inter Metal Dielectric (IMD)"), in which the second lateral interconnect lines 1251 and the second vertical via contacts 1252 may also be formed, and the second interconnect layer 125 may include the second lateral interconnect lines 1251 and the second vertical via contacts 1252 in the plurality of interlayer Dielectric layers. Specifically, the material of the second lateral interconnect lines 1251 and the second vertical via contacts 1252 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or combinations thereof, and the interlayer dielectric layer in the second interconnect layer 125 may include a dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or combinations thereof.
The second substrate 123, which may be a semiconductor substrate, is disposed on the first memory array 1221, and specifically includes at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.
Further, with reference to fig. 2, in the present embodiment, the semiconductor device 100 further includes a second insulating layer 130 disposed on a side of the second substrate 123 opposite to the memory array layer 122, and a second lead-out structure 131 disposed in the second insulating layer 130. Specifically, the second lead-out structure 131 includes a second pad 1311 and a second vertical lead-out contact 1312, the second pad 1311 is used to electrically connect an external circuit to transmit an electrical signal between the semiconductor device 100 and the external circuit, and the second interconnect layer 125 includes at least one second vertical interconnect contact 1253, and the second vertical lead-out contact 1312 is electrically connected to the second vertical interconnect contact 1253.
In another modification of the present invention, the second insulating layer 130 may be disposed on a side of the first substrate 111 opposite to the device layer 112, or a first insulating layer and a first lead-out structure (not shown) having the same functions as the second insulating layer 130 and the second lead-out structure 131 disposed in the second insulating layer 130 may be disposed on the side, the first lead-out structure disposed in the first insulating layer includes a first pad and a first vertical lead-out contact, the first pad is electrically connected to an external circuit to transmit an electrical signal between the semiconductor device 100 and the external circuit, and the first interconnect layer 115 includes at least one first vertical interconnect contact (not shown), and the first vertical lead-out contact is electrically connected to the first vertical interconnect contact.
In the present embodiment, the first driver 1121, the second driver 1122, and the controller 1123 may be electrically connected to the first memory array 1221 and the second memory array 1222 through first lateral interconnection lines 1151, first vertical via contacts 1152, first bonding contacts 1131, second bonding contacts 1211, second lateral interconnection lines 1251, and second vertical via contacts 1252.
Unlike the prior art, the present invention provides a semiconductor device 100 comprising: a peripheral circuit chip 110 sequentially stacked with a first substrate 111, a device layer 112 and a first bonding layer 113, the device layer 112 including a first driver 1121, a second driver 1122 and a controller 1123, a memory array chip 120 sequentially stacked with a second bonding layer 121, a second memory array 1222, a first memory array 1221 and a second substrate 123, and the memory array chip 120 disposed above the peripheral circuit chip 110 and electrically connected to the peripheral circuit chip 110 through the first bonding layer 113 and the second bonding layer 121, wherein the controller 1123 is configured to control the first memory array 1221 and the second memory array 1222 to perform read and write operations by controlling the first driver 1121 and the second driver 1122 and via the first bonding layer 113 and the second bonding layer 121, and since the controller 1123 is formed on the same chip as the first driver 1121 and the second driver, communication between the controller 1122 and the first driver 1121 and the second driver 1122 is effectively improved The data communication speed between the first memory array 1221 and the second memory array 1222 is increased, and at the same time, the manufacturing cost of the semiconductor device 100 is reduced.
Referring to fig. 3 and fig. 4a to 4j, fig. 3 is a schematic flow chart of a method for manufacturing the semiconductor device 200 according to an embodiment of the present invention, and fig. 4a to 4j are schematic process flow charts of a method for manufacturing the semiconductor device 200 according to an embodiment of the present invention.
As shown in fig. 3, the method for manufacturing the semiconductor device 200 specifically includes:
peripheral circuit wafer forming step S101: a first substrate 211 is provided, and a device layer 212 and a first bonding layer 213 are sequentially formed on the first substrate 211 to form a peripheral circuit wafer 210, wherein the device layer 212 includes a first driver 2121, a second driver 2122, and a controller 2123.
Specifically, referring to fig. 4a, in the present embodiment, the first substrate 211 may be a semiconductor substrate including, but not limited to, silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material, an Isolation structure 2111 and a doped structure 2112 are formed in the first substrate 211, and the Isolation structure 2111 may be a Shallow Trench Isolation (STI).
The device layer 212 is disposed over the first substrate 211, and the device layer 212 includes a first driver 2121, a second driver 2122, and a controller 2123 formed on the first substrate 211, wherein the first driver 2121, the second driver 2122, and the controller 2123 each include a plurality of transistors 2124. Further, the doped structures 2112 in the first substrate 211 may be source and drain regions of the transistor 2124.
It will be readily appreciated that in this embodiment, transistor 2124 may be formed by a variety of processes including, but not limited to, photolithography, dry/wet etching, thin film deposition, thermal growth, implantation, Chemical Mechanical Polishing (CMP), and any other suitable process; the doped structures 1112 may be formed in the first substrate 211 by ion implantation and/or thermal diffusion; the isolation structure 2111 may be formed in the first substrate 211 by wet/dry etching and thin film deposition.
It should be noted that, since the peripheral circuit wafer 210 further includes the first interconnect layer 215 for electrically connecting the device layer 212 and the first bonding layer 213, in the peripheral circuit wafer forming step S101, the method further includes:
a first interconnect layer 215 is formed overlying the device layer 212 on the first substrate 211.
Specifically, referring to fig. 4b, the first interconnect layer 215 includes a plurality of first lateral interconnect lines 2151 and a plurality of first vertical via contacts 2152. It should be noted that the first interconnect layer 215 may further include one or more interlayer Dielectric layers (not shown) (Inter Level Dielectric, ILD, also referred to as "Inter Metal Dielectric (IMD)"), in which the first lateral interconnect line 2151 and the first vertical via contact 2152 may also be formed, and the first interconnect layer 215 may include the first lateral interconnect line 2151 and the first vertical via contact 2152 among the plurality of interlayer Dielectric layers. Specifically, the material of the first lateral interconnect lines 2151 and the first vertical via contacts 2152 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or combinations thereof, and the interlayer dielectric layer in the first interconnect layer 215 may include a dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or combinations thereof.
It is readily understood that in the present embodiment, the plurality of first lateral interconnect lines 2151 and the plurality of first vertical via contacts 2152 in the first interconnect Layer 215 may comprise conductive material deposited by one or more thin film Deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), electroplating, electroless plating, or any combination thereof. The manufacturing process for forming the interconnect may also include photolithography, Chemical Mechanical Polishing (CMP), wet/dry etching, or any other suitable process. The interlayer dielectric layer (ILD layer) described above may comprise a dielectric material deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.
Further, referring to fig. 4c, the first bonding layer 213 is disposed above the first interconnection layer 215, and includes a plurality of first bonding contacts 2131 and a dielectric (not shown) electrically isolating the plurality of first bonding contacts 2131, wherein the first bonding contacts 2131 penetrate through the first bonding layer 213 and are electrically connected to the first interconnection layer 215. Specifically, the material of the first bonding contact 2131 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or a combination thereof. Further, in the first bonding layer 213, portions other than the plurality of first bonding contacts 2131 may be formed with a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or a combination thereof.
It is readily understood that in the present embodiment, the dielectric layer may be deposited on the top surface of the first interconnect layer 215 by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Then, first contact holes (not shown in the figure) are first patterned through the dielectric layer by using a patterning process (e.g., photolithography and dry/wet etching of the dielectric material in the dielectric layer), first contact holes may be formed through the dielectric layer and in contact with the first lateral interconnect lines 2151 and the first vertical via contacts 2152 in the first interconnect layer 115, and a conductor (e.g., copper) is filled in the first contact holes to form first bonding contacts 2131. In some embodiments, the process step of filling the first contact hole further comprises depositing a barrier layer, an adhesion layer, and/or a seed layer prior to depositing the conductor.
A memory array wafer forming step S102: a second substrate 223 is provided, and a first memory array 2221, a second memory array 2222, and a second bonding layer 221 are sequentially formed on the second substrate 223 to form a memory array wafer 220.
Specifically, referring to fig. 4d, in the present embodiment, the second substrate 223 may be a semiconductor substrate, and specifically includes at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.
It will be readily appreciated that the alternating layers of insulating 222111 and sacrificial layers may be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. And a replacement step to replace the sacrificial layer with the gate layer 222112 may be formed by a gate replacement process, e.g., wet/dry etching a recess into the sacrificial layer, followed by filling the resulting recess with a conductive material to replace the sacrificial layer with the gate layer 222112. And the process method for forming the plurality of channel pillars may include: a channel hole (not shown) is formed vertically through stack 22211 and into second substrate 223 using dry Etching and/or wet Etching (e.g., Deep Reactive Ion Etching (DRIE)), and epitaxial layer 2221213 is then epitaxially grown from second substrate 223 in a lower portion of the channel hole. In this embodiment, the manufacturing process for forming the NAND memory array further includes: filling the channel hole with a plurality of layers (functional layer 2221211 and channel layer 2221212) using a thin film deposition process such as ALD, CVD, PVD, or any combination thereof; and the manufacturing process for forming a NAND memory array further comprises: plugs 2221214 are formed in the upper portion of the channel holes by etching recesses at the upper ends of the channel posts 22212 and filling the recesses with semiconductor material using a thin film deposition process such as ALD, CVD, PVD, or any combination thereof.
Specifically, referring to fig. 4e, in the present embodiment, the second Memory array 2222 is a Phase Change Memory (PCM) array, and includes a plurality of second Word Lines (WL) 22221, a plurality of second Bit Lines (BL) 22222, and a plurality of second Memory cells 22223 (Phase Change Memory cells) disposed at intersections of the plurality of second Word lines 22221 and the plurality of second Bit lines 22222. The second word lines 22221 and the second bit lines 22222 are made of conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or combinations thereof. Second memory array 2222 (phase change memory array) stores data by the difference in conductivity exhibited by the phase change material in second memory cell 22223 as it transitions between the crystalline and amorphous states. Specifically, the material of the second memory cell 22223 includes a chalcogenide-based alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy, or any other suitable phase change material, resistive oxide material, or conductive bridge material.
It will be readily appreciated that the second memory cell 22223 (phase change memory cell) may be formed by a variety of processes including, but not limited to, photolithography, dry/wet etching, thin film deposition, thermal growth, implantation, Chemical Mechanical Polishing (CMP), and any other suitable process.
It should be noted that the memory array wafer 210 further includes a second interconnect layer 225 covering the first memory array 2221 and the second memory array 2222, and in the step S102 of forming the memory array wafer, the method further includes:
a second interconnect layer 225 is formed on the second substrate 223 covering the first memory array 2221 and the second memory array 2222.
Specifically, referring to fig. 4f, the second interconnect layer 225 is used to electrically connect the first memory array 2221 and the second bonding layer 221, and electrically connect the second memory array 2222 and the second bonding layer 221. Further, the second interconnect layer 225 includes a plurality of second lateral interconnect lines 2251 and a plurality of second vertical via contacts 2252. It should be noted that the second interconnect layer 225 may further include one or more Inter-Level Dielectric layers (not shown) (ILD, also referred to as "Inter Metal Dielectric (IMD)"), in which the second lateral interconnect lines 2251 and the second vertical via contacts 2252 may also be formed, and the second interconnect layer 225 may include the second lateral interconnect lines 2251 and the second vertical via contacts 2252 in the plurality of Inter-Level Dielectric layers. Specifically, the material of the second lateral interconnect lines 2251 and the second vertical via contacts 2252 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or combinations thereof, and the interlayer dielectric layer in the second interconnect layer 225 may include a dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or combinations thereof.
It is readily appreciated that, in the present embodiment, the plurality of second lateral interconnect lines 2251 and the plurality of second vertical via contacts 2252 in the second interconnect Layer 225 may comprise conductive material deposited by one or more thin film Deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), electroplating, electroless plating, or any combination thereof. The manufacturing process for forming the interconnect may also include photolithography, Chemical Mechanical Polishing (CMP), wet/dry etching, or any other suitable process. The interlayer dielectric layer (ILD layer) described above may comprise a dielectric material deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.
Further, referring to fig. 4g, the second bonding layer 221 includes a plurality of second bonding contacts 2211 and a dielectric (not shown) electrically isolating the plurality of second bonding contacts 2211, and the second bonding contacts 2211 penetrate the second bonding layer 221 and are electrically connected to the second interconnection layer 225. Specifically, the material of the second bonding contact 2211 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or a combination thereof. Further, in the second bonding layer 221, portions other than the plurality of second bonding contacts 2211 may be formed with a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or a combination thereof.
It is readily understood that in the present embodiment, the dielectric layer may be deposited on the top surface of the first interconnect layer 215 by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Then, first contact holes (not shown in the figure) may be formed through the dielectric layer and in contact with the first lateral interconnect lines 2151 and the first vertical via contacts 2152 in the first interconnect layer 215 by first patterning first contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry/wet etching of the dielectric material in the dielectric layer) and filling the first contact holes with a conductor (e.g., copper) to form first bonding contacts 1131. In some embodiments, the process step of filling the first contact hole further comprises depositing a barrier layer, an adhesion layer, and/or a seed layer prior to depositing the conductor.
Bonding step S103: the memory array wafer 220 is flipped over, and the peripheral circuit wafer 210 and the memory array wafer 220 are bonded through the first bonding layer 213 and the second bonding layer 221.
Specifically, referring to fig. 4 h-4 i, the first bonding contacts 2131 in the first bonding layer 213 correspond to the second bonding contacts 2211 in the second bonding layer 221 one to one.
In order to enable transmission of an electrical signal between the semiconductor device 200 and an external circuit, after the bonding step S103, the method further includes:
forming an insulating layer 230 on the second substrate 223;
an extraction structure 231 is formed in the insulating layer 230.
Specifically, referring to fig. 4j, the lead structure 231 includes a second pad 2311 and a second vertical lead contact 2312, the second pad 2311 is used for electrically connecting an external circuit to transmit an electrical signal between the semiconductor device 200 and the external circuit, the second interconnect layer 225 includes at least one second vertical interconnect contact 2253, and the second vertical lead contact 2312 is electrically connected to the second vertical interconnect contact 2253.
It is readily understood that, in the present embodiment, the first driver 2121, the second driver 2122, and the controller 2123 may be electrically connected to the first memory array 2221 and the second memory array 2222 by the first lateral interconnection line 2151, the first vertical via contact 2152, the first bonding contact 2131, the second bonding contact 2211, the second lateral interconnection line 2251, and the second vertical via contact 2252.
Different from the prior art, the invention provides a preparation method of a semiconductor device 200, which comprises the following steps: providing a first substrate 211, and sequentially forming a device layer 212 and a first bonding layer 213 on the first substrate 211 to form a peripheral circuit wafer 210, wherein the device layer 212 includes a first driver 2121, a second driver 2122, and a controller 2123, providing a second substrate 223, and sequentially forming a first storage array 2221, a second storage array 2222, and a second bonding layer 221 on the second substrate 223 to form a storage array wafer 220, and then flipping the storage array wafer 220 and bonding the peripheral circuit wafer 210 and the storage array wafer 220 through the first bonding layer 213 and the second bonding layer 221, wherein the storage array wafer 220 is electrically connected to the peripheral circuit wafer 210 through the first bonding layer 213 and the second bonding layer 221, wherein the controller 2123 is configured to control the first driver 2121 and the second driver 2122, and bond the peripheral circuit wafer 210 through the first bonding layer 213 and the second bonding layer 221, the first memory array 2221 and the second memory array 2222 are controlled to perform read/write operations, and the controller 2123, the first driver 2121 and the second driver 2122 are formed on the same chip, so that the data communication speed between the first memory array 2221 and the second memory array 2222 is effectively increased by increasing the communication speed between the controller 2123 and the first driver 2121 and the second driver 2122, and the manufacturing cost of the semiconductor device 200 is reduced.
In addition to the above embodiments, the present invention may have other embodiments. All technical solutions formed by using equivalents or equivalent substitutions fall within the protection scope of the claims of the present invention.
In summary, although the preferred embodiments of the present invention have been described above, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (15)
1. A semiconductor device, characterized in that the semiconductor device comprises:
the peripheral circuit chip comprises a first substrate, a device layer and a first bonding layer which are sequentially stacked, wherein the device layer comprises a controller and a plurality of drivers;
the storage array chip comprises a second bonding layer, a storage array layer and a second substrate which are sequentially stacked, the storage array layer comprises a plurality of storage arrays corresponding to each driver, and the storage array chip is electrically connected with the peripheral circuit chip through the second bonding layer and the first bonding layer;
the controller is configured to control the plurality of drivers and control the plurality of memory arrays corresponding to the plurality of drivers to perform read and write operations through the first bonding layer and the second bonding layer.
2. The semiconductor device according to claim 1, wherein the plurality of drivers include a first driver and a second driver, the storage array layer includes a first storage array and a second storage array, the first storage array and the first driver together constitute a first memory, the second storage array and the second driver together constitute a second memory, and wherein the second memory has a faster read/write operation speed than the first memory and is configured to store data during a program operation.
3. The semiconductor device according to claim 2, wherein the controller is configured to write the data held by the second memory to the first memory.
4. The semiconductor device according to claim 2, wherein the first memory array is a NAND memory array, the second memory array is a phase change memory array, and the phase change memory array is located on a side of the NAND memory array remote from the second substrate.
5. The semiconductor device according to claim 4, wherein the NAND memory array comprises a memory region and a staircase region, and wherein the phase change memory array is located below a longitudinal projection of the staircase region.
6. The semiconductor device according to claim 4, wherein the first memory array includes at least one NAND array stack, each of the NAND array stacks includes a stack layer, a plurality of channel pillars vertically penetrating the stack layer, a plurality of first word lines, and a plurality of first bit lines, and each of the NAND array stacks is electrically connected to the first driver in the peripheral circuit chip through the plurality of first word lines and the plurality of first bit lines.
7. The semiconductor device according to claim 4, wherein the second memory array includes at least one phase-change memory array stack, each of the phase-change memory array stacks includes a plurality of second word lines, a plurality of second bit lines, and a plurality of second memory cells disposed at intersections of the plurality of second word lines and the plurality of second bit lines, and each of the phase-change memory array stacks is electrically connected to the second driver in the peripheral circuit chip through the plurality of second word lines and the plurality of second bit lines.
8. The semiconductor device of claim 1, wherein the peripheral circuit die further comprises a first interconnect layer overlying the device layer, the first interconnect layer to electrically connect the device layer and the first bonding layer.
9. The semiconductor device according to claim 8, further comprising a first insulating layer provided on a side of the first substrate opposite to the device layer, and a first lead-out structure provided in the first insulating layer, the first lead-out structure including a first pad for electrically connecting an external circuit and a first vertical lead-out contact, the first interconnect layer including a first vertical interconnect contact, the first vertical lead-out contact being electrically connected to the first vertical interconnect contact.
10. The semiconductor device of claim 1, wherein the memory array chip further comprises a second interconnect layer overlying the memory array layer, the second interconnect layer configured to electrically connect the plurality of memory arrays in the memory array layer and the second bonding layer.
11. The semiconductor device according to claim 10, further comprising a second insulating layer provided on a side of the second substrate opposite to the memory array layer, and a second lead-out structure provided in the second insulating layer, the second lead-out structure including a second pad for electrically connecting an external circuit and a second vertical lead-out contact, the second interconnect layer including a second vertical interconnect contact, the second vertical lead-out contact being electrically connected to the second vertical interconnect contact.
12. A method of manufacturing a semiconductor device, the method comprising:
providing a first substrate, and sequentially forming a device layer and a first bonding layer on the first substrate to form a peripheral circuit wafer, wherein the device layer comprises a controller and a plurality of drivers;
providing a second substrate, and sequentially forming a storage array layer and a second bonding layer on the second substrate to form a storage array wafer, wherein the storage array layer comprises a plurality of storage arrays corresponding to each driver;
turning over the storage array wafer, and bonding the peripheral circuit wafer and the storage array wafer through the first bonding layer and the second bonding layer;
the controller is configured to control the plurality of drivers and control the plurality of memory arrays corresponding to the plurality of drivers to perform read and write operations through the first bonding layer and the second bonding layer.
13. The method of manufacturing according to claim 12, further comprising:
forming a first interconnect layer overlying the device layer on the first substrate;
wherein the first interconnect layer is to electrically connect the device layer and the first bonding layer.
14. The method of manufacturing according to claim 12, further comprising:
forming a second interconnect layer overlying the memory array layer on the second substrate;
wherein the second interconnect layer is configured to electrically connect the memory array in the memory array layer and the second bonding layer.
15. The method of manufacturing according to claim 14, further comprising:
forming an insulating layer on the second substrate;
forming an extraction structure in the insulating layer;
the lead-out structure comprises a bonding pad and a vertical lead-out contact, the bonding pad is used for being electrically connected with an external circuit, the second interconnection layer comprises a vertical interconnection contact, and the vertical lead-out contact is electrically connected with the vertical interconnection contact.
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