CN113192937A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN113192937A CN113192937A CN202110480443.5A CN202110480443A CN113192937A CN 113192937 A CN113192937 A CN 113192937A CN 202110480443 A CN202110480443 A CN 202110480443A CN 113192937 A CN113192937 A CN 113192937A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 239000000463 material Substances 0.000 claims description 8
- 238000005538 encapsulation Methods 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 abstract description 4
- 229910000679 solder Inorganic materials 0.000 description 19
- 230000000052 comparative effect Effects 0.000 description 6
- 230000003287 optical effect Effects 0.000 description 3
- 239000013307 optical fiber Substances 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 238000013528 artificial neural network Methods 0.000 description 1
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- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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- 239000011159 matrix material Substances 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000009423 ventilation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06E—OPTICAL COMPUTING DEVICES; COMPUTING DEVICES USING OTHER RADIATIONS WITH SIMILAR PROPERTIES
- G06E3/00—Devices not provided for in group G06E1/00, e.g. for processing analogue or hybrid data
- G06E3/001—Analogue devices in which mathematical operations are carried out with the aid of optical or electro-optical elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
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Abstract
The invention relates to the field of photonic integrated circuits, and provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes an EIC chip and a PIC chip, the PIC chip being mounted on a substrate, a plurality of the EIC chips being disposed on a surface of a single PIC chip facing the substrate. Therefore, the original electronic integrated circuit of the semiconductor device is divided into a plurality of sub-integrated circuits and formed on a plurality of small EIC chips, then the EIC chips are inversely arranged on the PIC chip through the first bonding structure and are further packaged on the substrate through the second bonding structure near the EIC chip, and therefore, electric signals can be led out to the substrate through the first bonding structure of the EIC chip, the wiring circuit on the PIC chip and the second bonding structure near the EIC chip, overlong line transmission is avoided, unnecessary voltage drop is reduced, and the propagation time of the corresponding electric signals can be shortened.
Description
Technical Field
The present invention relates to the field of photonic semiconductor integrated circuits, and more particularly, to a semiconductor device and a method of manufacturing the same.
Background
In recent years, artificial intelligence technology has been rapidly developed, and some neural network algorithms involved therein require a large number of matrix operations. At present, it has been proposed to perform the above operations by photon computation using light as a carrier of information, and to realize light transmission, processing, computation, and the like by an optical device/chip.
In an existing scheme for realizing a photonic computing system, an Electronic Integrated Circuit (EIC) chip and a Photonic Integrated Circuit (PIC) chip need to be electrically connected, and because the chips are large, lines for connection are long. Due to the existence of the resistor, voltage drop generated after current flows through a long connecting circuit is not negligible, extra power consumption is caused, and the system cannot work normally due to excessive voltage drop. In addition, in an application scenario such as a photonic computing chip, in order to realize transmission and electrical connection of a large amount of data and signals, each of the EIC chip and the PIC chip has a plurality of connection bumps, and the large number of connection bumps corresponds to a large number of wiring lines, which further causes unnecessary voltage drop. In addition, the PIC chip sometimes needs to have optical coupling with the outside world, which has a great limitation on the integration of the semiconductor device as a whole.
Disclosure of Invention
The invention provides a semiconductor device and a manufacturing method thereof, which can effectively restrain voltage drop, optimize electric connection between PIC and EIC chips and optimize packaging size.
In one aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device, including:
providing a substrate;
providing a plurality of Electronic Integrated Circuits (EIC) chips;
providing at least one Photonic Integrated Circuits (PIC) chip having a first surface, the at least one PIC chip including a first PIC chip;
disposing a plurality of EIC chips on a first surface of the first PIC chip;
mounting a first PIC chip provided with a plurality of EIC chips on the substrate, a first surface of the first PIC chip facing the substrate.
In some embodiments of the invention, providing a plurality of EIC chips comprises:
providing a wafer, determining a plurality of areas on the wafer, wherein EIC chips are to be formed, and forming an electronic integrated circuit in each area;
thinning the wafer;
and cutting the wafer to form a plurality of EIC chips.
In some embodiments of the invention, providing a plurality of EIC chips comprises:
determining a total pattern of an electronic integrated circuit of the semiconductor device and cutting the total pattern into a plurality of sub-patterns;
providing a wafer;
determining a plurality of regions on the wafer in which EIC chips are to be formed;
respectively forming sub-integrated circuits on a plurality of EIC areas of the wafer according to the plurality of sub-patterns, and thinning the wafer;
and cutting the wafer according to the EIC areas to obtain a plurality of EIC chips, so that the sizes of the EIC chips are smaller than that of the EIC chips of the electronic integrated circuit formed according to the total pattern.
In some embodiments of the invention, the EIC chips are disposed on the first surface of the PIC chip by a first bonding structure.
In some embodiments of the present invention, the first bonding structure comprises a bump structure formed of solder. In some embodiments of the invention, disposing a plurality of EIC chips on a first surface of the first PIC chip comprises:
determining a plurality of EIC chip mounting areas on the first surface;
mounting the plurality of EIC chips on a plurality of EIC chip mounting areas on the first surface.
In some embodiments of the invention, the plurality of EIC chip mounting areas are defined by providing a second bonding structure on the first surface of the first PIC chip.
In some embodiments of the present invention, mounting a first PIC chip provided with a plurality of EIC chips on the substrate comprises:
mounting the first PIC chip on the substrate via the second bonding structure.
In some embodiments of the present invention, the second bonding structure comprises a solder ball.
In some embodiments of the invention, the EIC chip has a gap relative to the substrate.
In some embodiments of the invention, the method of manufacturing further comprises: and filling the gap with an encapsulating material.
In another aspect, an embodiment of the present invention provides a semiconductor device including a substrate, an EIC chip and a PIC chip, and the PIC chip is mounted on the substrate, the PIC chip having a first surface facing the substrate; wherein a plurality of the EIC chips are disposed on a first surface of a single PIC chip.
In some embodiments of the present invention, the semiconductor device includes a plurality of first bonding structures for electrically connecting the EIC chip and the PIC chip.
In some embodiments of the present invention, the semiconductor device includes a plurality of second bonding structures for electrically connecting the PIC chip with the substrate; at least one second bonding structure is arranged around at least one EIC chip.
In some embodiments of the present invention, the semiconductor device includes a plurality of second bonding structures for electrically connecting the PIC chip with the substrate; the plurality of EIC chips comprise a first EIC chip and a second EIC chip, and at least one second bonding structure exists between the first EIC chip and the second EIC chip.
In some embodiments of the present invention, the second bonding structure comprises a solder ball.
In some embodiments of the invention, the EIC chip has a gap relative to the substrate.
In some embodiments of the invention, the gap is filled with an encapsulation material.
In the invention, the original electronic integrated circuit of the semiconductor device is divided into a plurality of sub-integrated circuits and formed on a plurality of small-sized EIC chips, then the plurality of EIC chips are inversely arranged on the PIC chip through a first bonding structure, and then are further packaged on the substrate through a second bonding structure near the EIC chip. Therefore, the electric signal of the EIC chip can be introduced onto the substrate through the second bonding structure nearby, so that an overlong wiring line is avoided, unnecessary voltage drop is reduced, and the propagation time of the corresponding electric signal can be shortened.
The semiconductor device of the present invention may be a photonic computing semiconductor device, but is not limited thereto, and may be other semiconductor devices including EIC and PIC electrical connections having similar problems. Further, the components such as EIC and PIC in the present invention may be selected from semiconductor devices manufactured using silicon-based materials.
Various aspects, features, advantages, etc. of embodiments of the invention are described in detail below with reference to the accompanying drawings. The above aspects, features, advantages, etc. of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
Drawings
Fig. 1 is a schematic structural view of a semiconductor device according to an embodiment of the present invention;
fig. 2 shows a plan layout of an EIC chip of the semiconductor apparatus shown in fig. 1 on a PIC chip;
FIG. 3 is a side view of the semiconductor device shown in FIG. 1, as viewed from the short side of FIG. 2;
FIG. 4 is a flow chart of a method of fabricating a semiconductor device according to one embodiment of the present invention;
FIG. 5 shows an example of an EIC chip provided in the manufacturing method shown in FIG. 4;
fig. 6 shows an example of providing a bonding structure on a PIC chip in the manufacturing method shown in fig. 4;
fig. 7 shows an example of flip-chip mounting of an EIC chip on a PIC chip in the manufacturing method shown in fig. 4;
fig. 8 shows an example of mounting a PIC chip on a substrate in the manufacturing method shown in fig. 4;
fig. 9 is a schematic structural view of a semiconductor device of a comparative example;
FIG. 10 shows an example of a flow for providing the EIC chip of FIG. 4.
Detailed Description
To facilitate an understanding of the various aspects, features and advantages of the present inventive subject matter, reference is made to the following detailed description taken in conjunction with the accompanying drawings. It should be understood that the various embodiments described below are illustrative only and are not intended to limit the scope of the invention.
[ semiconductor device ]
Fig. 1 is a schematic structural view of a semiconductor device according to an embodiment of the present invention; fig. 2 shows a plan layout of an EIC chip of the semiconductor apparatus shown in fig. 1 on a PIC chip; fig. 3 is a side view of the semiconductor device shown in fig. 1, not showing the substrate, as viewed from the short side of fig. 2. Fig. 1 to 3 schematically show one example of a semiconductor device provided by the present invention.
In an embodiment of the present invention, a semiconductor device is a hybrid package device including a photonic integrated circuit and an electronic integrated circuit. As shown in fig. 1 to 3, the semiconductor apparatus includes six EIC chips 100 and a single PIC chip 200. The EIC chip is mounted on the first surface of the PIC chip 200 through a bump structure 101 as an example of a first bonding structure, the first surface of the PIC chip 200 faces the substrate 300, and a solder ball 201 as an example of a second bonding structure is provided around each EIC chip. The PIC chip 200 is mounted on a substrate 300 by a plurality of solder balls 201, thereby forming a hybrid package structure in which the six EIC chips 100 are flip-chip mounted on the PIC chip 200 and the PIC chip 200 is mounted on the surface of the substrate 300.
In an embodiment of the present invention, the size of each of the six EIC chips 100 is smaller than the size, which may be thickness or area, of a single EIC chip of an electronic integrated circuit in which the six EIC chips 100 are integrated. Thus, the six EIC chips 100 may also be referred to as chiplets, as compared to existing single EIC chips. In some embodiments of the present invention, the electronic integrated circuits configured for the semiconductor device may be divided into six sub-integrated circuits, and the six sub-integrated circuits may be formed on a wafer, and the wafer may be thinned and diced to form six EIC chiplets. In an alternative embodiment of the invention, the electronic integrated circuit of the arrangement may be divided into two sub-integrated circuits, and correspondingly, the semiconductor device may comprise two EIC chiplets. In other alternative embodiments of the present invention, the semiconductor device may include 3, 4, 5, or more than 7 EIC chiplets.
In one embodiment of the present invention, the bump structure 101 includes a connection bump or a solder bump, and the solder ball 201 is a tin-silver solder ball. The present invention is not limited thereto and the first and second bonding structures may employ suitable connecting structures known in the art.
Further, although the above illustrates the case of a plurality of (two or more) EIC chips, the semiconductor device structure can be applied to the case of only one EIC chip, and such a structural arrangement can obviously reduce the size of the device, reduce the area occupied by the substrate, and the like, and also optimize the electrical connection or wiring between the EIC and the PIC to some extent.
In one embodiment of the present invention, as shown in fig. 1, a through hole 301 is formed on a substrate 300, and a light guide structure 400 coupled to the PIC chip 200 penetrates through the through hole 301, wherein the light guide structure 400 is disposed on a first surface of the PIC chip 200. Thus, even if the flip chip structure according to the embodiment of the present invention is adopted, the optical signal can be conveniently input to the PIC chip through the light guide structure 400. Wherein, the light guiding structure can be an optical Fiber unit, and the optical Fiber unit can be an optical Fiber array (Fiber Arrays).
In some embodiments, the location of the through-hole 301 in fig. 1 is located at the edge of the substrate 300, but is not limited thereto, and in some embodiments, the through-hole may be located at other locations of the substrate. In some embodiments, the shape of the through hole is circular or square, and in some embodiments, may be an irregular pattern, and is not particularly limited.
In fig. 3, wiring lines of the PIC chip and the EIC chip are exemplarily shown. As shown in fig. 3, electrical signals (including information, data, control signals, and the like) of the EIC chip 100 are transmitted to the wiring lines 202 on the PIC chip 200 through the wiring lines 102 and the bump structures 101 electrically connected to the wiring lines 102, further transmitted to the solder balls 201 near the EIC chip 100, and enter the substrate through the solder balls 201. Therefore, the overlong wiring is avoided, unnecessary voltage drop is reduced, and the propagation time of the electric signal can be shortened.
In an embodiment of the present invention, the height of the solder ball 201 protruding from the PIC chip 200 is greater than the thickness of the EIC chip 100, so that the EIC chip 100 is spaced apart from the substrate 300 with a gap. Therefore, ventilation and heat dissipation of the EIC chip are facilitated. In an alternative embodiment of the invention, the gap is filled with an encapsulation material, whereby the connection of the EIC chip to the PIC chip can be made more stable. In addition, the packaging material can also be provided with a heat dissipation material.
[ METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE ]
FIG. 4 is a flow chart of a method of fabricating a semiconductor device according to one embodiment of the present invention; FIG. 5 shows an example of an EIC chip provided in the manufacturing method shown in FIG. 4; fig. 6 shows an example of providing a bonding structure on a PIC chip in the manufacturing method shown in fig. 4; fig. 7 shows an example of flip-chip mounting of an EIC chip on a PIC chip in the manufacturing method shown in fig. 4; fig. 8 shows an example of mounting a PIC chip on a substrate in the manufacturing method shown in fig. 4.
An example of a method for manufacturing a semiconductor device according to the present invention will be described with reference to fig. 4 to 8.
As shown in fig. 4, a method of manufacturing a semiconductor device according to an embodiment of the present invention includes:
s101, providing a substrate;
s102, providing a plurality of EIC chips;
s103, providing at least one PIC chip, wherein the PIC chip is provided with a first surface, and the at least one PIC chip comprises a first PIC chip;
s104, arranging a plurality of EIC chips on a first surface of the first PIC chip;
s105 mounting a first PIC chip provided with a plurality of EIC chips on the substrate with a first surface of the first PIC chip facing the substrate.
In one embodiment of the present invention, as shown in fig. 10, the providing a plurality of EIC chips in the step S102 includes:
s102a, providing a wafer, determining a plurality of areas on the wafer where EIC chips are to be formed, and forming an electronic integrated circuit in each area;
s102b, thinning the wafer;
and S102c, cutting the wafer to form a plurality of EIC chips.
In one embodiment, S102 may include determining a total pattern of an electronic integrated circuit of the semiconductor device and dividing the total pattern into a plurality of sub-patterns, wherein the total pattern refers to an electronic integrated circuit pattern set based on a function of the semiconductor device; and cutting the wafer according to the EIC areas to obtain a plurality of EIC chips, so that the size of each EIC chip is smaller than that of the EIC chip for forming the electronic integrated circuit according to the total pattern.
Fig. 5 shows an example of an EIC chip obtained by cutting, a bump structure 101 is formed on a wiring line layer of the EIC chip 100 by solder, and the bump structure 101 is electrically connected to a wiring line 102 of the EIC chip 100. In alternative embodiments of the present invention, other bonding structures known in the art may be used in place of the bump structure; bonding of the PIC to the EIC may also be accomplished in other ways.
In one embodiment of the present invention, the disposing a plurality of EIC chips on a single PIC chip (first PIC chip) in the process S104 includes:
a plurality of EIC chip mounting areas are defined on the first surface of the PIC chip facing the substrate, for example, as shown in fig. 6, a plurality of solder balls 201 are formed on the first surface of the PIC chip 200, the area enclosed by the solder balls 201 is the EIC chip mounting area (refer back to fig. 2), and the solder balls 201 are electrically connected to the wiring lines 202 in the PIC chip 200;
as shown in fig. 7, the plurality of EIC chips 100 are mounted on a plurality of EIC chip mounting areas on the PIC chip 200 (refer back to fig. 2), and the bump structures 101 of the EIC chips 100 are electrically connected to the wiring lines 202 on the PIC chip 200.
In one embodiment of the present invention, in step S105, the PIC chip 200 is mounted on the substrate 300 by the solder balls 201. Thus, a hybrid package structure is formed in which a plurality of EIC chips 100 are flip-chip mounted on a single PIC chip 200 and the PIC chip 200 is mounted on a substrate 300. In alternative embodiments of the present invention, other bonding structures known in the art may be used in place of the solder balls.
In one embodiment of the invention, a height of the solder balls protruding from the PIC chip is greater than a thickness of the EIC chip, such that the EIC chip has a gap with respect to the substrate. In an alternative embodiment, the gap may be filled with an encapsulating material (not shown).
The semiconductor device according to the embodiment of the present invention and the method for manufacturing the same are explained in detail above, and the advantages of the semiconductor device according to the embodiment of the present invention will be explained below with reference to comparative examples.
Fig. 9 shows a structure example of a semiconductor device of a comparative example. In the comparative example, PIC chip 200 'is mounted on substrate 300', and one EIC chip 100 'is mounted on the upper surface of PIC chip 200', and the current path or signal transmission path from EIC chip 100 'to substrate 300' is schematically shown by the dotted arrows in fig. 9. According to the comparative example shown in fig. 9, an electrical signal enters the wiring lines of the PIC chip 200 'from the EIC chip 100' through the bonding structure, and is transmitted to the off-chip wires 500 'via the wiring lines of the PIC chip 200', and enters the substrate 300 'through the off-chip wires 500'. In addition, because a single EIC chip is large, the circuit for connection is long, and because of the existence of the resistor, a large voltage drop is generated after current flows through a long connection circuit.
In the embodiment of the present invention, as shown in fig. 1 and 8, the single EIC chip shown in fig. 9 is divided into a plurality of EIC chips 100, and the bump structures 101 of the EIC chips 100 are connected with the wiring structures on the PIC chip 200, so that the electrical signals from the EIC chips 100 can be connected to the substrate 300 through the solder balls 201 near the EIC chips 100. Compared with the comparative example, the transmission path of the embodiment of the invention is much shorter, the electric signal is prevented from flowing through a long circuit, unnecessary voltage drop is reduced, and the propagation time of the signal is shortened. In addition, optionally, the EIC chips and PIC chips in the invention can adopt silicon-based chips, and since the EIC chips and the PIC chips adopt semiconductor devices with the same base material, the stress mismatch between the EIC chips and the PIC chips can be reduced, and the warpage is reduced.
It should be understood by those skilled in the art that the foregoing is only illustrative of the present invention, and is not intended to limit the scope of the invention. For example, in an alternative embodiment of the present invention, the semiconductor device may include at least two PIC chips, and a plurality of EIC chips are flip-chip mounted on at least one PIC chip.
Claims (13)
1. A method of manufacturing a semiconductor device, the method comprising:
providing a substrate;
providing a plurality of electronic integrated circuit EIC chips;
providing at least one Photonic Integrated Circuit (PIC) chip, wherein the PIC chip has a first surface, and the at least one PIC chip comprises a first PIC chip;
disposing a plurality of EIC chips on a first surface of the first PIC chip;
mounting a first PIC chip provided with a plurality of EIC chips on the substrate, a first surface of the first PIC chip facing the substrate.
2. The method of manufacturing of claim 1, wherein providing a plurality of EIC chips comprises:
providing a wafer, determining a plurality of areas on the wafer, wherein EIC chips are to be formed, and forming an electronic integrated circuit in each area;
thinning the wafer;
and cutting the wafer to form a plurality of EIC chips.
3. The method of manufacturing of claim 1, wherein providing a plurality of EIC chips comprises:
determining a total pattern of an electronic integrated circuit of the semiconductor device and cutting the total pattern into a plurality of sub-patterns;
providing a wafer;
determining a plurality of regions on the wafer in which EIC chips are to be formed;
respectively forming sub-integrated circuits on a plurality of EIC areas of the wafer according to the plurality of sub-patterns, and thinning the wafer;
and cutting the wafer according to the EIC areas to obtain a plurality of EIC chips, so that the sizes of the EIC chips are smaller than that of the EIC chips of the electronic integrated circuit formed according to the total pattern.
4. The method of manufacturing of claim 1, wherein the plurality of EIC chips are disposed on the first surface of the first PIC chip by a first bond structure.
5. The manufacturing method according to claim 1, wherein mounting a first PIC chip provided with a plurality of EIC chips on the substrate comprises:
the first PIC chip is mounted on the substrate by a second bonding structure.
6. The method of manufacturing of claim 1, wherein the EIC chip has a gap relative to the substrate.
7. The method of manufacturing of claim 6, further comprising: and filling the gap with an encapsulating material.
8. A semiconductor device, comprising:
a substrate;
an Electronic Integrated Circuit (EIC) chip;
a Photonic Integrated Circuit (PIC) chip mounted on the substrate, the PIC chip having a first surface facing the substrate;
wherein a plurality of the EIC chips are disposed on a first surface of a single PIC chip.
9. The semiconductor device of claim 8, comprising a plurality of first bond structures to electrically connect the EIC chip with the PIC chip.
10. The semiconductor device according to claim 8 or 9, comprising a plurality of second bonding structures for electrically connecting the PIC chip with the substrate; at least one second bonding structure is arranged around at least one EIC chip.
11. The semiconductor device according to claim 8 or 9, comprising a plurality of second bonding structures for electrically connecting the PIC chip with the substrate; the plurality of EIC chips comprise a first EIC chip and a second EIC chip, and at least one second bonding structure exists between the first EIC chip and the second EIC chip.
12. The semiconductor device according to claim 10, wherein the EIC chip has a gap with respect to the substrate.
13. The semiconductor device of claim 12, wherein the gap is filled with an encapsulation material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110480443.5A CN113192937A (en) | 2021-04-30 | 2021-04-30 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110480443.5A CN113192937A (en) | 2021-04-30 | 2021-04-30 | Semiconductor device and method for manufacturing the same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113985533A (en) * | 2021-10-18 | 2022-01-28 | 上海曦智科技有限公司 | Photonic semiconductor device and method for manufacturing the same |
| CN114063229A (en) * | 2021-09-30 | 2022-02-18 | 上海曦智科技有限公司 | Semiconductor device with a plurality of semiconductor chips |
Citations (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100249539B1 (en) * | 1994-09-30 | 2000-03-15 | 가네꼬 히사시 | A semiconductor chip and a method of manufacturing the same |
| US6150724A (en) * | 1998-03-02 | 2000-11-21 | Motorola, Inc. | Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces |
| JP2002031747A (en) * | 2000-07-18 | 2002-01-31 | Canon Inc | Planar optical element mounted body, its manufacturing method, and device using it |
| US20080044128A1 (en) * | 2001-10-09 | 2008-02-21 | Infinera Corporation | TRANSMITTER PHOTONIC INTEGRATED CIRCUITS (TxPICs) AND OPTICAL TRANSPORT NETWORK SYSTEM EMPLOYING TxPICs |
| US20080075405A1 (en) * | 2006-09-19 | 2008-03-27 | Ibiden Co., Ltd | Optical interconnect device and method for manufacturing the same |
| US20120207426A1 (en) * | 2011-02-16 | 2012-08-16 | International Business Machines Corporation | Flip-chip packaging for dense hybrid integration of electrical and photonic integrated circuits |
| CN104037124A (en) * | 2013-03-08 | 2014-09-10 | 新科金朋有限公司 | Semiconductor Device And Method Of Forming Embedded Conductive Layer For Power/ground Planes In Fo-ewlb |
| US8971676B1 (en) * | 2013-10-07 | 2015-03-03 | Oracle International Corporation | Hybrid-integrated photonic chip package |
| US20150153524A1 (en) * | 2013-12-03 | 2015-06-04 | Forelux Inc. | Integrated optoelectronic module |
| US20150241631A1 (en) * | 2014-02-21 | 2015-08-27 | Aurrion, Inc. | Optical and thermal interface for photonic integrated circuits |
| US20160085038A1 (en) * | 2014-09-22 | 2016-03-24 | Oracle International Corporation | Integrated chip package with optical interface |
| US20180188448A1 (en) * | 2016-12-31 | 2018-07-05 | Intel Corporation | In-package photonics integration and assembly architecture |
| CN108780789A (en) * | 2016-03-31 | 2018-11-09 | 英特尔公司 | Optoelectronic transceiver device assembly |
| US10139564B1 (en) * | 2015-01-28 | 2018-11-27 | National Technology & Engineering Solutions Of Sandia, Llc | Vertically integrated optoelectronics package for MEMS devices |
| US10162139B1 (en) * | 2017-07-27 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semicondcutor package |
| US20190006549A1 (en) * | 2016-04-01 | 2019-01-03 | Intel Corporation | Optoelectronic device module having a silicon interposer |
| US20190103386A1 (en) * | 2017-09-29 | 2019-04-04 | Advanced Semiconductor Engineering, Inc. | Stacked semiconductor package assemblies including double sided redistribution layers |
| US20190324223A1 (en) * | 2016-12-29 | 2019-10-24 | Intel Corporation | Photonic engine platform utilizing embedded wafer level packaging integration |
| US20190326266A1 (en) * | 2018-04-24 | 2019-10-24 | Cisco Technology, Inc. | Integrated circuit bridge for photonics and electrical chip integration |
| CN111128749A (en) * | 2018-10-31 | 2020-05-08 | 中芯集成电路（宁波）有限公司 | Wafer level packaging method using lithographically bondable material |
| US20200365544A1 (en) * | 2019-05-15 | 2020-11-19 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure |
-
2021
- 2021-04-30 CN CN202110480443.5A patent/CN113192937A/en active Pending
Patent Citations (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100249539B1 (en) * | 1994-09-30 | 2000-03-15 | 가네꼬 히사시 | A semiconductor chip and a method of manufacturing the same |
| US6150724A (en) * | 1998-03-02 | 2000-11-21 | Motorola, Inc. | Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces |
| JP2002031747A (en) * | 2000-07-18 | 2002-01-31 | Canon Inc | Planar optical element mounted body, its manufacturing method, and device using it |
| US20080044128A1 (en) * | 2001-10-09 | 2008-02-21 | Infinera Corporation | TRANSMITTER PHOTONIC INTEGRATED CIRCUITS (TxPICs) AND OPTICAL TRANSPORT NETWORK SYSTEM EMPLOYING TxPICs |
| US20080075405A1 (en) * | 2006-09-19 | 2008-03-27 | Ibiden Co., Ltd | Optical interconnect device and method for manufacturing the same |
| US20120207426A1 (en) * | 2011-02-16 | 2012-08-16 | International Business Machines Corporation | Flip-chip packaging for dense hybrid integration of electrical and photonic integrated circuits |
| CN104037124A (en) * | 2013-03-08 | 2014-09-10 | 新科金朋有限公司 | Semiconductor Device And Method Of Forming Embedded Conductive Layer For Power/ground Planes In Fo-ewlb |
| US8971676B1 (en) * | 2013-10-07 | 2015-03-03 | Oracle International Corporation | Hybrid-integrated photonic chip package |
| US20150153524A1 (en) * | 2013-12-03 | 2015-06-04 | Forelux Inc. | Integrated optoelectronic module |
| US20150241631A1 (en) * | 2014-02-21 | 2015-08-27 | Aurrion, Inc. | Optical and thermal interface for photonic integrated circuits |
| US20160085038A1 (en) * | 2014-09-22 | 2016-03-24 | Oracle International Corporation | Integrated chip package with optical interface |
| US10139564B1 (en) * | 2015-01-28 | 2018-11-27 | National Technology & Engineering Solutions Of Sandia, Llc | Vertically integrated optoelectronics package for MEMS devices |
| CN108780789A (en) * | 2016-03-31 | 2018-11-09 | 英特尔公司 | Optoelectronic transceiver device assembly |
| US20190006549A1 (en) * | 2016-04-01 | 2019-01-03 | Intel Corporation | Optoelectronic device module having a silicon interposer |
| US20190324223A1 (en) * | 2016-12-29 | 2019-10-24 | Intel Corporation | Photonic engine platform utilizing embedded wafer level packaging integration |
| US20180188448A1 (en) * | 2016-12-31 | 2018-07-05 | Intel Corporation | In-package photonics integration and assembly architecture |
| US10162139B1 (en) * | 2017-07-27 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semicondcutor package |
| US20190103386A1 (en) * | 2017-09-29 | 2019-04-04 | Advanced Semiconductor Engineering, Inc. | Stacked semiconductor package assemblies including double sided redistribution layers |
| US20190326266A1 (en) * | 2018-04-24 | 2019-10-24 | Cisco Technology, Inc. | Integrated circuit bridge for photonics and electrical chip integration |
| CN111128749A (en) * | 2018-10-31 | 2020-05-08 | 中芯集成电路（宁波）有限公司 | Wafer level packaging method using lithographically bondable material |
| US20200365544A1 (en) * | 2019-05-15 | 2020-11-19 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114063229A (en) * | 2021-09-30 | 2022-02-18 | 上海曦智科技有限公司 | Semiconductor device with a plurality of semiconductor chips |
| CN114063229B (en) * | 2021-09-30 | 2023-06-16 | 上海曦智科技有限公司 | Semiconductor device with a semiconductor device having a plurality of semiconductor chips |
| CN113985533A (en) * | 2021-10-18 | 2022-01-28 | 上海曦智科技有限公司 | Photonic semiconductor device and method for manufacturing the same |
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