CN113191115A - Programmable arbitrary power divider based on DBS algorithm - Google Patents
Programmable arbitrary power divider based on DBS algorithm Download PDFInfo
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- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
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Abstract
The application relates to a programmable arbitrary power divider based on DBS algorithm. The power divider is designed on a silicon substrate and comprises: the multimode waveguide comprises a multimode input waveguide, two multimode output waveguides and an optimized design area; the optimization design area comprises a signal enhancement area and a power control area; the signal enhancement zone is a symmetrical structure, the state of each unit cell in the signal enhancement zone is calculated through a DBS algorithm, and the states of the unit cells in the signal enhancement zone comprise: no perforation or first central hole; the first central hole is filled with air; the power control area is of an asymmetric structure, the state of each unit cell in the power control area is calculated through a DBS algorithm, and the state of each unit cell in the power control area is a second central hole; the second central hole is filled with GSST; the state of the GSST is changed by external electricity to realize any power splitting ratio; the states of GSST include: a-GSST amorphous state and c-GSST crystalline state. Any power splitting ratio can be realized by adopting the any power divider.
Description
Technical Field
The application relates to the technical field of power devices, in particular to a programmable arbitrary power divider based on a DBS algorithm.
Background
In recent years, with the development of silicon photonics and manufacturing techniques thereof, photonic integrated circuits have been receiving more and more attention. Power splitters are widely used in many optical circuits as one of the most basic devices in integrated photonic systems on chip. The power divider is generally used for power division and power combination, and is mainly applied to radio frequency circuits such as balanced power amplifiers, balanced mixers, antenna arrays and the like. Conventional multimode interferometer based power splitters are widely used due to their reasonable package footprint and ease of fabrication. But the structure size is large, the cost is high, and only the average distribution of power can be realized because of the symmetrical structure. Compared with the traditional power divider, the power divider capable of realizing any power ratio is more attractive, and has wider application range, such as feedback circuits, tap port power monitoring and the like. However, achieving an arbitrary splitting ratio is a challenge, especially for multiple output devices. Therefore, it is a problem to be solved at present to find an arbitrary power divider with excellent performance and low cost.
With the extensive research of algorithms in recent years, a plurality of devices designed based on the algorithms break through the symmetrical structure of the traditional device, and further, the superior performance of the power divider compared with the traditional power divider is realized. Ke Xu et al originally utilized DBS algorithms for on-chip arbitrary power divider optimization [ K.xu, L.Liu, X.Wen, W.Sun, N.Zhang, N.Yi, S.Sun, S.Xiao, and Q.Song, "Integrated Phonic power divider with allocation power rates," Optics letter.42, 855(2017) ]. However, the arbitrary power distribution based on the algorithm cannot change the splitting ratio, the air holes are drilled on the silicon structure, the splitting ratio of the power is realized on the fixed structure, one structure can only realize one splitting ratio, and if the power distribution of another ratio is realized, a device needs to be prepared again, so that the cost is very high, and certain obstacles exist for the effective integration of the photonic integrated circuit.
Disclosure of Invention
In view of the foregoing, it is necessary to provide a programmable arbitrary power divider based on DBS algorithm capable of solving arbitrary power splitting ratio.
A programmable arbitrary power divider based on DBS algorithm, the power divider being designed on a silicon substrate, comprising: the multimode waveguide comprises a multimode input waveguide, two multimode output waveguides and an optimized design area;
the optimal design area comprises a signal enhancement area and a power control area; the optimized design area consists of a plurality of unit cells;
the signal enhancement region is of a symmetrical structure, the state of each unit cell in the signal enhancement region is calculated through a DBS algorithm, and the state of each unit cell in the signal enhancement region comprises: no perforation or first central hole; the first central hole is filled with air;
the power control area is of an asymmetric structure, the state of each unit cell in the power control area is calculated through a DBS algorithm, and the state of each unit cell in the power control area is a second central hole; the second central hole is filled with GSST; the state of the GSST is changed by external electricity to realize any power splitting ratio; wherein the state of the GSST includes: a-GSST amorphous state and c-GSST crystalline state.
In one embodiment, the method further comprises the following steps: randomly setting the state of the cell; the first center hole or the second center hole represents 0, and no hole represents 1;
setting a target function according to the transmittances of the two multimode output waveguides;
and changing the state of each cell one by one, if the output value of the target function is increased, keeping the state of the pixel points, otherwise, setting the state as an original value until the maximum value of the target function is reached, and determining the state of the cells.
In one embodiment, the objective function of the signal enhancement zone is set according to the transmittance of the two multimode output waveguides as:
FOM1＝T1＝T2
wherein, T1 and T2 are transmittance in the preset input light source mode, and FOM1 represents the objective function of the signal enhancement region.
In one embodiment, setting the objective function based on the transmittances of two multimode output waveguides comprises:
setting the objective function of the power control region as follows according to the transmittances of the two multimode output waveguides:
FOM2＝-abs(α*T1-T2)
wherein T1 and T2 are transmittance in a preset input light source mode, FOM2 represents an objective function of a signal enhancement region, α is a proportionality coefficient of two multimode output waveguides, and abs (·) represents an absolute value in parentheses.
In one embodiment, the sub-power splitter is further connected to a uniform output power splitter, so as to obtain a combined power splitter.
In one embodiment, the area of the optimized region is 2.4 μm x 2.4.4 μm.
In one embodiment, the optimal design area comprises 20 columns and 20 rows, wherein the number of the unit cells is 20 × 20.
In one embodiment, the number of the unit cells in the signal enhancement region is 20 × 16 in the first 16 columns.
In one embodiment, the number of the unit cells in the power control region is 20 × 4 in the last 4 columns.
In one embodiment, the first central hole or the second central hole is a circular hole with a diameter of 90nm and a depth of 220 nm.
The programmable arbitrary power divider based on the DBS algorithm can realize different power splitting ratios on one device, and has high efficiency and low cost. Only a small part of the phase change material GSST needs to be filled at the end of a design area, the phase change material GSST is optimized based on the programmable characteristic of a DBS algorithm, and the splitting ratio of any proportion can be realized in the wavelength range of 1530nm-1560nm by regulating and controlling the state (crystalline state or amorphous state) of the GSST. Compared with the traditional device, the structure of the device is several orders of magnitude smaller, the size is very small, and the structure is simple.
Drawings
FIG. 1 is a three-dimensional block diagram of a programmable arbitrary power divider based on DBS algorithm in one embodiment;
fig. 2 is a schematic diagram of an arbitrary power divider when α is 1.5 in one embodiment; wherein, (a) represents a two-dimensional structure diagram of an arbitrary power divider when α is 1.5, and (b) represents a split ratio curve when α is 1.5;
fig. 3 is a schematic diagram of an arbitrary power divider when α is 2.5 in one embodiment; wherein, (a) represents a two-dimensional structure diagram of an arbitrary power divider when α is 2.5, and (b) represents a split ratio curve when α is 2.5.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In one embodiment, there is provided a programmable arbitrary power divider based on DBS algorithm, the power divider being designed on a silicon substrate, comprising: the optical waveguide structure comprises a multimode input waveguide, two multimode output waveguides and an optimized design area, specifically as shown in fig. 1, the left side is the multimode input waveguide, the right side is the multimode output waveguides, and the middle part is the optimized design area.
The optimization design area comprises a signal enhancement area and a power control area; the optimal design area is composed of a plurality of unit cells.
The signal enhancement region is of a symmetric structure, the left side of the optimal design region in fig. 1 shows, the state of each cell in the signal enhancement region is calculated by the DBS algorithm, and the states of the cells in the signal enhancement region include: no perforation or first central hole; the first central hole is filled with air. The signal enhancement region is used for equally dividing the power and transmitting the power to the power control region, and the transmission efficiency is high.
The power control area is of an asymmetric structure, as shown on the right side of the optimized design area in fig. 1, the state of each unit cell in the power control area is calculated through a DBS algorithm, and the state of each unit cell in the power control area is a second center hole; the second central hole is filled with GSST; the state of the GSST is changed by external electricity to realize any power splitting ratio; wherein the state of the GSST includes: a-GSST amorphous state and c-GSST crystalline state. The GSST is a phase change material, when the GSST is in different states, light is output from different output ports, and the output ports of the light can be changed by changing the GSST, so that different power splitting ratios are realized.
The programmable arbitrary power divider based on the DBS algorithm can realize different power splitting ratios on one device, and has high efficiency and low cost. Only a small part of the phase change material GSST needs to be filled at the end of a design area, the phase change material GSST is optimized based on the programmable characteristic of a DBS algorithm, and the splitting ratio of any proportion can be realized in the wavelength range of 1530nm-1560nm by regulating and controlling the state (crystalline state or amorphous state) of the GSST. Compared with the traditional device, the structure of the device is several orders of magnitude smaller, the size is very small, and the structure is simple.
In one embodiment, the step of the DBS algorithm comprises:
randomly setting the state of the cell; the first center hole or the second center hole represents 0, and no hole represents 1; setting a target function according to the transmittances of the two multimode output waveguides; and changing the state of each cell one by one, if the output value of the target function is increased, keeping the state of the pixel points, otherwise, setting the state as an original value until the maximum value of the target function is reached, and determining the state of the cells.
Specifically, not perforated indicates that silicon is retained.
In one embodiment, the objective function of the signal enhancement zone is set according to the transmittance of the two multimode output waveguides as:
FOM1＝T1＝T2
wherein, T1 and T2 are transmittance in the preset input light source mode, and FOM1 represents the objective function of the signal enhancement region. The preset input light source mode may be a TE0 mode. And perforating through a column-column scanning until the objective function converges. By the design, the transmission efficiency of the signal enhancement area is more than 94%.
In another embodiment, the objective function for setting the power control region is based on the transmission of two multimode output waveguides:
FOM2＝-abs(α*T1-T2)
wherein T1 and T2 are transmittance in a preset input light source mode, FOM2 represents an objective function of a signal enhancement region, α is a proportionality coefficient of two multimode output waveguides, and abs (·) represents an absolute value in parentheses. The preset input light source mode may be a TE0 mode.
The transmission performance of the device when α ═ 1.5 and α ═ 2.5 are discussed below. As shown in fig. 2 and 3, a strict power splitting ratio can be achieved.
In fig. 2(a), a two-dimensional structure diagram of an arbitrary power divider when α is 1.5 is given, and in fig. 2(b), a splitting ratio curve when α is 1.5 is given.
In fig. 3(a), a two-dimensional structure diagram of an arbitrary power divider when α is 2.5 is given, and a splitting ratio curve when α is 2.5 is given in fig. 3 (b).
In one embodiment, the area of the optimized region is 2.4 μm x 2.4.4 μm.
In another embodiment, the optimal design area includes 20 columns and 20 rows, wherein the number of cells is 20 × 20.
In one embodiment, the number of cells in the signal enhancement region is 20 × 16 in the first 16 columns.
In another embodiment, the number of cells in the power control region is 20 × 4 in the last 4 columns.
In yet another embodiment, the first central hole or the second central hole is a circular hole having a diameter of 90nm and a depth of 220 nm.
In summary, the arbitrary power divider is designed on a 220nm thick top silicon-on-insulator (SOI) platform. The device consists of a multimode input waveguide, two multimode output waveguides and an optimized design area. The optimized design area is divided into 20x20 square cells, and each cell is in a state of no punching or a right center round hole; the radius of the pores was 45nm and the depth of the pores was 220 nm. The determination of the state of each cell is as follows: and calculating the state of each cell according to the DBS algorithm and the set target function so as to enable the target function to reach the maximum value. The step of calculating the state of each cell according to the DBS algorithm and the set objective function so that the objective function reaches a maximum value includes: sequentially scanning each cell in the optimized design area, changing the state of the scanned cell, calculating a current objective function, comparing the current objective function with an objective function value when the state of the cell is not changed, if the current objective function value is improved, keeping the new state of the scanned cell, otherwise, restoring the original state of the cell.
In calculating the state of each cell of the optimal design area by using the DBS algorithm, a column-by-column scanning mode is used. When scanning in columns, the scanning direction is from top to bottom in the vertical direction, and from left to right in the horizontal direction (scanning calculation is performed in a column from left to right). Scanning each cell in the optimization area in sequence, changing the state of the scanned cell, calculating an objective function, comparing the objective function value with the objective function value when the state of the cell is not changed, if the objective function value is improved, keeping the new state of the scanned cell, otherwise, restoring the original state of the cell.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (9)
1. A programmable arbitrary power divider based on DBS algorithm, wherein the power divider is designed on a silicon substrate, comprising: the multimode waveguide comprises a multimode input waveguide, two multimode output waveguides and an optimized design area;
the optimal design area comprises a signal enhancement area and a power control area; the optimized design area consists of a plurality of unit cells;
the signal enhancement region is of a symmetrical structure, the state of each unit cell in the signal enhancement region is calculated through a DBS algorithm, and the state of each unit cell in the signal enhancement region comprises: no perforation or first central hole; the first central hole is filled with air;
the power control area is of an asymmetric structure, the state of each unit cell in the power control area is calculated through a DBS algorithm, and the state of each unit cell in the power control area is a second central hole; the second central hole is filled with GSST; the state of the GSST is changed by external electricity to realize any power splitting ratio; wherein the state of the GSST includes: a-GSST amorphous state and c-GSST crystalline state.
2. A programmable arbitrary power divider based on DBS algorithm as claimed in claim 1, wherein said DBS algorithm step comprises:
randomly setting the state of the cell; the first center hole or the second center hole represents 0, and no hole represents 1;
setting a target function according to the transmittances of the two multimode output waveguides;
and changing the state of each cell one by one, if the output value of the target function is increased, keeping the state of the pixel points, otherwise, setting the state as an original value until the maximum value of the target function is reached, and determining the state of the cells.
3. A programmable arbitrary power divider based on DBS algorithm according to claim 2, wherein setting the objective function according to the transmittance of two multimode output waveguides comprises:
according to the transmittance of the two multimode output waveguides, the objective function of the signal enhancement region is set as follows:
FOM1＝T1＝T2
wherein, T1 and T2 are transmittance in the preset input light source mode, and FOM1 represents the objective function of the signal enhancement region.
4. A programmable arbitrary power divider based on DBS algorithm according to claim 2, wherein setting the objective function according to the transmittance of two multimode output waveguides comprises:
setting the objective function of the power control region as follows according to the transmittances of the two multimode output waveguides:
FOM2＝-abs(α*T1-T2)
wherein T1 and T2 are transmittance in a preset input light source mode, FOM2 represents an objective function of a signal enhancement region, α is a proportionality coefficient of two multimode output waveguides, and abs (·) represents an absolute value in parentheses.
5. Programmable arbitrary power divider based on DBS algorithm according to any of claims 1 to 4 characterized in that the area of the optimized region is 2.4 μm x 2.4.4 μm.
6. A programmable arbitrary power divider based on DBS algorithm as defined in claim 5, wherein said optimal design area comprises 20 columns and 20 rows, and wherein the number of cells is 20x 20.
7. A programmable arbitrary power divider based on DBS algorithm as claimed in claim 6, wherein the number of cells in the signal enhancement region is 20x 16 in the first 16 columns.
8. A programmable arbitrary power divider based on DBS algorithm as claimed in claim 6, wherein the number of cells in the power control region is 20x 4 in the last 4 columns.
9. A programmable arbitrary power divider based on DBS algorithm as claimed in any of the claims 6-8, wherein said first or said second central hole is a circular hole with a diameter of 90nm and a depth of 220 nm.
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