CN113178175B - GOA circuit and display panel - Google Patents
GOA circuit and display panel Download PDFInfo
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- CN113178175B CN113178175B CN202110357066.6A CN202110357066A CN113178175B CN 113178175 B CN113178175 B CN 113178175B CN 202110357066 A CN202110357066 A CN 202110357066A CN 113178175 B CN113178175 B CN 113178175B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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Abstract
The embodiment of the application discloses and provides a GOA circuit and a display panel. The GOA circuit comprises a plurality of cascaded GOA units, and at least one GOA unit comprises: a precharge module for precharging the potential of the first node to a first high potential at a first node potential rising stage; the excitation module is used for exciting the potential of the first node from a first high potential to a second high potential in the potential rising stage of the first node; and the scanning signal generating module is used for raising the potential of the first node from the second high potential to the peak value high potential at the first node potential raising stage and outputting the nth-level scanning signal. The embodiment of the application can solve the problems of insufficient capability and insufficient margin of the GOA circuit unit for improving the potential of the first node Qn, and improves the problem of reliability reduction.
Description
Technical Field
The application relates to the field of display, in particular to a GOA circuit and a display panel.
Background
A Gate Driver On Array (GOA), i.e., a driving method for scanning a scan line (Gate) line by fabricating a line scan driving signal circuit On an Array substrate using a Thin Film Transistor (TFT) Array (Array) process of a conventional liquid crystal display. Because the GOA technology can save the scan driver chip (Gate IC), realize the narrow border (narrow border), and so on, the GOA technology is widely applied to the panel design at present.
Fig. 1 is a schematic diagram of a GOA unit in the prior art, where the GOA unit includes a pre-charge module 100, a scan signal generation module 200, a level signaling signal generation module 300, a bootstrap module 400, a reset module 500, a pull-down module 600, and a pull-down maintenance module 700, and fig. 2 is a diagram illustrating a change of a potential of a first node Qn in fig. 1 with an operation of the GOA unit. In the rising period T1, the potential of the first node Qn is raised from the low potential L11 to the first high potential L12, and then raised from the first high potential L12 to the peak high potential L14; in the potential falling period T2, the potential of the first node Qn is pulled down from the peak high potential L14 to the first low potential L21, and then pulled down from the first low potential L21 to the low potential L23. However, the potential of the first node Qn is pulled up from the first high potential L12 to the peak high potential L14, which occupies an excessive potential boosting capability of the GOA cell, and sometimes the potential of the first node Qn cannot be pulled up from the first high potential L12 to the peak high potential L14 of the target value, or the GOA cell exceeds the capability of the thin film transistor after the potential of the first node Qn is pulled up from the first high potential L12 to the peak high potential L14, and the thin film transistor of the GOA cell does not have a sufficient margin for the potential boosting of the first node Qn, which results in a reduction in the lifetime of the GOA cell and a reduction in reliability.
Disclosure of Invention
The embodiment of the application provides a GOA circuit and a display panel, which can solve the problems of insufficient capability and insufficient allowance of a GOA circuit unit for improving the potential of a first node Qn and improve the problem of reliability reduction.
The embodiment of the application provides a GOA circuit, including a plurality of cascaded GOA units, at least one GOA unit includes:
a precharge module, configured to precharge a potential of a first node to a first high potential in a first node potential rising stage;
the excitation module is used for exciting the potential of the first node from the first high potential to a second high potential in the potential rising stage of the first node;
and the scanning signal generating module is used for raising the potential of the first node from the second high potential to a peak high potential at the first node potential raising stage and outputting an nth-level scanning signal.
Optionally, in some embodiments of the present application, the excitation module includes:
the excitation capacitor comprises a first excitation capacitor end and a second excitation capacitor end, and the first excitation capacitor end is electrically connected with the first node; and
a driver transistor sub-module comprising: the input end is electrically connected with the (n-1) th-level clock signal; the driving end is electrically connected with the first node or electrically connected with the (n-2) th level signal; and the output end is electrically connected with the second excitation capacitor end.
Optionally, in some embodiments of the present application, the driver transistor sub-module includes a driver transistor.
Optionally, in some embodiments of the present application, an output end of the precharge module is electrically connected to the first node, a driving end of the scan signal generation module is electrically connected to the first node, an input end of the scan signal generation module is electrically connected to the nth stage clock signal, and an output end of the scan signal generation module outputs the nth stage scan signal.
Optionally, in some embodiments of the present application, the GOA unit further includes a level signaling generation module, a driving end of the level signaling generation module is electrically connected to the first node, an input end of the level signaling generation module is electrically connected to the nth level clock signal, and an output end of the level signaling generation module outputs the nth level signaling.
Optionally, in some embodiments of the present application, the GOA unit further includes a reset module, configured to reset a potential of an output end of the reset module, a first output end of the reset module is electrically connected to the output end of the stage signal generation module, a second output end of the reset module is electrically connected to the first node, and a third output end of the reset module is electrically connected to the output end of the scan signal generation module.
Optionally, in some embodiments of the present application, the GOA unit further includes a pull-down module and a bootstrap module, the bootstrap module is configured to generate a bootstrap capacitor, a first end of the bootstrap module is electrically connected to the first node, a second end of the bootstrap module is electrically connected to the third output end of the reset module, the pull-down module is configured to pull down a potential of an output end of the pull-down module, a first output end of the pull-down module is electrically connected to the first node, and a second output end of the pull-down module is electrically connected to the output end of the scan signal generation module.
Optionally, in some embodiments of the present application, the GOA unit further includes a pull-down maintaining module, where the pull-down maintaining module is configured to maintain a potential of an output end of the pull-down maintaining module during a shutdown phase of the GOA unit, a first output end of the pull-down maintaining module is electrically connected to the first node, a second output end of the pull-down maintaining module is electrically connected to the output end of the level signaling generation module, a third output end of the pull-down maintaining module is electrically connected to the output end of the scan signaling generation module and the second end of the bootstrap module, and a fourth output end of the pull-down maintaining module is electrically connected to the second excitation capacitor end of the excitation capacitor.
Optionally, in some embodiments of the application, in a first node potential falling stage, the excitation module is further configured to excite the potential of the first node from a peak high potential to a first low potential, the scan signal generation module is further configured to pull down the potential of the first node from the first low potential to a second low potential, and the pull-down module pulls down the potential of the first node from the second low potential to a third low potential.
Correspondingly, the embodiment of the present application further provides a display panel, where the display panel includes a first substrate, a second substrate disposed opposite to the first substrate, and a liquid crystal layer interposed between the first substrate and the second substrate, and the first substrate includes any one of the foregoing GOA circuits.
In an embodiment of the present application, a GOA circuit and a display panel are provided. In the GOA unit, an excitation module is added in the GOA unit, and the excitation module participates in exciting the potential rise of the first node Qn at the potential rise stage of the first node Qn, so that the pull-up capability of the GOA unit on the potential of the first node Qn is improved, the GOA unit has more sufficient pull-up capability and pull-up margin on the potential of the first node Qn, and the service life and reliability of the GOA circuit are improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a prior art GOA unit of the present application;
FIG. 2 is a schematic diagram of the potential variation of the first node in a GOA unit according to the prior art;
fig. 3 is a schematic diagram of a GOA unit according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram illustrating a potential variation of a first node in a GOA unit according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of a GOA unit according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram illustrating a potential variation of a first node in a GOA unit according to an embodiment of the present disclosure;
fig. 7 is a schematic circuit diagram of a GOA unit according to an embodiment of the present disclosure;
FIG. 8 is a timing diagram of a plurality of clock signals provided by an embodiment of the present application;
FIG. 9 is a timing diagram of a plurality of scan signals according to an embodiment of the present application;
fig. 10 is a timing diagram of signals of a GOA unit according to an embodiment of the present disclosure;
fig. 11 is a schematic circuit diagram of a GOA unit according to an embodiment of the present disclosure;
fig. 12 is a timing diagram of signals of a GOA unit according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
The embodiment of the application provides a GOA circuit and a display panel. The following are detailed below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.
The first embodiment,
Referring to fig. 3 and 4, fig. 4 is a graph illustrating a variation of the voltage level of the first node Qn of fig. 3 with the operation of the GOA unit. The embodiment of the present application provides a GOA circuit, where the GOA circuit includes a plurality of cascaded GOA units 10, and at least one GOA unit 10 includes: a precharge module 100, an excitation module 800, and a scan signal generation module 200. The precharge module 100 is configured to precharge the potential of the first node Qn to the first high potential L12 in the rising period T1 of the potential of the first node Qn; the excitation module 800 is configured to excite the potential of the first node Qn from the first high potential L12 to the second high potential L13 in the rising phase T1 of the potential of the first node Qn; the scan signal generating module 200 is configured to pull up the potential of the first node Qn from the second high potential L13 to the peak high potential L14 in the rising period T1 of the potential of the first node Qn, and output the nth scan signal Gn.
Specifically, in some embodiments, the GOA circuit includes n stages of cascaded GOA cells 10, and at least one GOA cell 10 includes a pre-charge module 100, an excitation module 800, and a scan signal generation module 200. The potential change of the first node Qn includes a rising period T1 and a falling period T2.
It can be understood that each of the plurality of GOA units includes an off period and an on period, the off period of the GOA unit means that the GOA unit constantly outputs a scan signal to turn off the thin film transistors in the pixels connected to the corresponding row, and the on period of the GOA unit means that the GOA unit outputs a scan signal to turn on the thin film transistors in the pixels connected to the corresponding row.
Note that both the potential rising period T1 and the potential falling period T2 of the first node Qn are included in the period when the nth-stage GOA unit 10 starts operating or generates the nth-stage scanning signal Gn. The working period of the GOA cell includes a potential rising period T1 of the first node Qn, a potential falling period T2 of the first node Qn, and a scan signal output period between the potential rising period T1 and the potential falling period T2 of the first node Qn.
Specifically, in some embodiments, during the rising period T1 of the potential of the first node Qn, the pre-charge module 100 pre-charges the potential of the first node Qn from the low potential L11 to the first high potential L12, the excitation module 800 excites the potential of the first node Qn from the first high potential L12 to the second high potential L13, the scan signal generation module 200 pulls up the potential of the first node Qn from the second high potential L13 to the peak high potential L14, and the output terminal of the scan signal generation module 200 outputs the nth scan signal Gn.
Specifically, in some embodiments, during the falling period T2 of the potential of the first node Qn, the excitation module 800 first excites the potential of the first node Qn from the peak high potential L14 to the first low potential L21, and then the scan signal generation module 200 pulls the potential of the first node Qn from the first low potential L21 to the second low potential L22.
Specifically, in some embodiments, the GOA unit further includes a pull-down module 600, and during the falling period T2 of the potential of the first node Qn, the pull-down module 600 pulls down the potential of the first node Qn from the second low potential L22 to the third low potential L23.
Specifically, in some embodiments, the low potential L11 and the third low potential L23 are the lowest potentials, and the potentials of the low potential L11 and the third low potential L23 may be the same or similar. The potential value of the first high potential L12 is larger than that of the low potential L11, the potential value of the second high potential L13 is larger than that of the first high potential L12, and the potential value of the peak high potential L14 is larger than that of the second high potential L13. The first low potential L21 has a potential value smaller than the peak high potential L14, the second low potential L22 has a potential value smaller than the first low potential L21, and the third low potential L23 has a potential value smaller than the second low potential L22.
With continuing reference to fig. 3 and 4, the driving module 800 includes a driving capacitor Cbt2 and a driving transistor sub-module. The excitation capacitor Cbt2 comprises a first excitation capacitor end and a second excitation capacitor end, and the first excitation capacitor end is electrically connected with the first node Qn; the driving transistor submodule comprises an input end, a driving end and an output end, and the input end of the driving transistor submodule is electrically connected with the (n-1) th-level clock signal CKn-1; the driving end of the drive transistor submodule is electrically connected with the first node Qn; and the output end of the drive transistor submodule is electrically connected with the end of the second drive capacitor.
With continued reference to fig. 3, in some embodiments, the driver transistor sub-module includes a driver transistor T71, and an input terminal of the driver transistor T71 is electrically connected to the (n-1) th stage clock signal CKn-1; the driving terminal of the driver transistor T71 is electrically connected to the first node Qn; the output end of the driving transistor T71 is electrically connected to the second driving capacitor end.
Referring to fig. 3, the output terminal of the pre-charge module 100 is electrically connected to the first node Qn, the driving terminal of the scan signal generation module 200 is electrically connected to the first node Qn, the input terminal of the scan signal generation module 200 is electrically connected to the nth-stage clock signal CKn, and the output terminal of the scan signal generation module 200 outputs the nth-stage scan signal Gn.
Referring to fig. 3, the goa unit 10 further includes a level signal generating module 300, a driving end of the level signal generating module 300 is electrically connected to the first node Qn, an input end of the level signal generating module 300 is electrically connected to the nth level clock signal CKn, and an output end of the level signal generating module 300 outputs the nth level signal STn.
Referring to fig. 3, the goa unit 10 further includes a reset module 500 for resetting the potential of the output terminal of the reset module 500, the first output terminal 51 of the reset module 500 is electrically connected to the output terminal of the level signaling generation module 300, the second output terminal 52 of the reset module 500 is electrically connected to the first node Qn, and the third output terminal 53 of the reset module 500 is electrically connected to the output terminal of the scan signal generation module 200.
Please refer to fig. 3, the goa unit 10 further includes a pull-down module 600 and a bootstrap module 400, a first output terminal 61 of the pull-down module 600 is electrically connected to the first node Qn, a second output terminal 62 of the pull-down module 600 is electrically connected to the output terminal of the scan signal generating module 200, and the pull-down module 600 is configured to pull down the potential of the output terminal of the pull-down module 600. The first end of the bootstrap module 400 is electrically connected to the first node Qn, the second end of the bootstrap module 400 is electrically connected to the third output end 53 of the reset module 500, and the bootstrap module 400 is configured to generate a bootstrap capacitor.
Please refer to fig. 3, the GOA unit 10 further includes a pull-down maintaining module 700, the pull-down maintaining module 700 is configured to maintain a voltage level of an output terminal of the pull-down maintaining module 700 during a shutdown period of the GOA unit 10, a first output terminal 71 of the pull-down maintaining module 700 is electrically connected to the first node Qn, a second output terminal 72 of the pull-down maintaining module 700 is electrically connected to an output terminal of the level signaling signal generating module 300, a third output terminal 73 of the pull-down maintaining module 700 is electrically connected to an output terminal of the scanning signal generating module 200 and a second terminal of the bootstrap module 400, and a fourth output terminal 74 of the pull-down maintaining module 700 is electrically connected to a second excitation capacitor terminal of the excitation capacitor Cbt 2.
In the embodiment of the present application, it is proposed to add the excitation module 800 in the GOA unit, where the excitation module 800 participates in exciting the potential rise of the first node Qn at the potential rise stage of the first node Qn, and the excitation module 800 participates in exciting the potential fall of the first node Qn at the potential fall stage of the first node Qn, so as to improve the pull-up capability and the pull-down capability of the GOA unit on the potential of the first node Qn, so that the GOA unit has more sufficient pull-up capability and pull-down capability on the potential of the first node Qn, thereby improving the lifetime and reliability of the GOA unit.
Example II,
Referring to fig. 5 and 6, fig. 6 is a diagram illustrating a variation of the potential of the first node Qn in fig. 5 with the operation of the GOA unit. The same or similar parts of this embodiment as those of the embodiment are not described herein again, but the difference is that the driving end of the driver transistor sub-module is connected to a signal differently.
Referring to fig. 5, the driving module 800 includes a driving capacitor Cbt2 and a driving transistor sub-module. The excitation capacitor Cbt2 comprises a first excitation capacitor end and a second excitation capacitor end, and the first excitation capacitor end is electrically connected with the first node Qn; the driving transistor submodule comprises an input end, a driving end and an output end, and the input end of the driving transistor submodule is electrically connected with the n-1 st level clock signal CKn-1; the driving end of the drive transistor submodule is electrically connected with the stage transmission signal STn-2 of the (n-2) th stage; and the output end of the drive transistor submodule is electrically connected with the end of the second drive capacitor.
Specifically, in some embodiments, the driver transistor submodule includes a driver transistor T71, and an input terminal of the driver transistor T71 is electrically connected to the n-1 th stage clock signal CKn-1; the driving terminal of the driver transistor T71 is electrically connected to the stage signal STn-2 of the (n-2) th stage; the output terminal of the driving transistor T71 is electrically connected to the second driving capacitor terminal.
The embodiment of the present application provides a GOA circuit, where the GOA circuit includes a plurality of cascaded GOA units 10, and at least one GOA unit 10 includes a pre-charging module 100, an excitation module 800, and a scan signal generation module 200. The precharge module 100 is configured to precharge the potential of the first node Qn to the first high potential L12 in the rising period T1 of the potential of the first node Qn; the excitation module 800 is configured to excite the potential of the first node Qn from the first high potential L12 to the second high potential L13 in the rising phase T1 of the potential of the first node Qn; the scan signal generating module 200 is configured to pull up the potential of the first node Qn from the second high potential L13 to the peak high potential L14 in the rising period T1 of the potential of the first node Qn, and output the nth scan signal Gn.
Specifically, referring to fig. 6, in some embodiments, in the rising period T1 of the potential of the first node Qn, the pre-charging module 100 pre-charges the potential of the first node Qn from the low potential L11 to the first high potential L12, the excitation module 800 excites the potential of the first node Qn from the first high potential L12 to the second high potential L13, the scan signal generating module 200 pulls up the potential of the first node Qn from the second high potential L13 to the peak high potential L14, and the output end of the scan signal generating module 200 outputs the nth-level scan signal Gn.
Specifically, referring to fig. 6, in some embodiments, the GOA unit further includes a pull-down module 600, and in the falling stage T2 of the potential of the first node Qn, the scan signal generation module 200 pulls down the potential of the first node Qn from the peak high potential L14 to the second low potential L22, and the pull-down module 600 pulls down the potential of the first node Qn from the second low potential L22 to the third low potential L23.
Note that the potential rising phase and the potential falling phase of the first node Qn are both included in the period when the nth-stage GOA unit 10 starts operating or generates the nth-stage scanning signal Gn.
In this embodiment, in the GOA unit, it is proposed to add an excitation module in the GOA unit, where the excitation module participates in exciting the potential rise of the first node Qn at the potential rise stage of the first node Qn, so as to improve the pull-up capability of the GOA unit on the potential of the first node Qn, so that the GOA unit has more sufficient pull-up capability and pull-up margin on the potential of the first node Qn, thereby improving the lifetime and reliability of the GOA circuit.
Example III,
Referring to fig. 7, the GOA cell 10 in the first embodiment is described in detail in the present embodiment, and the circuit diagrams of the precharge module 100, the reset module 500, the pull-down module 600, and the pull-down sustain module 700 in the first embodiment are described in detail by way of example, but the circuit structures of the precharge module 100, the reset module 500, the pull-down module 600, and the pull-down sustain module 700 are not limited thereto.
Specifically, the precharge module 100 includes a precharge transistor T11, a driving terminal of the precharge transistor T11 is electrically connected to the stage transfer signal STn-3 of the nth-3 stage, an input terminal of the precharge transistor T11 is electrically connected to the high potential signal VGH, and an output terminal of the precharge transistor T11 is electrically connected to the first node Qn.
Specifically, the scan signal generating module 200 includes a scan signal generating transistor T21, a driving terminal of the scan signal generating transistor T21 is electrically connected to the first node Qn, an input terminal of the scan signal generating transistor T21 is electrically connected to the nth-stage clock signal CKn, and an output terminal of the scan signal generating transistor T21 outputs the nth-stage scan signal Gn.
Specifically, the stage signal generating module 300 includes a stage signal generating transistor T22, a driving terminal of the stage signal generating transistor T22 is electrically connected to the first node Qn, an input terminal of the stage signal generating transistor T22 is electrically connected to the clock signal CKn of the nth stage, and an output terminal of the stage signal generating transistor T22 outputs the stage signal STn of the nth stage.
Specifically, the bootstrap module 400 includes a bootstrap capacitor Cb1, a first end capacitor electrode of the bootstrap capacitor Cb1 is electrically connected to the first node Qn, and a second end capacitor electrode of the bootstrap capacitor Cb1 is electrically connected to the output end of the scan signal generating transistor T21.
Specifically, the Reset module 500 includes three Reset transistors, which are a first Reset transistor Tr _ S, a second Reset transistor Tr _ Q, and a third Reset transistor Tr _ G, respectively, and a driving terminal of each Reset transistor is electrically connected to a Reset signal Reset. The output terminal of the first reset transistor Tr _ S is the first output terminal 51 of the reset module 500, and is electrically connected to the output terminal of the stage signal generating transistor T22. The output terminal of the second reset transistor Tr _ Q is the second output terminal 52 of the reset module 500 and is electrically connected to the first node Qn. An output terminal of the third reset transistor Tr _ G is the third output terminal 53 of the reset module 500 and is electrically connected to an output terminal of the scan signal generating transistor T21. The input terminals of the first and second reset transistors Tr _ S and Tr _ Q are electrically connected to the VSSQ signal, and the input terminal of the third reset transistor Tr _ G is electrically connected to the VSSG signal. In some embodiments, both the VSSQ signal and the VSSG signal are dc negative voltage signals, and the voltage values of the VSSQ signal and the VSSG signal may be the same or different.
Specifically, the pull-down module 600 includes a first pull-down transistor T31 and a second pull-down transistor T41. The driving terminals of the first pull-down transistor T31 and the second pull-down transistor T41 are electrically connected to the stage pass signal STn +3 of the (n + 3) th stage. The output terminal of the first pull-down transistor T31 is the second output terminal 62 of the pull-down module 600, and is electrically connected to the output terminal of the scan signal generating transistor T21, and the input terminal of the first pull-down transistor T31 is electrically connected to the VSSG signal. The output terminal of the second pull-down transistor T41 is the first output terminal 61 of the pull-down module 600, and is electrically connected to the first node Qn. The input terminal of the second pull-down transistor T41 is electrically connected to the VSSQ signal.
Specifically, the pull-down maintaining module 700 may include two parallel first pull-down maintaining sub-modules 710 and second pull-down maintaining sub-modules 720, and the first pull-down maintaining sub-module 710 and the second pull-down maintaining sub-module 720 are mirror-symmetrical in the circuit diagram of fig. 7. The first pull-down sustain submodule 710 and the second pull-down sustain submodule 720 may each include an inverter, a first output terminal 71, a second output terminal 72, a third output terminal 73, and a fourth output terminal 74. Although it is illustrated that the pull-down maintenance module 700 may include two parallel first and second pull-down maintenance sub-modules 710 and 720, in some embodiments, the pull-down maintenance module 700 may also include one of the first and second pull-down maintenance sub-modules 710 and 720. The first LC signal LC1 and the second LC signal LC2 are usually opposite in potential, for example, when the first LC signal LC1 is high, the second LC signal LC2 is low, and when the first LC signal LC1 is low, the second LC signal LC2 is high.
As shown in fig. 7, the first pull-down maintaining sub-module 710 includes a first pull-down maintaining transistor T34, a second pull-down maintaining transistor T24, a third pull-down maintaining transistor T44, a fourth pull-down maintaining transistor T73, a fifth pull-down maintaining transistor T65, a sixth pull-down maintaining transistor T64, a seventh pull-down maintaining transistor T62, and an eighth pull-down maintaining transistor T61. The driving terminals of the first pull-down maintaining transistor T34, the second pull-down maintaining transistor T24, the third pull-down maintaining transistor T44 and the fourth pull-down maintaining transistor T73 are electrically connected to the output terminals of the fifth pull-down maintaining transistor T65, the sixth pull-down maintaining transistor T64, the seventh pull-down maintaining transistor T62 and the eighth pull-down maintaining transistor T61. The output terminal of the first pull-down sustain transistor T34 is the third output terminal 73 of the first pull-down sustain submodule 710 and is electrically connected to the output terminal of the scan signal generating transistor T21. The output terminal of the second pull-down sustain transistor T24 is the second output terminal 72 of the first pull-down sustain submodule 710 and is electrically connected to the output terminal of the stage signal generating transistor T22. The output terminal of the third pull-down sustain transistor T44 is the first output terminal 71 of the first pull-down sustain submodule 710 and is electrically connected to the first node Qn. The output terminal of the fourth pull-down sustain transistor T73 is the fourth output terminal 74 of the first pull-down sustain submodule 710 and is electrically connected to the output terminal of the driver transistor T71. The input terminal of the first pull-down sustain transistor T34 is electrically connected to the VSSG signal. The input terminals of the second pull-down maintaining transistor T24, the third pull-down maintaining transistor T44 and the fourth pull-down maintaining transistor T73 are electrically connected to the VSSQ signal. Driving terminals of the fifth pull-down maintaining transistor T65, the sixth pull-down maintaining transistor T64, the seventh pull-down maintaining transistor T62, and the eighth pull-down maintaining transistor T61 are electrically connected to the n-3 th stage transfer signal STn-3, the first LC signal LC1, the first node Qn, and the second LC signal LC2, respectively. The input terminals of the fifth pull-down maintaining transistor T65, the sixth pull-down maintaining transistor T64 and the seventh pull-down maintaining transistor T62 are electrically connected to the VSSQ signal. The input terminal of the eighth pull-down maintaining transistor T61 is electrically connected to the high potential signal VGH.
It is understood that the second pull-down maintaining sub-module 720 includes a ninth pull-down maintaining transistor T33, a tenth pull-down maintaining transistor T23, an eleventh pull-down maintaining transistor T43, a twelfth pull-down maintaining transistor T72, a thirteenth pull-down maintaining transistor T55, a fourteenth pull-down maintaining transistor T54, a fifteenth pull-down maintaining transistor T52 and a sixteenth pull-down maintaining transistor T51, wherein the driving terminals of the ninth pull-down maintaining transistor T33, the tenth pull-down maintaining transistor T23, the eleventh pull-down maintaining transistor T43 and the twelfth pull-down maintaining transistor T72 are electrically connected to the output terminals of the thirteenth pull-down maintaining transistor T55, the fourteenth pull-down maintaining transistor T54, the fifteenth pull-down maintaining transistor T52 and the sixteenth pull-down maintaining transistor T51. The output terminal of the ninth pull-down sustain transistor T33 is the third output terminal 73 of the second pull-down sustain submodule 720 and is electrically connected to the output terminal of the scan signal generating transistor T21. The output terminal of the tenth pull-down sustain transistor T23 is the second output terminal 72 of the second pull-down sustain submodule 720, and is electrically connected to the output terminal of the stage signal generating transistor T22. An output terminal of the eleventh pull-down sustain transistor T43 is the first output terminal 71 of the second pull-down sustain submodule 720 and is electrically connected to the first node Qn. The output terminal of the twelfth pull-down sustain transistor T72 is the fourth output terminal 74 of the second pull-down sustain submodule 720 and is electrically connected to the output terminal of the driver transistor T71. The input terminal of the ninth pull-down sustain transistor T33 is electrically connected to the VSSG signal. The input terminals of the tenth, eleventh, and twelfth pull-down sustain transistors T23, T43, and T72 are electrically connected to the VSSQ signal. Driving terminals of a thirteenth pull-down maintaining transistor T55, a fourteenth pull-down maintaining transistor T54, a fifteenth pull-down maintaining transistor T52, and a sixteenth pull-down maintaining transistor T51 are electrically connected to the n-3 th stage transfer signal STn-3, the second LC signal LC2, the first node Qn, and the first LC signal LC1, respectively. The input terminals of the thirteenth pull-down sustain transistor T55, the fourteenth pull-down sustain transistor T54, and the fifteenth pull-down sustain transistor T52 are all electrically connected to the VSSQ signal. The input terminal of the sixteenth pull-down maintaining transistor T51 is electrically connected to the high potential signal VGH.
Referring to fig. 8, voltage waveforms of the clock signals of the GOA circuit including the multiple levels of the GOA units 10 are illustrated, which schematically show the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CK4, the fifth clock signal CK5, and the sixth clock signal CK6, by way of example.
Referring to fig. 9, voltage waveforms of a plurality of scan signals output by the GOA circuit including the multi-level GOA unit 10 are illustrated, in which a first row scan signal G1, a second row scan signal G2, a third row scan signal G3, a fourth row scan signal G4, a fifth row scan signal G5, and a sixth row scan signal G6 are illustrated by way of example.
Fig. 10 illustrates a process of changing a voltage of the first node Qn in the circuit of the GOA cell in fig. 7, where the process of operating the GOA cell in fig. 7 includes:
in the first stage C1, STn-3 changes from low potential to high potential, the pre-charge transistor T11 is turned on, the pre-charge module 100 charges the first node Qn, the pre-charge module 100 pre-charges the potential of the first node Qn from low potential L11 to high potential L12, and at this time, the driving transistor T71 and the scan signal generating transistor T21 start to be turned on to prepare for the subsequent stage.
In the second stage C2, the n-1 th stage clock signal CKn-1 changes from the low level to the high level, and the pumping module 800 pumps the voltage of the first node Qn from the first high level L12 to the second high level L13 because the pumping transistor T71 is in the on state.
In the third stage C3, the nth stage clock signal CKn changes from the low potential to the high potential, and the scan signal generating module 200 pulls up the potential of the first node Qn from the second high potential L13 to the peak high potential L14 because the scan signal generating transistor T21 is in the on state.
In the fourth stage C4, the n-1 th clock signal CKn-1 changes from high to low, and the driving module 800 first drives the first node Qn from the peak high level L14 to the first low level L21.
In the fifth stage C5, the nth clock signal CKn changes from high to low, and the scan signal generating module 200 pulls the potential of the first node Qn from the first low potential L21 to the second low potential L22.
In the sixth stage C6, STn +3 changes from the low potential to the high potential, and the pull-down module 600 pulls down the potential of the first node Qn from the second low potential L22 to the third low potential L23.
In the embodiment of the present application, a GOA circuit is provided, where in a GOA unit, an excitation module is added in the GOA unit, the excitation module participates in exciting a potential rise of a first node Qn in a potential rise stage of the first node Qn, and the excitation module 800 participates in exciting a potential fall of the first node Qn in a potential fall stage of the first node Qn, so that a pull-up capability and a pull-down capability of the GOA unit on a potential of the first node Qn are improved, so that the GOA unit has a more sufficient pull-up capability and pull-down capability on a potential of the first node Qn, thereby improving a lifetime and reliability of the GOA unit.
Examples IV,
Referring to fig. 11, the second embodiment of the present application describes in detail the GOA cell 10, and the second embodiment of the present application describes in detail the circuit diagrams of the precharge module 100, the reset module 500, the pull-down module 600, and the pull-down sustain module 700, but the circuit structures of the precharge module 100, the reset module 500, the pull-down module 600, and the pull-down sustain module 700 are not limited thereto.
Referring to fig. 11, the same or similar parts of this embodiment as those of the embodiment are not repeated herein, but the difference is that the driving end of the driver transistor sub-module is connected to a different signal.
Referring to fig. 11, the driver transistor sub-module includes a driver transistor T71, and an input terminal of the driver transistor T71 is electrically connected to the n-1 th clock signal CKn-1; the driving end of the driver transistor T71 is electrically connected to the stage signal of the (n-2) th stage; the output end of the driving transistor T71 is electrically connected to the second driving capacitor end.
Fig. 12 is a graph illustrating the change of the potential of the first node Qn in fig. 11 according to the operation of the GOA cell. The working process of the GOA unit in fig. 11 includes:
in the first stage C1, STn-3 changes from low potential to high potential, the pre-charge transistor T11 is turned on, the pre-charge module 100 charges the first node Qn, the pre-charge module 100 pre-charges the potential of the first node Qn from low potential L11 to high potential L12, and at this time, the scan signal generating transistor T21 is turned on to prepare for the subsequent stage.
In the second stage C2, the gate signal STn-2 of the (n-2) th stage is changed from the low potential to the high potential, and the driver transistor T71 is turned on.
In the third stage C3, the n-1 th clock signal CKn-1 changes from the low voltage level to the high voltage level, and the pumping module 800 pumps the voltage level of the first node Qn from the first high voltage level L12 to the second high voltage level L13.
In the fourth stage C4, the nth clock signal CKn changes from low to high, and since the scan signal generating transistor T21 is in an on state, the scan signal generating module 200 pulls up the potential of the first node Qn from the second high potential L13 to the peak high potential L14, and the output terminal of the scan signal generating module 200 outputs the nth scan signal Gn.
In the fifth stage C5, the nth clock signal CKn changes from high to low, and the scan signal generating module 200 pulls the potential of the first node Qn from the peak high level L14 to the second low level L22.
In the sixth stage C6, the level transmission signal STn +3 of the (n + 3) th stage changes from the low level to the high level, and the pull-down module 600 pulls down the potential of the first node Qn from the second low level L22 to the third low level L23.
In the embodiment of the present application, a GOA circuit is provided, in which an excitation module is added in a GOA unit, and the excitation module participates in exciting a potential rise of a first node Qn in a potential rise stage of the first node Qn, so that a pull-up capability of the GOA unit on the potential of the first node Qn is improved, so that the GOA unit has a more sufficient pull-up capability on the potential of the first node Qn, thereby improving a lifetime and reliability of the GOA unit.
Example V,
The embodiment of the present application further provides a display panel, where the display panel includes a first substrate, a second substrate disposed opposite to the first substrate, and a liquid crystal layer interposed between the first substrate and the second substrate, and the first substrate includes the GOA circuit in any one of the above embodiments.
It should be noted that each transistor in the above embodiments may refer to a thin film transistor, an input terminal of each transistor may be one of a source and a drain of the transistor, and an output terminal of each transistor may be the other of the source and the drain of the transistor.
The foregoing detailed description is directed to a GOA circuit and a display panel provided in the embodiments of the present application, and specific examples are applied herein to illustrate the principles and implementations of the present application, and the above description of the embodiments is only used to help understand the method and the core ideas of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (9)
1. A GOA circuit comprising a plurality of cascaded GOA cells, at least one of said GOA cells comprising:
a precharge module, configured to precharge a potential of a first node to a first high potential in a first node potential rising phase;
the excitation module is used for exciting the potential of the first node from the first high potential to a second high potential in the potential rising stage of the first node;
a scanning signal generating module, configured to, in the first node potential rising stage, raise the potential of the first node from the second high potential to a peak high potential, and output an nth-level scanning signal;
the output end of the scanning signal generation module outputs an nth-level scanning signal, and the excitation module comprises an excitation capacitor and an excitation transistor submodule;
the excitation capacitor comprises a first excitation capacitor end and a second excitation capacitor end, and the first excitation capacitor end is electrically connected with the first node;
the driving transistor submodule comprises an input end, a driving end and an output end, and the input end is electrically connected with the n-1 level clock signal; the driving end is electrically connected with the level signal of the (n-2) th level; the output end is electrically connected with the second excitation capacitor end.
2. The GOA circuit of claim 1, wherein the driver transistor submodule comprises a driver transistor.
3. The GOA circuit according to claim 1 or 2, wherein an output terminal of the pre-charge module is electrically connected to the first node, a driving terminal of the scan signal generation module is electrically connected to the first node, and an input terminal of the scan signal generation module is electrically connected to an nth stage clock signal.
4. The GOA circuit of claim 3, wherein the GOA unit further comprises a stage signal generation module, a driving end of the stage signal generation module is electrically connected with the first node, an input end of the stage signal generation module is electrically connected with the nth stage clock signal, and an output end of the stage signal generation module outputs the nth stage transmission signal.
5. The GOA circuit of claim 4, wherein the GOA unit further comprises a reset module for resetting a potential of an output terminal of the reset module, a first output terminal of the reset module is electrically connected to the output terminal of the stage signaling generation module, a second output terminal of the reset module is electrically connected to the first node, and a third output terminal of the reset module is electrically connected to the output terminal of the scan signal generation module.
6. The GOA circuit of claim 5, wherein the GOA unit further comprises a pull-down module and a bootstrap module, the bootstrap module is configured to generate a bootstrap capacitor, a first end of the bootstrap module is electrically connected to the first node, a second end of the bootstrap module is electrically connected to the third output end of the reset module, the pull-down module is configured to pull down a potential of an output end of the pull-down module, a first output end of the pull-down module is electrically connected to the first node, and a second output end of the pull-down module is electrically connected to the output end of the scan signal generation module.
7. The GOA circuit of claim 6, wherein the GOA unit further comprises a pull-down maintaining module, the pull-down maintaining module is configured to maintain a voltage level of an output terminal of the pull-down maintaining module during a turn-off period of the GOA unit, a first output terminal of the pull-down maintaining module is electrically connected to the first node, a second output terminal of the pull-down maintaining module is electrically connected to the output terminal of the stage signaling generation module, a third output terminal of the pull-down maintaining module is electrically connected to the output terminal of the scan signal generation module and the second terminal of the bootstrap module, and a fourth output terminal of the pull-down maintaining module is electrically connected to the second excitation capacitor terminal of the excitation capacitor.
8. The GOA circuit as claimed in claim 6 or 7, wherein the pumping module is further configured to pump the potential of the first node from a peak high potential to a first low potential during a first node potential drop phase, the scan signal generating module is further configured to pull down the potential of the first node from the first low potential to a second low potential, and the pull-down module pulls down the potential of the first node from the second low potential to a third low potential.
9. A display panel comprising a first substrate, a second substrate disposed opposite to the first substrate, and a liquid crystal layer interposed between the first substrate and the second substrate, wherein the first substrate comprises the GOA circuit according to any one of claims 1 to 8.
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| CN202110357066.6A CN113178175B (en) | 2021-04-01 | 2021-04-01 | GOA circuit and display panel |
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| CN113178175B true CN113178175B (en) | 2023-03-28 |
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| JP5349693B2 (en) * | 2010-06-25 | 2013-11-20 | シャープ株式会社 | Scanning signal line driving circuit and scanning signal line driving method |
| CN102800292B (en) * | 2012-08-21 | 2014-12-10 | 昆山龙腾光电有限公司 | Gate driving circuit |
| CN103050106B (en) * | 2012-12-26 | 2015-02-11 | 京东方科技集团股份有限公司 | Gate driving circuit, display module and displayer |
| CN105489190B (en) * | 2016-02-15 | 2019-03-15 | 京东方科技集团股份有限公司 | Shifting deposit unit and its driving method, gate driving circuit, array substrate |
| CN110390903B (en) * | 2019-06-20 | 2022-12-30 | 昆山龙腾光电股份有限公司 | Grid driving circuit and display device |
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