CN113161410A - Gallium nitride high-temperature annealing protection structure and application thereof - Google Patents
Gallium nitride high-temperature annealing protection structure and application thereof Download PDFInfo
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 161
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 88
- 238000000137 annealing Methods 0.000 title claims abstract description 71
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 37
- 238000000231 atomic layer deposition Methods 0.000 claims abstract description 26
- 239000011241 protective layer Substances 0.000 claims abstract description 23
- 238000005468 ion implantation Methods 0.000 claims abstract description 16
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims abstract description 13
- 230000003213 activating effect Effects 0.000 claims abstract description 8
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- 229910052681 coesite Inorganic materials 0.000 claims description 10
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- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 10
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- 229910052682 stishovite Inorganic materials 0.000 claims description 10
- 229910052905 tridymite Inorganic materials 0.000 claims description 10
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- 229910052593 corundum Inorganic materials 0.000 claims description 7
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 7
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- 150000002500 ions Chemical class 0.000 description 3
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- 229910052735 hafnium Inorganic materials 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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Abstract
The invention discloses a gallium nitride high-temperature annealing protection structure and application thereof. The method for realizing the gallium nitride P-type doping comprises the steps of carrying out ion implantation on a gallium nitride material; forming an oxide layer on the surface of the gallium nitride material by adopting an atomic layer deposition mode; forming a low-stress silicon nitride layer on the surface of the oxide layer by adopting a low-pressure chemical vapor deposition mode; and taking the oxide layer and the silicon nitride layer as protective layers, carrying out high-temperature annealing on the gallium nitride material, and activating acceptor impurities in the gallium nitride material to realize P-type doping of the gallium nitride material. According to the method for protecting gallium nitride from high-temperature annealing activation provided by the embodiment of the invention, the formed protective layer can protect a GaN sample from annealing at the temperature of more than 1230 ℃ in the atmosphere of normal pressure and nitrogen, and the GaN sample is not decomposed in a short time.
Description
Technical Field
The invention particularly relates to a gallium nitride high-temperature annealing protection structure and application thereof, belonging to the technical field of semiconductors.
Background
With the development of science and technology, the exploration of the characteristics of Si materials has basically reached the extreme, and the characteristics of Si-based power electronic devices have approached the theoretical limit which can be reached by Si materials. Therefore, the third generation semiconductor typified by GaN is a material of choice for the next generation semiconductor power device. GaN has the following advantages: the wide forbidden band width (3.39eV) means that the material can resist high temperature and high pressure; high electron mobility 2000(2DEG) mu (cm)2V · s), which indicates that the device has higher working frequency; the good thermal conductivity indicates that the device is convenient to dissipate heat during operation; the smaller dielectric constant epsilonr is 9, indicating a smaller parasitic capacitance. Meanwhile, the third generation semiconductor material has more stable chemical property, radiation resistance and other characteristics than the first generation and the second generation semiconductor materials, and can work in a more severe environment.
Ion implantation is a very attractive technique in the fabrication of GaN-based semiconductor discrete devices, such as electrically and optically selective region doping, dry etching, electrical isolation, quantum well intermixing, and ion cutting. As a commonly used semiconductor device fabrication process, ion implantation initially pushed the progress in CMOS processes. The method can introduce almost all elements in the periodic table and accurately control the concentration and the depth of the dopant, and can achieve the effect required by an epitaxial GaN process to a certain extent, so that the ion implantation has great influence on the optical and electrical properties of the GaN material. Research on the important influence of ion implantation on GaN materials in various aspects is essential for the rapidly developing GaN industry. However, ion implantation causes damage to GaN materials, and ions implanted into GaN materials also have certain activation problems. Usually, a high-temperature annealing method is adopted to solve the unavoidable side effects caused by ion implantation. Particularly, in the process of implementing P-type GaN by Mg ion implantation today, because Mg has large activation energy in GaN, annealing under high temperature and high pressure environment is generally needed, and a protective layer with very harsh conditions needs to be added on GaN before annealing to prevent GaN materials or devices from decomposing under high temperature annealing.
High temperature anneal protection most commonly used throughout the world todayThe layer is formed by sputtering or extending an AlN protective film or SiO2The protective film is made of AlN, which has a large forbidden band width, can resist ultra-high temperature (about 1300 ℃), even more, can reach 1500 ℃, and can reach a dense degree due to lattice mismatch with GaN. SiO 22The protective layer is compatible with GaN at present, can be used for a buffer layer of a GaN material or a device, can generally resist the high temperature of 1100 ℃, and the rest protective layers are immature at present and are not widely adopted.
Although the AlN protective film can resist high temperature, the AlN protective film and the GaN belong to III-V nitride semiconductors, and the selection of the AlN protective film and the GaN material in etching is small, so that the GaN can be etched off while the AlN protective film is removed by dry etching, the surface appearance of the GaN is poor, the roughness of the material can be influenced, the electric leakage of a device can be caused, and the like, while the AlN protective film with poor epitaxial quality can be removed by wet etching, and the AlN protective film with good quality is not completely corroded. The etching is performed because the protective layer is used for protecting GaN from decomposition during high-temperature activation, and the protective layer needs to be removed after annealing, and the clean and simple removal of the protective layer is one of the reasons for selecting the protective layer. And SiO2The protective film decomposes at temperatures substantially around 1100 c, which is far from desirable for activation of Mg ion implanted GaN.
Disclosure of Invention
The invention mainly aims to provide a gallium nitride high-temperature annealing protection structure and application thereof, thereby overcoming the defects in the prior art.
In order to achieve the purpose, the technical scheme adopted by the invention comprises the following steps:
the embodiment of the invention provides a gallium nitride high-temperature annealing protection structure which comprises an oxide layer and a silicon nitride layer which are sequentially stacked on the surface of a gallium nitride material.
The embodiment of the invention provides a method for activating gallium nitride by high-temperature annealing, which comprises the following steps: the gallium nitride high-temperature annealing protection structure is arranged on the surface of a gallium nitride material, and the gallium nitride material is annealed at the temperature of over 1200 ℃.
The embodiment of the invention provides a method for realizing gallium nitride P-type doping, which comprises the steps of carrying out ion implantation on a gallium nitride material;
forming an oxide layer on the surface of the gallium nitride material by adopting an atomic layer deposition mode;
forming a low-stress silicon nitride layer on the surface of the oxide layer by adopting a low-pressure chemical vapor deposition mode;
and taking the oxide layer and the silicon nitride layer as protective layers, carrying out high-temperature annealing on the gallium nitride material, and activating acceptor impurities in the gallium nitride material to realize P-type doping of the gallium nitride material.
Compared with the prior art, the invention has the advantages that:
1) according to the gallium nitride high-temperature annealing protection structure provided by the embodiment of the invention, the oxide layer grown in the ALD mode can cover the defects on the surface of the gallium nitride material, the low-stress silicon nitride layer grown in the LPCVD mode is used as a compact high-temperature protection layer and can avoid the influence of tensile stress in the annealing process, and the gallium nitride material can be protected from being annealed at the temperature of over 1200 ℃ without decomposition through a specific growth sequence;
2) according to the method for protecting the high-temperature annealing activation of the gallium nitride, the oxide film grown in the ALD mode has small influence on the GaN sample during annealing, does not react with the GaN sample, and can play a role in passivation in the high-temperature annealing process so as to prevent the GaN sample from being decomposed under the high-temperature annealing condition;
3) according to the method for protecting the high-temperature annealing activation of the gallium nitride, provided by the embodiment of the invention, the low-stress SiN layer has a higher melting point as that of LPCVD-SiN of a standard program, and meanwhile, adverse influence on GaN caused by the problem of larger stress in high-temperature annealing can be prevented, so that a good protection effect is achieved;
4) according to the method for realizing the gallium nitride P-type doping, provided by the embodiment of the invention, the low-stress SiN layer and the ALD grown oxide layer can be completely removed, and the influence on a GaN sample in the removing process is small, unlike the larger influence on GaN in the removing process of an epitaxial AlN film;
5) according to the method for realizing the P-type doping of the gallium nitride, the formed protective layer can protect a GaN sample from being annealed at the temperature of more than 1230 ℃ in the atmosphere of normal pressure and nitrogen, and the GaN sample is not decomposed in a short time.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for implementing P-type gan doping according to an exemplary embodiment of the present invention.
Detailed Description
In view of the deficiencies in the prior art, the inventors of the present invention have made extensive studies and extensive practices to provide technical solutions of the present invention. The technical solution, its implementation and principles, etc. will be further explained as follows.
The method for realizing the P-type doping of the gallium nitride provided by the embodiment of the invention can protect GaN from decomposition under the annealing conditions of temperature above 1200 ℃, normal pressure and nitrogen atmosphere; at the same time, the protective layer does not react with the GaN material during annealing or removal (such as the AlN film removal problem mentioned above), and the protective layer can be repeatedly grown and easily removed, thereby activating the berms for high temperature annealing of GaN.
The embodiment of the invention provides a gallium nitride high-temperature annealing protection structure which comprises an oxide layer and a silicon nitride layer which are sequentially stacked on the surface of a gallium nitride material.
Further, the oxide layer is grown by using an Atomic Layer Deposition (ALD) method.
Further, the material of the oxide layer comprises Al2O3、SiO2、HfO2Any one or a combination of two or more of (hafnium oxide), but not limited thereto.
Further, the thickness of the oxide layer is 5-30 nm.
Further, the silicon nitride layer is grown by Low Pressure Chemical Vapor Deposition (LPCVD).
Further, the silicon nitride layer comprises low stress silicon nitride.
Further, the thickness of the silicon nitride layer is 200-300 nm.
The embodiment of the invention provides a method for activating gallium nitride by high-temperature annealing, which comprises the following steps: the gallium nitride high-temperature annealing protection structure is arranged on the surface of a gallium nitride material, and the gallium nitride material is annealed at the temperature of over 1200 ℃.
Further, the annealing temperature is 1230-1250 ℃.
Further, the annealing time is 5min-30 min.
The embodiment of the invention provides a method for realizing gallium nitride P-type doping, which comprises the steps of carrying out ion implantation on a gallium nitride material;
forming an oxide layer on the surface of the gallium nitride material by adopting an atomic layer deposition mode;
forming a low-stress silicon nitride layer on the surface of the oxide layer by adopting a low-pressure chemical vapor deposition mode;
and taking the oxide layer and the silicon nitride layer as protective layers, carrying out high-temperature annealing on the gallium nitride material, and activating acceptor impurities in the gallium nitride material to realize P-type doping of the gallium nitride material.
Further, the material of the oxide layer comprises Al2O3、SiO2、HfO2Any one or a combination of two or more of them, but not limited thereto.
Further, the thickness of the oxide layer is 5-30 nm.
Further, the thickness of the silicon nitride layer is 200-300nm, and the silicon nitride layer comprises low-stress silicon nitride.
Further, the method comprises the following steps: and forming the oxide layer by adopting an atomic layer deposition mode.
In some more specific embodiments, the method specifically includes: placing gallium nitride material in a reaction chamber, adjusting the temperature in the reaction chamber to 300-320 ℃, and adding trimethylaluminum and H in the form of gas pulse2O is alternately fed into the reaction chamber to deposit and form Al on the surface of the gallium nitride material2O3A layer of a material selected from the group consisting of,wherein the flow rate of the trimethylaluminum is 150sccm, the pulse time is 0.1s-0.2s, the purging time is 6.0s-10s, and the H is2The flow rate of the introduced O is 200sccm, the pulse time is 0.1s-0.2s, the purging time is 6.0s-10s, and Al is formed by deposition2O3The rate of the layer was 0.093 nm/deposition cycle and the deposition time was 1 h.
In some more specific embodiments, the method specifically includes: gallium nitride material is placed in a reaction chamber, the temperature in the reaction chamber is regulated to 250-270 ℃, and SiH is added in the form of gas pulse4(silane) and ozone are alternately fed into the reaction chamber to deposit SiO on the surface of the gallium nitride material2Layer of, wherein, the SiH4The flow rate of the ozone is 120sccm, the pulse time is 0.1s-0.2s, the purging time is 150s-170s, the flow rate of the ozone is 70sccm, the pulse time is 5s, the purging time is 6s-10s, and SiO is formed by deposition2The rate of the layer was 0.05 nm/deposition cycle and the deposition time was 4 h.
In some more specific embodiments, the method specifically includes: placing gallium nitride material in a reaction chamber, adjusting the temperature in the reaction chamber to 250-270 ℃, and adding TDMHf (tetra-dimethylamino-hafnium) and H in the form of gas pulse2O is alternately fed into the reaction chamber to deposit and form HfO on the surface of the gallium nitride material2The TDMHf has the inlet flow of 50sccm, the pulse time of 1-1.2s, the purging time of 10-12.0s and the H2The flow rate of the introduced O is 60sccm, the pulse time is 0.1s, the purging time is 6.0s-10s, and the deposition is carried out to form HfO2The rate of the layer was 0.1 nm/deposition cycle and the deposition time was 40 min.
Further, the method specifically comprises the following steps: the high-temperature annealing is carried out in a protective atmosphere at normal pressure, and the adopted temperature is over 1200 ℃, preferably over 1230 ℃, particularly preferably 1230-1250 ℃, and the time is 5-30 min.
Further, the method further comprises the following steps: and removing the protective layer after the high-temperature annealing is finished.
Further, the method specifically comprises the following steps: and removing the silicon nitride layer by adopting a reactive ion etching mode.
Further, the method specifically comprises the following steps: under the heating condition, the oxide layer is removed by etching with a buffered oxide etching solution.
In some more specific embodiments, the method specifically includes: and performing Mg ion implantation on the gallium nitride material. The embodiments, implementations, principles, and so on of the present invention will be further explained with reference to the drawings and specific embodiments, and unless otherwise specified, the deposition, ion implantation, annealing, and so on processes used in the embodiments of the present invention may be known to those skilled in the art.
Referring to fig. 1, a method for implementing P-type doping of gan includes the following steps:
1) extending GaN samples with the thickness of about 2 mu m on a substrate such as sapphire and the like, and carrying out inorganic cleaning (such as acetone ultrasonic for 5min or isopropanol ultrasonic for 5min or deionized water ultrasonic for 5 min);
2) performing Mg ion implantation on the GaN sample;
3) depositing a 20nm oxide layer on the surface of the GaN sample by Atomic Layer Deposition (ALD), wherein the oxide layer can be Al2O3、SiO2、HfO2Etc.;
when the oxide layer is Al2O3The method specifically comprises the following steps: placing gallium nitride material in a reaction chamber, adjusting the temperature in the reaction chamber to 300 ℃, and adding trimethylaluminum and H in the form of gas pulses2O is alternately fed into the reaction chamber to deposit and form Al on the surface of the gallium nitride material2O3Layer, wherein the flow rate of the trimethylaluminum is 150sccm, the pulse time is 0.1s, the purge time is 6.0s, H2Introducing O with the flow rate of 200sccm, the pulse time of 0.1s and the purging time of 6.0s, and depositing to form Al2O3The rate of the layer is 0.093 nm/deposition cycle, the deposition temperature is 300 ℃, and the deposition time is 1 h;
when the oxide layer is SiO2The method specifically comprises the following steps: adding gallium nitrideThe material is placed in a reaction chamber, the temperature in the reaction chamber is adjusted to 250 ℃ and SiH is introduced in the form of a gas pulse4And ozone are alternately fed into the reaction chamber to deposit SiO on the surface of the gallium nitride material2Layer of, wherein, the SiH4The flow rate of the ozone is 120sccm, the pulse time is 0.2s, the purging time is 150s, the flow rate of the ozone is 70sccm, the pulse time is 5s, the purging time is 10s, and SiO is formed by deposition2The rate of the layer was 0.05 nm/deposition cycle and the deposition time was 4 h.
When the oxide layer is HfO2The method specifically comprises the following steps: gallium nitride material was placed in a reaction chamber, the temperature in the reaction chamber was adjusted to 250 ℃, and TDMHf and H were pulsed with gas2O is alternately fed into the reaction chamber to deposit and form HfO on the surface of the gallium nitride material2The TDMHf has the inlet flow of 50sccm, the pulse time of 1.2s, the purging time of 12.0s, and the H2The flow rate of the introduced O is 60sccm, the pulse time is 0.1s, the purging time is 6.0s, and the deposition is carried out to form HfO2The rate of the layer was 0.1 nm/deposition cycle and the deposition time was 40 min.
4) Forming a low-stress silicon nitride layer with a thickness of 300nm on the surface of the oxide layer by Low Pressure Chemical Vapor Deposition (LPCVD), wherein the growth parameters are shown in table 1, and the stacked oxide layer and the low-stress silicon nitride layer are used as protective layers:
TABLE 1 parameters for low stress silicon nitride layer by low pressure CVD
The reaction principle is as follows:
the total reaction time is 3h (wherein the preparation processes such as vacuumizing and the like are 1.5h), and the growth rate of the silicon nitride layer is 4.1 nm/min;
5) putting the sample obtained in the step 4) into a cavity of a Dayang acid MOCVD device at 1230℃,N2Annealing for 5min under the atmosphere, wherein the annealing pressure is about one atmospheric pressure, namely normal pressure;
6) after annealing activation, etching and removing low-stress SiN by adopting an RIE etching mode, wherein the etching rate is 70-80nm/min, and the etching parameters are as follows: CH (CH)4The flow rate of F is 313sccm, the flow rate of SF is 610sccm, the flow rate of Ar is 10sccm, the etching power is 100w, the air pressure is 70mtorr, and plasma etched by RIE is blocked by an oxide layer when RIE etching is carried out, so that a GaN sample cannot be influenced;
7) heating the sample treated in the step 6) in a BOE solution at 85 ℃ for 6h in a water bath to remove the oxide layer deposited by ALD, or firstly etching the oxide layer deposited by ALD by adopting an ICP dry etching mode, and then adopting concentrated sulfuric acid: cleaning the etched sample for about 1min by using a strong oxidizing solution with the ratio of hydrogen peroxide to hydrogen peroxide being 7:3 to remove stains during ALD deposition so as to prevent the influence on the aspects of electric leakage and the like on subsequent materials or device processes; by this method, no matter Al is used2O3、SiO2、HfO2Can be removed cleanly.
According to the embodiment of the invention, the oxide layer and the low-stress silicon nitride layer are sequentially arranged on the surface of the GaN sample to serve as a protection structure, Mg and SI ion selective region injection of the GaN sample can be protected and realized, P-type doping of the GaN sample is realized, the GaN sample is protected from decomposition after annealing activation, and in addition, the oxide layer and the low-stress silicon nitride layer can be easily removed after annealing activation, so that the GaN sample is prevented from being remained and polluted.
Comparative example 1
One method of comparative example 1 to achieve P-type doping of gallium nitride is substantially the same as that of example 1, except that: comparative example 1 is a method in which a low-stress silicon nitride layer is deposited on the surface of a GaN sample, an oxide layer is deposited on the low-stress silicon nitride layer, and the low-stress silicon nitride layer and the oxide layer, which are stacked, are used as a protective layer, however, the sample in comparative example 1 is decomposed when being annealed at 1230 ℃, so that a sample realizing P-type doping cannot be obtained, since defects on the surface of GaN cannot be densely covered, and the oxide formed by the ALD method only covers the SiN layer, thereby causing GaN to be decomposed from the defects at a temperature exceeding 1000 ℃.
Comparative example 2
One method of comparative example 2 to achieve P-type doping of gallium nitride is substantially the same as that of example 1, except that: comparative example 1 an oxide layer was deposited only on the surface of a GaN sample and used as a protective layer; however, the sample in comparative example 2 was decomposed when annealed at 1230 ℃, resulting in failure to obtain a sample that achieved P-type doping; this is because the ALD grown oxide is generally thin, about 20nm takes several hours, and if the ALD grown oxide is thick enough, it takes several days, which not only consumes cost but also damages the equipment, and at the same time, the ALD grown oxide can only shield part of the defects, resulting in decomposition of GaN from the defects at temperatures exceeding 1000 ℃.
Comparative example 3
One method of comparative example 3 to achieve P-type doping of gallium nitride is substantially the same as that of example 1, except that: comparative example 3 a low-stress silicon nitride layer having a thickness of 300nm was deposited only on the surface of the GaN sample and used as a protective layer, however, the sample in comparative example 3 was decomposed when annealed at 1230 c, resulting in failure to obtain a sample that achieved P-type doping.
The low-stress SiN grown only by LPCVD is taken as a protective layer to resist high-temperature corrosion and avoid stress influence, but the low-stress SiN is not compact enough, so that the GaN sample is ensured not to be influenced as a whole, but weak defect positions are not covered, the GaN sample is decomposed from the defect positions during annealing, and the low-stress SiN is difficult to achieve a good protective effect.
It should be noted that other technologies capable of realizing the protection of the gan annealing at high temperature are also disclosed in the prior art, for example:
the AlN film is used as a high-temperature annealing protection structure of the GaN sample, the AlN film comprises a 4nm AlN layer deposited at the temperature of 1100 ℃ and a 25nm AlN layer deposited at the temperature of 600 ℃, the AlN film can realize pulse annealing of the GaN sample at the temperature of 1300 ℃ for 30min without decomposition, and the AlN film is not easy to remove after the annealing is finished; the reason is that AlN and GaN belong to III-V nitride, tensile stress exists between the AlN film and the GaN, and the AlN film formed by adopting an epitaxial mode or a sputtering mode is thinner; if the AlN is removed by wet etching, the AlN thin film with good growth quality is hardly removed, and if the quality of the AlN thin film does not meet the specified requirement, the annealing protection effect is difficult to realize; if the AlN is etched by adopting the dry etching method, the etching gas components for etching the GaN and etching the AlN also contain-cl base, so the GaN is easily damaged in the etching process, and the GaN is mainly concentrated on the surface of the GaN by the activation of the ion implantation annealing, which is not beneficial to the process progress of a GaN-based device.
With GaOxNyThe protective film is used as a high-temperature annealing protective structure of the GaN sample, GaOxNyThe protective film can prevent the GaN sample from decomposing in annealing at normal pressure and 1150 ℃ for 5 min; wherein, the GaOxNyThe protective film is formed by performing N on the surface of a GaN sample in an Oxford Plasma Enhanced Chemical Vapor Deposition (PECVD) mode2The O plasma treatment is performed, the adopted plasma power is 20-150W, however, the GaOxNy protective film can not realize the annealing treatment of the gallium nitride sample under the temperature condition of more than 1200 ℃, and the GaOxNy protective film is difficult to remove.
According to the gallium nitride high-temperature annealing protection structure provided by the embodiment of the invention, the oxide layer grown in the ALD mode can cover the defects on the surface of the gallium nitride material, the low-stress silicon nitride layer grown in the LPCVD mode is used as a compact high-temperature protection layer and can avoid the influence of tensile stress in the annealing process, and the gallium nitride material can be protected from being annealed at the temperature of over 1200 ℃ without being decomposed through a specific growth sequence.
According to the method for protecting the high-temperature annealing activation of the gallium nitride, the oxide layer is formed by depositing in the ALD mode, the ALD deposition grows in the circulation mode, and the defects generated on the surface of the epitaxial GaN have a certain covering effect, so that the decomposition of the GaN defects can be avoided during high-temperature annealing, and the oxide film (layer) grown in the ALD deposition mode is compact and has a low speed due to the circulation mode, so that the uniformity of the obtained oxide film is better;
according to the method for protecting the high-temperature annealing activation of the gallium nitride, the oxide film grown in the ALD mode has small influence on the GaN sample during annealing, does not react with the GaN sample, and can play a role in passivation in the high-temperature annealing process to prevent the GaN sample from being decomposed.
According to the method for protecting the high-temperature annealing activation of the gallium nitride, provided by the embodiment of the invention, the low-stress SiN layer has a higher melting point as that of LPCVD-SiN of a standard program, and meanwhile, the adverse influence on GaN caused by the problem of higher stress in high-temperature annealing can be prevented, so that a good protection effect is achieved.
According to the method for realizing the gallium nitride P-type doping provided by the embodiment of the invention, the low-stress SiN layer and the ALD grown oxide layer can be completely removed, and the influence on a GaN sample in the removing process is small, unlike the larger influence on GaN in the removing process of the epitaxial AlN film.
The protective layer formed in the method for realizing the P-type doping of the gallium nitride provided by the embodiment of the invention can protect a GaN sample from being annealed at the temperature of more than 1230 ℃ in the atmosphere of normal pressure and nitrogen, and does not decompose in a short time.
It should be understood that the above-mentioned embodiments are merely illustrative of the technical concepts and features of the present invention, which are intended to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and therefore, the protection scope of the present invention is not limited thereby. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (10)
1. A high temperature annealing protection structure for gallium nitride is characterized by comprising: and sequentially laminating an oxide layer and a silicon nitride layer which are arranged on the surface of the gallium nitride material.
2. The gallium nitride high temperature anneal protection structure of claim 1, wherein: the oxide layer is grown by adopting an atomic layer deposition mode;
preferably, the material of the oxide layer includes Al2O3、SiO2、HfO2Any one or a combination of two or more of them;
preferably, the thickness of the oxide layer is 5nm to 30 nm;
and/or, the silicon nitride layer is grown by adopting a low-pressure chemical vapor deposition mode;
preferably, the silicon nitride layer comprises low stress silicon nitride;
preferably, the thickness of the silicon nitride layer is 200nm-300 nm.
3. A method for activating gallium nitride by high-temperature annealing is characterized by comprising the following steps: forming a gallium nitride high-temperature annealing protection structure according to any one of claims 1-2 on the surface of a gallium nitride material, and annealing the gallium nitride material at a temperature of 1200 ℃ or higher;
preferably, the temperature of the annealing is 1230-1250 ℃;
preferably, the annealing time is 5min-30 min.
4. A method for realizing gallium nitride P-type doping is characterized by comprising the following steps:
performing ion implantation on the gallium nitride material;
forming an oxide layer on the surface of the gallium nitride material by adopting an atomic layer deposition mode;
forming a low-stress silicon nitride layer on the surface of the oxide layer by adopting a low-pressure chemical vapor deposition mode;
and taking the oxide layer and the silicon nitride layer as protective layers, carrying out high-temperature annealing on the gallium nitride material, and activating acceptor impurities in the gallium nitride material to realize P-type doping of the gallium nitride material.
5. The method of claim 4, wherein: the material of the oxide layer comprises Al2O3、SiO2、HfO2Any ofOne or a combination of two or more; preferably, the thickness of the oxide layer is 5nm to 30 nm; and/or the thickness of the silicon nitride layer is 200nm-300 nm.
6. The method according to claim 4, characterized in that it comprises in particular: placing gallium nitride material in a reaction chamber, adjusting the temperature in the reaction chamber to 300-320 ℃, and adding trimethylaluminum and H in the form of gas pulse2O is alternately fed into the reaction chamber to deposit and form Al on the surface of the gallium nitride material2O3A layer;
preferably, the flow rate of the trimethylaluminum is 150sccm, the pulse time is 0.1s-0.2s, the purging time is 6.0s-10s, and the H is2The flow rate of the introduced O is 200sccm, the pulse time is 0.1s-0.2s, and the purging time is 6.0s-10 s;
preferably, Al is deposited2O3The rate of the layer was 0.093 nm/deposition cycle and the deposition time was 1 h.
7. The method according to claim 4, characterized in that it comprises in particular: gallium nitride material is placed in a reaction chamber, the temperature in the reaction chamber is regulated to 250-270 ℃, and SiH is added in the form of gas pulse4And ozone are alternately fed into the reaction chamber to deposit SiO on the surface of the gallium nitride material2A layer;
preferably, the SiH4The flow rate of the ozone is 120sccm, the pulse time is 0.1s-0.2s, the purging time is 150s-170s, the flow rate of the ozone is 70sccm, the pulse time is 5s, and the purging time is 10s-15 s;
preferably, the deposition forms SiO2The rate of the layer was 0.05 nm/deposition cycle and the deposition time was 4 h.
8. The method according to claim 4, characterized in that it comprises in particular: gallium nitride material was placed in a reaction chamber, the temperature in the reaction chamber was adjusted to 250 ℃, and TDMHf and H were pulsed with gas2O is alternately fed into the reaction chamber to deposit and form on the surface of the gallium nitride materialHfO2A layer;
preferably, the TDMHf has the introduction flow rate of 50sccm, the pulse time of 1-1.2s, the purging time of 10s-12.0s, and the H2The flow rate of the introduced O is 60sccm, the pulse time is 0.1s, and the purging time is 6.0s-10 s;
preferably, the deposition forms HfO2The rate of the layer was 0.1 nm/deposition cycle and the deposition time was 40 min.
9. The method according to claim 4, characterized in that it comprises in particular: the high-temperature annealing is carried out in a protective atmosphere at normal pressure, and the adopted temperature is over 1200 ℃ and the time is 5-30 min; preferably, the temperature of the high-temperature annealing is 1230-1250 ℃.
10. The method of claim 4, further comprising: after the high-temperature annealing is finished, removing the protective layer;
preferably, the method specifically comprises the following steps: removing the silicon nitride layer by adopting a reactive ion etching mode;
preferably, the method specifically comprises the following steps: under the heating condition, etching and removing the oxide layer by using a buffer oxide etching solution;
preferably, the method specifically comprises the following steps: and performing Mg ion implantation on the gallium nitride material.
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| CN113594028A (en) * | 2021-07-27 | 2021-11-02 | 中国科学院苏州纳米技术与纳米仿生研究所 | Gallium nitride p-type doping method, manufacturing method of GaN-based PN junction and application of GaN-based PN junction |
| WO2024050866A1 (en) * | 2022-09-07 | 2024-03-14 | 中国科学技术大学 | Gallium oxide device preparation method based on high-temperature annealing technology, and gallium oxide device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113594028A (en) * | 2021-07-27 | 2021-11-02 | 中国科学院苏州纳米技术与纳米仿生研究所 | Gallium nitride p-type doping method, manufacturing method of GaN-based PN junction and application of GaN-based PN junction |
| WO2024050866A1 (en) * | 2022-09-07 | 2024-03-14 | 中国科学技术大学 | Gallium oxide device preparation method based on high-temperature annealing technology, and gallium oxide device |
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