CN113161367A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN113161367A CN113161367A CN202110240792.XA CN202110240792A CN113161367A CN 113161367 A CN113161367 A CN 113161367A CN 202110240792 A CN202110240792 A CN 202110240792A CN 113161367 A CN113161367 A CN 113161367A
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
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Abstract
The invention relates to a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises a substrate and a film layer stacking structure, the film layer stacking structure is stacked along a first direction vertical to the substrate, and the manufacturing method comprises the following steps: forming a support structure in the semiconductor structure, a projection of the support structure on the substrate along the first direction being a support structure projection pattern; and forming a first auxiliary mark in the semiconductor structure, wherein the projection of the first auxiliary mark on the substrate along the first direction is a first projection pattern, and the first projection pattern is positioned inside the support structure projection pattern. In the semiconductor structure, the supporting structure plays a role in reinforcing and supporting the area where the first auxiliary mark is located, so that the problem that the first auxiliary mark cannot be applied due to the defect of the film structure can be avoided.
Description
Technical Field
The present invention relates to the field of integrated circuit manufacturing, and more particularly, to a semiconductor structure and a method for fabricating the same, which can prevent an auxiliary mark from being unusable due to a structural defect.
Background
With the development of the technology, the 3D NAND flash memory adopts a device structure of vertically stacking multiple layers of memory cells, and has a very high integration level. In the manufacturing process of the 3D NAND, stacking of a plurality of film layers is required, in which a photolithography process and an alignment process of a plurality of layers are involved. In the photoetching process flow, some auxiliary marks are designed according to the requirements of each process flow, for example, an overlay (OVL mark) error mark can be used for measuring overlay errors; an Alignment mark (Alignment mark) is for Alignment; the reference marks are used to locate or measure features to be formed, etc. However, due to the limitation of the process, some film layer structures have defects, and the defects can affect the use of the auxiliary mark, so that the auxiliary mark cannot play its role.
Disclosure of Invention
The invention aims to provide a semiconductor structure and a manufacturing method thereof, which avoid the limitation of auxiliary mark application caused by the defect of a film layer structure.
The present invention has been made to solve the above-mentioned problems, and an aspect of the present invention is a method for manufacturing a semiconductor structure, the semiconductor structure including a substrate and a film stack structure, the film stack structure being stacked in a first direction perpendicular to the substrate, the method including: forming a support structure in the semiconductor structure, a projection of the support structure on the substrate along the first direction being a support structure projection pattern; and forming a first auxiliary mark in the semiconductor structure, wherein the projection of the first auxiliary mark on the substrate along the first direction is a first projection pattern, and the first projection pattern is positioned inside the support structure projection pattern.
In an embodiment of the invention, the first projected pattern and the support structure projected pattern have an overlapping area.
In an embodiment of the invention, the support structure penetrates through part or all of the film stack structure along the first direction.
In an embodiment of the present invention, the step of forming a support structure in the semiconductor structure comprises: and forming a support structure in the semiconductor structure, and forming a vertical channel structure penetrating through the film layer stacking structure.
In an embodiment of the invention, the support structure includes a pillar structure extending along the first direction and penetrating through the film stack structure.
In an embodiment of the invention, the support structure includes a wall structure extending along the first direction and penetrating through the film stack structure.
In an embodiment of the invention, the support structure is formed by a dry etching method.
In an embodiment of the invention, before forming the support structure in the semiconductor structure, the method further includes: forming a second auxiliary mark in the semiconductor structure, wherein the projection of the second auxiliary mark on the substrate along the first direction is a second projection pattern, and the second projection pattern and the first projection pattern do not intersect.
In an embodiment of the invention, the second projection pattern is located at a periphery of the first projection pattern.
In an embodiment of the invention, the first projection pattern is located at a periphery of the second projection pattern.
The present invention further provides a semiconductor structure for solving the above technical problems, the semiconductor structure including a substrate and a film stack structure, the film stack structure being stacked along a first direction perpendicular to the substrate, the semiconductor structure including: a support structure formed in the semiconductor structure, a projection of the support structure onto the substrate along the first direction being a support structure projection pattern; and a first auxiliary mark formed in the semiconductor structure, wherein the projection of the first auxiliary mark on the substrate along the first direction is a first projection pattern, and the first projection pattern is positioned inside the support structure projection pattern.
In an embodiment of the invention, the first projected pattern and the support structure projected pattern have an overlapping area.
In an embodiment of the invention, the support structure penetrates through part or all of the film stack structure along the first direction.
In an embodiment of the invention, the semiconductor device further includes a vertical channel structure penetrating through the film stack structure, and the support structure and the vertical channel structure are formed in the same process step.
In an embodiment of the invention, the support structure includes a pillar structure extending along the first direction and penetrating through the film stack structure.
In an embodiment of the invention, the support structure includes a wall structure extending along the first direction and penetrating through the film stack structure.
In an embodiment of the invention, the semiconductor device further includes a second auxiliary mark formed in the semiconductor structure, a projection of the second auxiliary mark on the substrate along the first direction is a second projection pattern, and the second projection pattern and the first projection pattern do not intersect.
In an embodiment of the invention, the second projection pattern is located at a periphery of the first projection pattern.
In an embodiment of the invention, the first projection pattern is located at a periphery of the second projection pattern.
In an embodiment of the present invention, the first auxiliary mark and the second auxiliary mark are any combination of one or more of an overlay error mark, an alignment mark and an L-shaped mark, respectively.
In the process step of forming the semiconductor structure, the support structure and the first auxiliary mark are formed, so that the first projection pattern of the first auxiliary mark along the direction vertical to the substrate is positioned inside the projection pattern of the support structure along the direction vertical to the substrate, the support structure plays a role in reinforcing and supporting the area where the first auxiliary mark is positioned, and the problem that the first auxiliary mark cannot be applied due to the defect of the film structure can be avoided. Furthermore, in the semiconductor structure, the support structure can be formed simultaneously in the process step of forming the vertical channel structure, only the mask pattern of the process needs to be modified, no additional process step needs to be added, and the cost is saved.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
FIG. 1A is a schematic illustration of an overlay error mark;
FIG. 1B is a cross-sectional view of a semiconductor structure;
FIG. 1C is a schematic view of the semiconductor structure after removal of the second material layer of FIG. 1B;
FIG. 1D is a diagram illustrating a state in which a stacked structure of a semiconductor structure is collapsed;
FIG. 2 is an exemplary flow chart of a method of fabricating a semiconductor structure in accordance with one embodiment of the present invention;
FIG. 3 is a schematic diagram of a semiconductor structure in accordance with one embodiment of the present invention;
FIG. 4A is a schematic view of a projected pattern of a support structure in a method for fabricating a semiconductor structure according to an embodiment of the invention;
FIG. 4B is a schematic diagram of a support structure projection pattern and a first projection pattern in a method of fabricating a semiconductor structure according to an embodiment of the invention;
FIGS. 5A-5C are process diagrams of a method of fabricating a semiconductor structure according to another embodiment of the present invention;
FIGS. 6A-6C are schematic diagrams of a projected pattern of a support structure, a first projected pattern, and a second projected pattern in methods of fabricating a semiconductor structure according to three embodiments of the present invention;
FIGS. 7A-7C are schematic diagrams of a first auxiliary mark in a method of fabricating a semiconductor structure according to an embodiment of the present invention;
fig. 8 is a schematic top view of a semiconductor structure according to an embodiment of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of protection of the present application is not to be construed as being limited.
The term "three-dimensional (3D) memory device" as used herein refers to a semiconductor structure having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," e.g., NAND strings) on a laterally oriented substrate such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertically" means nominally perpendicular to a lateral surface of a substrate.
As used herein, the term "substrate" refers to a material upon which a subsequent layer of material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.
The term "layer" as used in this application refers to a portion of material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure or may have an extent less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between or at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, which may include one or more layers therein, and/or may have one or more layers thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
Flow charts are used herein to illustrate operations performed by systems according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes.
Fig. 1A is a schematic view of an overlay error mark, the view angle of which is from above. Referring to fig. 1A, the overlay error mark includes a first mark 110 and a second mark 120. Wherein the first mark 110 and the second mark 120 are bar patterns filled with different filling patterns. The first mark 110 and the second mark 120 may be provided on different masks in different process flows for measurement of overlay error.
FIG. 1B is a cross-sectional view of a semiconductor structure. Referring to fig. 1B, the semiconductor structure includes a substrate 130 and a stacked structure in which first material layers 131 and second material layers 132 are alternately stacked. A trench 140 is formed in the stacked structure through the stacked structure, and the trench 140 may be a gate line slit in a three-dimensional memory. The first material layer 131 may be a dielectric layer in a three-dimensional memory, and the second material layer 132 may be a dummy gate layer in a three-dimensional memory manufacturing process. In forming the semiconductor structure, the first mark 110 and the second mark 120 shown in fig. 1A may be involved in some process flows for alignment. For example, the first marker 110 is used in the first material layer 131 and the second marker 120 is used in the second material layer 132 in the stacked structure.
Fig. 1C is a schematic diagram of the semiconductor structure after removing the second material layer 132 in fig. 1B. Referring to fig. 1C, the second material layer 132 in the stacked structure is removed, forming a dummy gate layer void 133. These dummy gate layer voids 133 communicate with the trenches 140. Without support structure support or with less support structure support, the structure shown in FIG. 1C tends to collapse, resulting in the state shown in FIG. 1D.
Fig. 1D is a schematic diagram illustrating a state in which a stacked structure of the semiconductor structure is collapsed. Referring to fig. 1D, the stacked structure after removing the second material layer 132 collapses, which causes defects in the semiconductor structure, and such structural defects further cause the first mark 110 and/or the second mark 120 shown in fig. 1A to be unusable.
Fig. 2 is an exemplary flow chart of a method of fabricating a semiconductor structure in accordance with an embodiment of the present invention. Referring to fig. 2, the manufacturing method of this embodiment includes the following steps:
step S210: a support structure is formed in the semiconductor structure, a projection of the support structure onto the substrate along a first direction being a support structure projection pattern.
Step S220: a first auxiliary mark is formed in the semiconductor structure, and a projection of the first auxiliary mark on the substrate along a first direction is a first projection pattern, and the first projection pattern is positioned inside the support structure projection pattern.
A method of fabricating a semiconductor structure according to the present invention is described below with reference to fig. 2 and 3-4B.
Fig. 3 is a schematic diagram of a semiconductor structure according to an embodiment of the invention. Referring to fig. 3, the semiconductor structure of the present invention includes a substrate 310 and a film-layer stack structure 320, wherein the film-layer stack structure 320 is stacked along a first direction D1 perpendicular to the substrate 310. Figure 3 illustrates a side view of a semiconductor structure showing a portion of the semiconductor structure of the present invention.
Referring to fig. 3, the substrate 310 may be a Silicon substrate (Si), a Germanium substrate (Ge), a Silicon Germanium substrate (SiGe), a Silicon On Insulator (SOI), a Germanium On Insulator (GOI), or the like. In some embodiments, the substrate 310 may also be a substrate comprising other elemental or compound semiconductors, such as GaAs, InP, or SiC. But also a stacked structure such as Si/SiGe or the like. Other epitaxial structures may also be included, such as Silicon Germanium On Insulator (SGOI) and the like. In some embodiments, the substrate 310 may be made of a non-conductive material, such as glass, plastic, or sapphire wafers, among others. The substrate 310 shown in fig. 3 may have undergone some necessary processing, such as having formed a common active region and having undergone necessary cleaning, etc.
The film-layer stack structure 320 may be a stack in which first material layers 321 and second material layers 322 are alternately stacked. The first material layer 321 and the second material layer 322 may be materials selected from and include at least one insulating dielectric, such as silicon nitride, silicon oxide, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, and the like, and combinations thereof. The first material layer 321 and the second material layer 322 have different etch selectivity. For example, a combination of silicon nitride and silicon oxide, a combination of silicon oxide and undoped polysilicon or amorphous silicon, a combination of silicon oxide or silicon nitride and amorphous carbon, or the like may be used. The deposition method of the first material layer 321 and the second material layer 322 of the film stack structure 320 may include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), Atomic Layer Deposition (ALD), or a physical vapor deposition method such as Molecular Beam Epitaxy (MBE), thermal oxidation, evaporation, sputtering, and the like, among other methods. As shown in fig. 3, in the embodiment of the invention, the first material layer 321 is a dummy gate layer, and the second material layer 322 is a dielectric layer. The material for the gate sacrificial layer may be, for example, a silicon nitride layer. The material for the gate layer may be a conductive material such as tungsten, cobalt, copper, nickel, etc., or may be polysilicon, doped silicon, or any combination thereof. The material for the dielectric layer may be, for example, silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like.
In an embodiment of the present invention, the material of the substrate 310 is, for example, silicon. The first material layer 321 and the second material layer 322 are, for example, a combination of silicon nitride and silicon oxide. Taking the combination of silicon nitride and silicon oxide as an example, the film stack structure 320 may be formed by alternately depositing silicon nitride and silicon oxide on the substrate 310 in sequence by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or other suitable deposition methods.
Although exemplary configurations of the initial semiconductor structure are described herein, it will be appreciated that one or more features may be omitted, substituted, or added to the semiconductor structure. For example, various well regions may be formed in the substrate as desired. In addition, the materials of the various layers illustrated are merely exemplary, e.g., substrate 310 may also be other silicon-containing substrates, such as SOI (silicon on insulator), SiGe, Si: C, etc. The gate layer may also be other conductive layers such as tungsten, cobalt, nickel, etc. The second material layer may also be other dielectric materials such as aluminum oxide, hafnium oxide, tantalum oxide, and the like.
Referring to fig. 3, a trench 330 is further included in the semiconductor structure, and the trench 330 may be a gate line slit in a three-dimensional memory.
Referring to fig. 3, in step S210, a support structure 340 is formed in the semiconductor structure. In this embodiment, the support structure 340 includes a pillar structure extending along the first direction D1 and penetrating through the film stack structure 320. As shown in fig. 3, the support structure 340 includes a plurality of pillar structures extending along the first direction D1 and penetrating through the film stack structure 320.
In some embodiments, the support structure 340 is formed using a dry etching method.
In some embodiments, the support structure 340 extends through part or all of the film layer stack structure 320 along the first direction D1. The support structure 340 extends through the entirety of the film-layer stack structure 320 and into the interior of the substrate 310 as shown in fig. 3.
In some embodiments, the step of forming the support structure in the semiconductor structure of step S210 includes: the support structure 340 is formed in the semiconductor structure, and a vertical channel structure (not shown) is formed through the film stack structure 320. That is, the support structure 340 and the vertical channel structure are formed in the same process step. Therefore, in the manufacturing process, no additional process step is needed, only the mask pattern of the process for forming the vertical channel structure is needed to be modified, and the exposure area corresponding to the support structure 340 to be formed is increased, so that the support structure 340 and the vertical channel structure can be formed at the same time, and the cost can be saved.
In some embodiments, the vertical channel structure may be formed in a channel hole vertically passing through the film-layer stack structure 320, and thus the vertical channel structure may be cylindrical. The shape of the vertical channel structure may be the same as the shape of the support structure 340. The vertical channel structure may include a channel layer and a memory layer. Viewed from the whole, the memory layer and the channel layer are arranged in sequence from the outside to the inside along the radial direction of the vertical channel structure. The memory layer may include a blocking layer, a charge trapping layer, and a tunneling layer sequentially arranged from outside to inside in a radial direction of the vertical channel structure. A filling layer can be arranged in the channel layer. The filler layer may function as a support. The material of the fill layer may be silicon oxide. The filling layer can be solid or hollow without affecting the reliability of the device. The formation of the vertical channel structure may be accomplished using one or more thin film deposition processes, such as ALD, CVD, PVD, the like, or any combination thereof.
In some embodiments, the vertical channel structure is a dummy structure, which is not used for memory function, but is used for support and the like. In these embodiments, the vertical channel structure may be filled with an insulating material or a support material.
Fig. 4A is a schematic diagram of a projection pattern of a supporting structure in a method for fabricating a semiconductor structure according to an embodiment of the invention. Fig. 4A may be a top view of the semiconductor structure shown in fig. 3, from which the projection of the support structure 340 formed in step S210 onto the substrate 310 along the first direction D1, i.e., the support structure projection pattern 411, may be illustrated. The dashed box 410 in fig. 4A represents the area where the support structure projects the pattern 411. The square patterns are used to represent the support structure projection pattern 411 corresponding to the support structure 340 shown in fig. 3, and the support structure 340 is a square column.
The support structure projection pattern 411 in step S210 of the present invention refers to all the support structure projection patterns, and when a single support structure projection pattern is indexed by a label, the label refers specifically to the support structure projection pattern indicated by the label.
Fig. 3 and 4A are not intended to limit the number and specific locations of the support structures, nor the specific shape of the support structure projection pattern 411.
In other embodiments, the support structure projection pattern 411 may include a circular pattern, and the corresponding support structure 340 is a cylinder.
In other embodiments, the support structure 340 includes a wall-like structure extending along the first direction D1 and penetrating the film-layer stack structure 320. The corresponding support structure projection pattern 411 in fig. 4A may correspond to a striped pattern.
In some embodiments, the support structure 340 may include different structures such as a column structure, a wall structure, and the like.
In step S220, a first auxiliary mark (not shown) is formed in the semiconductor structure shown in fig. 3, and a projection of the first auxiliary mark on the substrate 310 along the first direction D1 is a first projection pattern.
Fig. 4B is a schematic diagram of a support structure projection pattern and a first projection pattern in a method for fabricating a semiconductor structure according to an embodiment of the invention. Referring to fig. 4B, the first projected pattern 420 has a rectangular shape, and a plurality of similar rectangles together constitute the first projected pattern 420. The first projection pattern 420 includes two kinds of first projection patterns 421 and 422 having different arrangement directions, in which the first projection pattern 421 extends along the X direction shown in fig. 4B, and the first projection pattern 422 extends along the Y direction perpendicular to the X direction.
Referring to fig. 4B, the first projected pattern 420 is located inside the region where the support structure projected pattern 411 is located, i.e., inside the dashed box 410.
The first projection patterns 420 in step S220 of the present invention refer to all the first projection patterns, and when a single first projection pattern is labeled with a label, the label refers specifically to the first projection pattern indicated by the label. In step S220, the first projected pattern 420 is located inside the support structure projected pattern 411, which means that the first projected pattern 420 is located inside the area where the support structure projected pattern 411 is located as a whole.
Fig. 4B is not intended to limit the specific shape, size, and number of the first projected patterns 420.
In some embodiments, the first projected pattern 420 and the support structure projected pattern 411 have an overlapping region. As shown in fig. 4B, the first projection pattern 420 having a rectangular shape has an overlapping region with some of the square support structure projection patterns 411, such as a first projection pattern 422a and a support structure projection pattern 411 a. As shown in fig. 4B, there are some support structure projection patterns that do not overlap the first projection pattern 420, such as support structure projection pattern 411B.
It is understood that the first projected pattern 420 and the support structure projected pattern 411 are concepts provided for explaining the first auxiliary mark and the support structure 340, and do not actually exist in the semiconductor structure. As shown in connection with fig. 3, fig. 4B may show the first auxiliary indicia and support structure 340 from a top or bottom view.
In some embodiments, the first projected pattern 420 shown in fig. 4B is the same shape as the actual first auxiliary mark. I.e. the first auxiliary mark is a planar marking.
According to the semiconductor structure shown in fig. 4B, since the region where the first auxiliary mark is located is surrounded by the region where the support structure 340 is located, the deformation or collapse of the partial region due to the defect of the film structure can be avoided, thereby improving the usability of the first auxiliary mark.
In some embodiments, the method for fabricating a semiconductor structure of the present invention may further include, before forming the support structure: and forming a second auxiliary mark in the semiconductor structure, wherein the projection of the second auxiliary mark on the substrate along the first direction is a second projection pattern, and the second projection pattern and the first projection pattern do not have intersection.
Fig. 5A-5C are process diagrams illustrating a method of fabricating a semiconductor structure according to another embodiment of the invention. Similar to fig. 4A-4B, fig. 5A-5C may also be top views corresponding to the semiconductor structure shown in fig. 3. Fig. 5A shows a projection of a second auxiliary mark onto the substrate 310 in a first direction D1, i.e. a second projected pattern 510. As shown in fig. 5A, a plurality of similar rectangles together form a second projected pattern 510, and a single second projected pattern 510 has a rectangular shape. Similarly to the first projection pattern 420 shown in fig. 4A, the second projection pattern 510 also includes a second projection pattern 511 extending in the X direction and a second projection pattern 512 extending in the Y direction.
As shown in fig. 5A, the second projection pattern 510 includes 4 relatively independent areas, including the second projection pattern area 501 and 504.
According to the embodiment shown in fig. 5A-5C, after the second auxiliary mark is formed, steps S210 and S220 shown in fig. 2 may be performed.
Referring to fig. 5B, the support structure 340 is formed according to step S210, the support structure 340 projecting the pattern 411 on the projection formed on the substrate 310 along the first direction D1. It is clear that the support structure projected pattern 411 does not intersect the second projected pattern 510. All of the support structure projection patterns 411 do not intersect with, and do not overlap, all of the second projection patterns 510.
Referring to fig. 5C, a first auxiliary mark is formed according to step S220, and the projection of the first auxiliary mark on the substrate 310 along the first direction D1 is a first projected pattern 420. Obviously, since the first projected pattern 420 is located inside the support structure projected pattern 411, the second projected pattern 510 and the first projected pattern 420 also do not intersect and overlap.
In the embodiment shown in fig. 5A-5C, the first auxiliary mark and the second auxiliary mark may be used in pairs. In the process steps, the second auxiliary mark is formed in a previously performed step, and in order that the first auxiliary mark formed later may not be used due to a film structure defect, the support structure 340 is formed in an intermediate step. Since the support structure projection pattern 411 surrounds the first projection pattern 420, and supports the first auxiliary mark, the above-mentioned problems can be avoided, and the first auxiliary mark and the second auxiliary mark can be used normally.
In some embodiments, the second projected pattern 510 is located at the periphery of the first projected pattern 420. In this embodiment, the first projected pattern 420 is located in a region that extends outward from the center of the overall pattern, forming a contiguous sheet of regions, as shown in FIG. 5C. The second projected pattern 510 is located at the periphery of the first projected pattern 420, that is, the second projected pattern 510 does not occupy the center of the overall pattern, but surrounds only the periphery of the central region where the first projected pattern 420 is located. The 4 independent areas in the second projected pattern 510 are all located at the periphery of the first projected pattern 420.
In some embodiments, the first projected pattern 420 may also be located at the periphery of the second projected pattern 510.
Fig. 6A-6C are schematic diagrams of a support structure projection pattern, a first projection pattern, and a second projection pattern in methods of fabricating a semiconductor structure according to three embodiments of the present invention.
Referring to fig. 6A, in this embodiment, the first projected pattern 620 is located at the inner side of the support structure projected pattern 610, and the first projected pattern 620 is located at the outer periphery of the second projected pattern 630, and it is apparent that the support structure projected pattern 610 is also located at the outer periphery of the second projected pattern 630.
Referring to fig. 6B, in this embodiment, the first projected pattern 620 is located inside the support structure projected pattern 610, the first projected pattern 620 is located at the periphery of the second projected pattern 632, and the second projected pattern 631 is located at the periphery of the first projected pattern 620, that is, the first projected pattern 620 is located between the second projected pattern 631 and the second projected pattern 632. According to this embodiment, the second projected patterns 631 and 632 may be projected patterns of auxiliary marks formed in the same process step, or may be projected patterns of auxiliary marks formed in different process steps.
Referring to fig. 6C, in this embodiment, the support structure projection pattern 640 is not a multi-square projection as shown in fig. 6A-6B, but is a whole. In this embodiment, the support structure corresponding to the support structure projection pattern 640 is an integral structure in the film stack structure, and a support material or an insulating material may be filled in the integral structure to support the film stack structure. The first projected pattern 620 is inside the support structure projected pattern 640, and the second projected pattern 630 is located at the periphery of the support structure projected pattern 640 and the first projected pattern 620.
The present invention does not limit the type and use of the first auxiliary mark and the second auxiliary mark, and may be an overlay error measurement mark, an alignment mark, or the like.
Fig. 7A-7C are schematic diagrams of first auxiliary marks in a method for fabricating a semiconductor structure according to an embodiment of the invention. Fig. 7A is a top view of a BiB (box in box) type mark, in which a first projection pattern 710 of a first auxiliary mark is a large square shape, a second projection pattern 720 of a second auxiliary mark is a rectangular long bar shape, and four second projection patterns 720 surround one first projection pattern 710 to form a BiB shape in which a large rectangle is surrounded by a small rectangle. In this embodiment, the first projected pattern 710 is located inside the support structure projected pattern 730, and there is an overlap between the first projected pattern 710 and the support structure projected pattern 730, and some rectangular support structure projected patterns 730 are covered by the first projected pattern 710.
Fig. 7B is a top view of an L-shaped first auxiliary mark. Here, the first projection pattern 711 of the first auxiliary mark has an L shape, and some rectangular patterns, which are a part of the support structure projection pattern 731, are surrounded around the first projection pattern 711. The first projection pattern 711 is located inside the support structure projection pattern 731, and there is an overlap between the first projection pattern 711 and the support structure projection pattern 731, and some rectangular support structure projection patterns 731 are covered by the first projection pattern 711.
Fig. 7C is a top view of a first auxiliary mark of a line type. A first projected pattern 712 in which a plurality of mutually parallel straight lines are first auxiliary marks, the first projected pattern 712 being located inside a support structure projected pattern 732 including a plurality of rectangular patterns, and there being an overlap between the first projected pattern 712 and the support structure projected pattern 732, some of the rectangular support structure projected patterns 732 being covered by the first projected pattern 712.
In a preferred embodiment of the present invention, a first auxiliary mark and a second auxiliary mark of Advanced Imaging Metrology (AIM) type are used. The AIM-type auxiliary mark is a grating structure consisting of a plurality of lines and has a relatively high measurement signal-to-noise ratio.
The invention also includes a semiconductor structure comprising a substrate and a film stack, the film stack being stacked in a first direction perpendicular to the substrate, the semiconductor structure comprising a support structure formed in the semiconductor structure, a projection of the support structure onto the substrate in the first direction being a support structure projection pattern; and a first auxiliary mark formed in the semiconductor structure, wherein the projection of the first auxiliary mark on the substrate along the first direction is a first projection pattern, and the first projection pattern is positioned inside the support structure projection pattern. Figure 4B illustrates one embodiment of a semiconductor structure that may be used to illustrate the present invention.
The semiconductor structure of the present invention can be formed by the manufacturing method described above, and therefore, the description of the manufacturing method and the drawings can be used to describe the semiconductor structure of the present invention. The repeated content is not expanded here.
In some embodiments, the first projected pattern and the support structure projected pattern have an overlapping region, as shown in fig. 4B, 5C, 6A-6C, 7A-7C.
In some embodiments, the support structure extends through some or all of the film layer stack structure in the first direction, as shown in fig. 3.
In some embodiments, the semiconductor structure of the present invention is a three-dimensional memory, and the film stack structure is a stack structure formed by alternately stacking gate layers and dielectric layers. The semiconductor structure further includes a vertical channel structure extending through the film stack structure, the support structure being formed in the same process step as the vertical channel structure.
In some embodiments, the support structure includes a columnar structure extending in the first direction and through the film layer stack structure.
In some embodiments, the support structure includes a wall-like structure extending in the first direction and through the film-layer stack structure.
In some embodiments, the semiconductor device further includes a second auxiliary mark formed in the semiconductor structure, a projection of the second auxiliary mark on the substrate along the first direction is a second projection pattern, and the second projection pattern and the first projection pattern do not intersect. As shown in fig. 5C, 6A-6C.
In some embodiments, the second projected pattern is located at a periphery of the first projected pattern. As shown in fig. 5C, 6B, 6C.
In some embodiments, the first projected pattern is located at the periphery of the second projected pattern. As shown in fig. 6A and 6B.
In some embodiments, the first auxiliary mark and the second auxiliary mark are any combination of one or more of an overlay error mark, an alignment mark and an L-shaped mark, respectively.
Fig. 8 is a schematic top view of a semiconductor structure according to an embodiment of the invention. The semiconductor structure of this embodiment is formed by the method of manufacturing a semiconductor structure of the present invention, and fig. 8 is drawn from a photograph of the semiconductor structure taken from a top view. The first projected pattern 810 of the first auxiliary mark is composed of a plurality of linear marks, and the projected pattern 820 of the support structure includes a plurality of small holes, which indicates that the support structure is a plurality of columnar structures. The first projected pattern 810 is located inside the support structure projected pattern 820.
The first projection pattern in the semiconductor structure is positioned in the support structure pattern, so that the problem that the first auxiliary mark cannot be normally used due to the defects of the film layer structure can be avoided.
Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.
Claims (20)
1. A method of fabricating a semiconductor structure, the semiconductor structure comprising a substrate and a film stack, the film stack being stacked in a first direction perpendicular to the substrate, the method comprising:
forming a support structure in the semiconductor structure, a projection of the support structure on the substrate along the first direction being a support structure projection pattern; and
forming a first auxiliary mark in the semiconductor structure, wherein the projection of the first auxiliary mark on the substrate along the first direction is a first projection pattern, and the first projection pattern is positioned inside the support structure projection pattern.
2. The method of manufacturing of claim 1, wherein the first projected pattern and the support structure projected pattern have an overlapping region.
3. The method of manufacturing of claim 1, wherein the support structure extends through part or all of the film layer stack structure along the first direction.
4. The method of claim 1, wherein forming a support structure in the semiconductor structure comprises: and forming a support structure in the semiconductor structure, and forming a vertical channel structure penetrating through the film layer stacking structure.
5. The method of claim 1, wherein the support structure comprises a pillar structure extending along the first direction and through the film stack structure.
6. The method of claim 1, wherein the support structure comprises a wall-like structure extending along the first direction and through the film-layer stack structure.
7. The method of claim 1, wherein the support structure is formed using a dry etching process.
8. The method of fabricating of claim 1, further comprising, prior to forming the support structure in the semiconductor structure: forming a second auxiliary mark in the semiconductor structure, wherein the projection of the second auxiliary mark on the substrate along the first direction is a second projection pattern, and the second projection pattern and the first projection pattern do not intersect.
9. The method of claim 8, wherein the second projected pattern is located at a periphery of the first projected pattern.
10. The method of claim 8, wherein the first projected pattern is located at a periphery of the second projected pattern.
11. A semiconductor structure comprising a substrate and a film stack stacked in a first direction perpendicular to the substrate, comprising:
a support structure formed in the semiconductor structure, a projection of the support structure onto the substrate along the first direction being a support structure projection pattern; and
a first auxiliary mark formed in the semiconductor structure, a projection of the first auxiliary mark on the substrate along the first direction being a first projected pattern, the first projected pattern being located inside the support structure projected pattern.
12. The semiconductor structure of claim 11, wherein the first projected pattern and the support structure projected pattern have an overlapping region.
13. The semiconductor structure of claim 11, wherein the support structure extends through some or all of the film layer stack structure along the first direction.
14. The semiconductor structure of claim 11, further comprising a vertical channel structure extending through the film stack structure, the support structure being formed in a same process step as the vertical channel structure.
15. The semiconductor structure of claim 11, wherein the support structure comprises a columnar structure extending along the first direction and through the film layer stack structure.
16. The semiconductor structure of claim 11, wherein the support structure comprises a wall structure extending along the first direction and through the film stack structure.
17. The semiconductor structure of claim 11, further comprising a second auxiliary mark formed in the semiconductor structure, a projection of the second auxiliary mark on the substrate along the first direction being a second projected pattern, the second projected pattern and the first projected pattern not intersecting.
18. The semiconductor structure of claim 17, wherein the second projected pattern is located at a periphery of the first projected pattern.
19. The semiconductor structure of claim 17, wherein the first projected pattern is located at a periphery of the second projected pattern.
20. The semiconductor structure of claim 17, wherein the first auxiliary mark and the second auxiliary mark are one or any combination of an overlay error mark, an alignment mark and an L-shaped mark, respectively.
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