CN113161357A - Semiconductor structure and forming method thereof - Google Patents

Abstract

The disclosure provides a semiconductor structure and a forming method thereof, and relates to the technical field of semiconductors. The forming method comprises the following steps: providing a substrate comprising an array region and an open area surrounding the array region; forming a reference semiconductor layer covering the open region; performing a first etching process on the reference semiconductor layer to reduce a distance between a boundary of the reference semiconductor layer and an edge of the array region; and carrying out second etching treatment on the reference semiconductor layer to form a target semiconductor layer, wherein the target semiconductor layer has a flat surface in a direction vertical to the substrate. The forming method of the semiconductor structure can prevent the short circuit of the interconnection structure and reduce the failure risk of the device.

Description

Semiconductor structure and forming method thereof

Technical Field

The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.

Background

Dynamic Random Access Memory (DRAM) has the advantages of small size, high integration degree, high transmission speed, and the like, and is widely used in mobile devices such as mobile phones and tablet computers. The interconnection structure is used as a core component of the dynamic random access memory and is mainly used for leading out the capacitor array electrically.

In the manufacturing process, an insulating layer is usually required to be filled outside the capacitor array, but an air gap is easily formed in the insulating layer under the influence of the capacitor array structure, so that each interconnection structure formed in the insulating layer is short-circuited, and the device fails.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure is directed to overcoming the above-mentioned deficiencies in the prior art and providing a semiconductor structure and a method for forming the same, which can prevent the short circuit of the interconnect structure and reduce the risk of device failure.

According to an aspect of the present disclosure, there is provided a method of forming a semiconductor structure, including:

providing a substrate comprising an array region and an open area surrounding the array region;

forming a reference semiconductor layer covering the open region;

performing a first etching process on the reference semiconductor layer to reduce a distance between a boundary of the reference semiconductor layer and an edge of the array region;

and carrying out second etching treatment on the reference semiconductor layer to form a target semiconductor layer, wherein the target semiconductor layer has a flat surface in a direction vertical to the substrate.

In an exemplary embodiment of the present disclosure, a boundary of the reference semiconductor layer away from the array region has a first distance from an edge of the array region in a direction parallel to the substrate; after the first etching treatment is carried out on the reference semiconductor layer, the boundary of the reference semiconductor layer has a second distance with the edge of the array region; the boundary of the target semiconductor layer far away from the array region and the edge of the array region have a target distance, and the difference between the second distance and the target distance is smaller than the difference between the first distance and the second distance.

In an exemplary embodiment of the present disclosure, the array region is formed with a capacitor array, the capacitor array has an outer edge of an irregular topography in a direction perpendicular to the substrate, and the outer edge of the irregular topography has at least one protrusion in a direction parallel to the substrate, a height of the protrusion is not greater than the target distance, and the target semiconductor layer can completely cover the protrusion.

In an exemplary embodiment of the present disclosure, the first etching process includes a wet etching process, and the second etching process includes a dry etching process.

In one exemplary embodiment of the present disclosure, the reference semiconductor layer is subjected to a second etching process to form a target semiconductor layer having a flat surface in a direction perpendicular to the substrate:

performing a photoetching process on the array region to form a mask pattern, and defining the target distance by using the mask pattern;

and performing the second etching treatment by taking the mask pattern as a mask.

In an exemplary embodiment of the present disclosure, the array region is disposed adjacent to the open region, and the target semiconductor layer covers both the array region and the open region.

In an exemplary embodiment of the present disclosure, the substrate further includes a peripheral region, the open region is located between the peripheral region and the array region, and the reference semiconductor layer is simultaneously formed in the peripheral region while the reference semiconductor layer covering the open region is formed.

In an exemplary embodiment of the present disclosure, after the first etching process is performed on the reference semiconductor layer, the reference semiconductor layer remains in the peripheral region, and a surface of the reference semiconductor layer remaining in the peripheral region is lower than a surface of the reference semiconductor layer in the open region.

In an exemplary embodiment of the present disclosure, after the second etching process is performed on the reference semiconductor layer, the reference semiconductor layer of the peripheral region is completely removed.

In an exemplary embodiment of the present disclosure, the array region includes a plurality of capacitor plugs arranged at intervals, and the forming of the capacitor array on the array region includes:

forming a sacrificial layer and a supporting layer which are sequentially distributed in an overlapped mode on the surface of the array area;

etching the sacrificial layer and the support layer by taking the substrate as an etching stop layer so as to form a plurality of capacitor holes which are distributed at intervals in the sacrificial layer and the support layer, wherein each capacitor hole is communicated with each capacitor plug in a one-to-one correspondence manner;

forming a first electrode layer in the capacitor hole, wherein the first electrode layer is in contact connection with the capacitor plug;

removing each sacrificial layer;

forming a dielectric layer on the outer surface and the inner surface of a structure formed by the first electrode layer and the support layer;

and forming a second electrode layer on the surface of the dielectric layer.

In an exemplary embodiment of the present disclosure, further comprising:

an insulating layer is formed overlying the peripheral region and the target semiconductor layer.

In an exemplary embodiment of the present disclosure, the peripheral region includes a conductive contact plug, and the forming method further includes:

and forming a first interconnection structure in the peripheral region, wherein the first interconnection structure is formed in the insulating layer and is in contact connection with the conductive contact plug.

In an exemplary embodiment of the present disclosure, the forming method further includes:

and forming a second interconnection structure in the insulating layer on the surface of the target semiconductor layer, wherein the second interconnection structure is communicated with the target semiconductor layer.

In one exemplary embodiment of the present disclosure, forming the first and second interconnect structures includes:

etching the insulating layer by using the conductive contact plug of the peripheral area as an etching stop layer to form a first via hole;

forming a first interconnect structure in the first via;

etching the insulating layer on the surface of the target semiconductor layer by taking the target semiconductor layer as an etching stop layer to form a second through hole;

and forming a second interconnection structure in the second via hole.

According to an aspect of the present disclosure, there is provided a semiconductor structure formed by the method of forming a semiconductor structure of any one of the above.

According to the semiconductor structure and the forming method thereof, the thickness of the reference semiconductor layer located at the edge of the open area can be reduced through the first etching treatment, so that the edge of the open area and the middle area thereof can be simultaneously etched to the surface of the substrate in the second etching process, the subsequently formed interconnection structure is ensured to be in contact with the substrate, and the interconnection structure is prevented from being short-circuited. Meanwhile, the target semiconductor layer formed by etching has a flat surface in the direction vertical to the substrate, so that air gaps cannot be generated due to uneven edge portions when an insulating layer is formed subsequently, and therefore the phenomenon that all interconnection structures formed in the insulating layer are connected together through the air gaps to cause short circuit is avoided, and the risk of device failure is reduced.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 is a schematic diagram of a semiconductor structure in the related art.

Fig. 2 is a schematic view illustrating formation of an air gap in the related art.

Fig. 3 is a schematic diagram of an interconnect structure in the related art.

Fig. 4 is a top view of an interconnect structure in the related art.

Fig. 5 is a flow chart of a method of forming a semiconductor structure in an embodiment of the present disclosure.

Fig. 6 is a schematic diagram of a capacitor array in an embodiment of the disclosure.

Fig. 7 is a flow chart of forming a capacitor array in an embodiment of the disclosure.

Fig. 8 is a schematic diagram of a capacitive aperture in an embodiment of the disclosure.

Fig. 9 is a schematic view of a first electrode layer in an embodiment of the present disclosure.

Fig. 10 is a schematic view of a layer of masking material in an embodiment of the disclosure.

Fig. 11 is a schematic structural diagram of the sacrificial layer exposed after etching the mask material layer according to the embodiment of the disclosure.

Fig. 12 is a schematic diagram after step S240 is completed in the embodiment of the present disclosure.

Fig. 13 is a schematic view of a reference semiconductor layer in an embodiment of the disclosure.

Fig. 14 is a schematic diagram after step S130 is completed in the embodiment of the present disclosure.

Fig. 15 is a schematic diagram after step S140 is completed in the embodiment of the present disclosure.

Fig. 16 is a schematic diagram after step S1410 is completed in the embodiment of the present disclosure.

Fig. 17 is a schematic diagram after step S150 is completed in the embodiment of the present disclosure.

Fig. 18 is a flowchart of step S150 in the embodiment of the present disclosure.

Fig. 19 is a flow chart of a method of forming a semiconductor structure in another embodiment of the present disclosure.

Fig. 20 is a schematic diagram of an interconnect structure in an embodiment of the disclosure.

Fig. 21 is a flow chart of a method of forming a semiconductor structure in another embodiment of the present disclosure.

Fig. 22 is a schematic diagram of a first via and a second via in an embodiment of the disclosure.

In the figure: 100. a substrate; 200. a capacitor array; 201. a support layer; 202. a semiconductor layer; 203. an insulating layer; 2031. an air gap; 204. an interconnect structure; 1. a substrate; 11. a conductive contact plug; 2. a capacitor array; 21. a first sacrificial layer; 22. a first support layer; 23. a second sacrificial layer; 24. a second support layer; 25. a first electrode layer; 26. a dielectric layer; 27. a second electrode layer; 210. a protrusion; 220. a capacitor hole; 230. a layer of masking material; 240. a photoresist layer; 3. a reference semiconductor layer; 4. a target semiconductor layer; 5. an insulating layer; 51. a first via hole; 52. a second via hole; 501. a first interconnect structure; 502. a second interconnect structure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.

The terms "a," "an," "the," and "said" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc. The terms "first" and "second" are used merely as labels, and are not limiting on the number of their objects.

In the related art, as shown in fig. 1-4, a semiconductor structure mainly includes a substrate 100 and a capacitor array 200 formed on the substrate 100, in order to prevent short circuit caused by collapse between capacitors in the capacitor array 200, a support layer 201 is required to be disposed at the periphery of the capacitors to laterally support the capacitors. However, since the supporting layer 201 is usually located outside the capacitor array 200, the edge portion of the capacitor array 200 exhibits a concave-convex structure in a direction perpendicular to the substrate, so that the edge of the semiconductor layer 202 filled in the capacitor array 200 is not flat due to the concave-convex structure, when the insulating layer 203 is formed later, the air gap 2031 is easily generated due to the uneven edge portion, and thus, the interconnection structures 204 formed in the insulating layer 203 are connected together through the air gap 2031 to cause a short circuit, thereby causing device failure.

The embodiment of the present disclosure provides a method for forming a semiconductor structure, which may be a Dynamic Random Access Memory (DRAM), as shown in fig. 5, the method for forming may include steps S110 to S140, wherein:

step S110, providing a substrate, wherein the substrate comprises an array area and an open area surrounding the array area;

step S120 of forming a reference semiconductor layer covering the open region;

step S130 of performing a first etching process on the reference semiconductor layer to reduce a distance between a boundary of the reference semiconductor layer and an edge of the array region;

step S140, performing a second etching process on the reference semiconductor layer to form a target semiconductor layer having a flat surface in a direction perpendicular to the substrate.

According to the forming method of the semiconductor structure, the thickness of the reference semiconductor layer located at the edge of the open area can be reduced through the first etching treatment, so that the edge of the open area and the middle area of the open area can be etched to the surface of the substrate at the same time in the second etching process, the subsequently formed interconnection structure is ensured to be in contact with the substrate, and the interconnection structure is prevented from being short-circuited. Meanwhile, the target semiconductor layer formed by etching has a flat surface in the direction vertical to the substrate, so that air gaps cannot be generated due to uneven edge portions when an insulating layer is formed subsequently, and therefore the phenomenon that all interconnection structures formed in the insulating layer are connected together through the air gaps to cause short circuit is avoided, and the risk of device failure is reduced.

The following describes in detail the steps of the forming method of the disclosed embodiments:

as shown in fig. 5, in step S110, a substrate is provided, the substrate including an array region and an open region surrounding the array region.

As shown in fig. 6, the substrate 1 may have a flat plate structure, which may have a rectangular shape, a circular shape, an oval shape, a polygonal shape, or an irregular pattern, and the material thereof may be silicon or other semiconductor materials, and the shape and the material of the substrate 1 are not particularly limited.

A plurality of conductive contact plugs 11 may be formed in the substrate 1 at intervals, for example, a plurality of via holes may be formed in the substrate 1 at intervals through an opening process, and then a conductive material may be deposited in each opening by vacuum evaporation, magnetron sputtering, or chemical vapor deposition, so as to form the conductive contact plug 11 in each opening, but of course, the conductive contact plugs 11 may also be formed in other manners, which are not listed here.

The substrate 1 may have an array region and an open region, the array region and the open region may be distributed adjacently, the open region may surround the periphery of the array region, the array region may be used to form the capacitor array 2, and the open region may be used to form other circuit structures. For example, the array region may be a circular region, a rectangular region or an irregular pattern region, and may also be a region with other shapes, which is not limited herein. The open area may be an annular area and may surround the periphery of the array area, which may be a circular annular area, a rectangular annular area, or an annular area of other shapes, which are not listed here.

It should be noted that, conductive contact plugs 11 may be distributed in both the array region and the open region, wherein: the array area can comprise a plurality of conductive contact plugs 11 which are arranged at intervals, and each conductive contact plug 11 positioned in the array area can be used as a capacitor plug and can be respectively connected with each capacitor in the array area in a one-to-one correspondence manner; conductive contact plugs 11 in the open area may be connected to the interconnect structure and may be used to electrically drain the capacitor array 2.

The capacitor array 2 may be formed on the substrate 1, the capacitor array 2 may be located in the array region, and in an embodiment of the present disclosure, the capacitor array 2 has an outer edge with an irregular profile in a direction perpendicular to the substrate 1, and the outer edge with the irregular profile has at least one protrusion 210 in a direction parallel to the substrate 1. For example, the capacitor array 2 may include a plurality of pillar capacitors arranged at intervals, and each pillar capacitor may be connected to a corresponding contact of each capacitor plug located in the array region. When in use, the plurality of columnar capacitors can be charged and discharged simultaneously, thereby improving the capacitance.

In one embodiment of the present disclosure, as shown in fig. 6, each of the pillar capacitors may include a first electrode layer 25, a support layer, a dielectric layer 26, and a second electrode layer 27, wherein:

the first electrode layer 25 may be a stripe shape, which may be formed in the array region of the substrate 1 and may be in contact connection with a capacitor plug, and which may extend along a direction perpendicular to the substrate 1 to a side away from the substrate 1 so as to form a pillar capacitor. The support layer may be located at the periphery of the first electrode layer 25, and may laterally support the first electrode layer 25, for example, the support layer may include a first support layer 22 and a second support layer 24, the first support layer 22 may surround the middle of the first electrode layer 25, and may support the middle of the first electrode layer 25, so as to prevent the middle of the first electrode layer 25 from deforming, and prevent the first electrode layer 25 from being shorted with the surrounding cylindrical capacitor; the second support layer 24 may surround the periphery of the end of the first electrode layer 25 away from the substrate 1, and may support the end of the first electrode layer 25 away from the substrate 1, so as to prevent the end of the first electrode layer 25 from being deformed, and further reduce the risk of short circuit of the capacitor array 2, and the first support layer 22 and the second support layer 24 may form an electrode support structure, so as to laterally support each portion of the first electrode layer 25. The dielectric layer 26 may be attached to the inner and outer surfaces of the structure formed by the first electrode layer 25 and the support layer. The second electrode layer 27 is attached to the surface of the dielectric layer 26, so that a double-sided capacitor can be formed in the array region. In this process, since the support layer is formed on the outer periphery of different portions of the first electrode layer 25, the edge portion of the finally formed capacitor array 2 has a protrusion 210 in a direction parallel to the substrate 1.

Furthermore, the substrate 1 may further include a peripheral region, and the peripheral region may be located on a side of the open region away from the array region and may be distributed adjacent to the open region, that is: the open area may be located between the peripheral region and the array region. The peripheral region may also be formed with conductive contact plugs 11, and an interconnect structure may be formed in the peripheral region, and the interconnect structure may be in contact connection with the conductive contact plugs 11 of the peripheral region to electrically lead out the capacitor array 2.

It should be noted that the interconnect structure in the peripheral region and the interconnect structure in the open region may be the same interconnect structure, that is, the interconnect structure may span the open region and the peripheral region, and of course, the interconnect structure may also be formed in any one of the open region and the peripheral region, which is not limited herein.

In an exemplary embodiment of the present disclosure, as shown in fig. 7, forming the capacitor array 2 in the array region may include steps S210 to S260, wherein:

step S210, forming a sacrificial layer and a support layer which are sequentially distributed in an overlapped mode on the surface of the array area.

The sacrificial layer and the supporting layer which are distributed in an overlapping manner can be sequentially formed on the surface of the substrate 1 by means of chemical vapor deposition, physical vapor deposition or atomic layer deposition, and the sacrificial layer and the supporting layer can be formed at least in the array area of the substrate 1. As shown in fig. 8, an atomic layer deposition process may be used to sequentially form a first sacrificial layer 21, a first support layer 22, a second sacrificial layer 23, and a second support layer 24 on the surface of the array region of the substrate 1. The first sacrificial layer 21 may be formed on the surface of the substrate 1; the first support layer 22 may be formed on a surface of the first sacrificial layer 21 facing away from the substrate 1; the second sacrificial layer 23 may be formed on the surface of the first support layer 22 facing away from the substrate 1, and may be the same as the material of the first sacrificial layer 21; the second support layer 24 may be formed on a surface of the second sacrificial layer 23 facing away from the substrate 1, which may be the same material as the first support layer 22.

It is noted that each support layer may be made of an insulating material, for example, Si₃N₄Or SiCN, but of course, other insulating materials are also possible, and are not listed here.

Step S220, etching the sacrificial layer and the support layer by using the substrate as an etching stop layer, so as to form a plurality of capacitor holes arranged at intervals in the sacrificial layer and the support layer, wherein each capacitor hole is in one-to-one correspondence with each capacitor plug.

A photoresist layer may be formed on the second support layer 24 by spin coating or other methods, and the material of the photoresist layer may be a positive photoresist or a negative photoresist, which is not particularly limited herein. The photoresist layer may be exposed using a mask having a pattern that matches the pattern required for the capacitor holes 220, and the orthographic projection of the pattern on the substrate 1 may be aligned with each capacitor plug of the array region. The exposed photoresist layer may then be developed to form a development zone, which may expose the second supporting layer 24, and which may have the same pattern as the desired pattern of the capacitor holes 220, and which may have the same size as the desired capacitor holes 220. Each support layer and each sacrificial layer may be etched in the development area by dry etching to form a plurality of capacitor holes 220 arranged at intervals, each capacitor hole 220 may expose each capacitor plug located in the array area in a one-to-one correspondence, and the structure after step S220 is completed is as shown in fig. 8.

Step S230, forming a first electrode layer in the capacitor hole, where the first electrode layer is in contact connection with the capacitor plug.

The first electrode layer 25 attached to the capacitor holes 220 may be formed in each capacitor hole 220, and the first electrode layer 25 may be in contact connection with the capacitor plug through the capacitor hole 220. For example, the first electrode layer 25 may be formed in the capacitor hole 220 by a chemical vapor deposition process, but the first electrode layer 25 may also be formed by other processes, which are not limited herein. The structure after completion of step S220 is shown in fig. 9.

Step S240, removing each sacrificial layer.

As shown in fig. 10, a masking material layer 230 may be formed by chemical vapor deposition or other means on a side of the support layer farthest from the substrate 1 facing away from the substrate 1, and the masking material layer 230 may cover a side of the capacitor hole 220 facing away from the capacitor plug. The material of the mask material layer 230 may be at least one of silicon, silicon oxide, silicon nitride, oxynitride or carbon, and of course, other materials may be used, which are not listed here. The masking material layer 230 may have a single-layer structure or a multi-layer structure, and is not particularly limited herein.

A photoresist layer 240 may be formed on the masking material layer 230 by spin coating or other methods, and the photoresist layer 240 may be exposed by using a mask plate, the pattern of which may match the pattern required by the opening on the support layer farthest from the substrate 1, and the orthographic projection of the opening on the substrate 1 may cover the region between two adjacent capacitor holes 220, and may at least partially coincide with the orthographic projection of two adjacent capacitor holes 220 on the substrate 1. The exposed photoresist layer 240 may then be developed to form developed regions, which may expose the masking material layer 230. The layer of masking material 230 and the support layer furthest from the substrate 1 are etched in the development zone to form openings that expose the sacrificial layer adjacent to the support layer furthest from the substrate 1.

After the opening etching is completed, the photoresist layer 240 may be subjected to ashing treatment to remove the photoresist layer 240, and the mask material layer 230 is removed by a dry etching process, so that the mask material layer 230 no longer covers the capacitor hole 220 and the support layer farthest from the substrate 1, and the finally formed structure is as shown in fig. 11.

The sacrificial layer (i.e., the second sacrificial layer 23) adjacent to the support layer farthest from the substrate 1 may be removed by a wet etching process. For example, wet etching may be performed using an acidic solution to remove the material of the second sacrificial layer 23. The first support layer 22 partially underlying the second sacrificial layer 23 may be removed by a dry etching process to expose the first sacrificial layer 21 underlying the first support layer 22, and then the material of the first sacrificial layer 21 may be removed by a wet etching process. At this time, the support layer located in the middle of the first electrode layer 25 can laterally support the middle of the first electrode layer 25, and the support layer farthest from the substrate 1 can laterally support the end of the first electrode layer 25 away from the substrate 1, so as to avoid short circuit between the columnar capacitors, as shown in fig. 12 after step S240 is completed.

Step S250, forming a dielectric layer on an outer surface and an inner surface of a structure formed by the first electrode layer and the support layer.

The dielectric layer 26 may be a thin film formed on the outer surface and the inner surface of the structure formed by the first electrode layer 25 and the support layer, and the dielectric layer 26 may be formed by a process such as vacuum evaporation or magnetron sputtering, of course, the dielectric layer 26 may be formed by other processes, which are not listed here. The dielectric layer 26 may comprise a material having a relatively high dielectric constant, such as aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, or mixtures thereof, but other materials may be used, and are not listed here.

Step S260, forming a second electrode layer on the surface of the dielectric layer.

The second electrode layer 27 may be formed on the surface of the dielectric layer 26 by a chemical vapor deposition process, but the second electrode layer 27 may also be formed by other processes, which are not limited herein. The material of the second electrode layer 27 may be titanium nitride.

As shown in fig. 6, the first electrode layer 25, the support layer, the dielectric layer 26, and the second electrode layer 27 formed as described above collectively constitute the capacitor array 2 of the present disclosure.

As shown in fig. 5, in step S120, a reference semiconductor layer covering the open region is formed.

As shown in fig. 13, the reference semiconductor layer 3 may be formed in the open region of the substrate 1 by vacuum evaporation, magnetron sputtering, chemical vapor deposition or atomic layer deposition, and in this process, the reference semiconductor layer 3 may cover the array region and the peripheral region at the same time, and may fill the gaps between the columnar capacitors in the array region.

In one embodiment, the reference semiconductor layer 3 may completely cover the protrusions 210 at the edge of the capacitor array 2, so as to avoid air gaps due to uneven edges of the array region when an insulating layer is formed later; meanwhile, in order to ensure that the reference semiconductor layer 3 completely fills the concave-convex structure induced by the protrusion 210, the reference semiconductor layer 3 may extend to the open region, and in an embodiment, a boundary of the reference semiconductor layer 3 away from the array region and an edge of the array region may have a first distance, which may be greater than or equal to 400nm, in a direction parallel to the substrate 1.

The reference semiconductor layer 3 may be made of a conductor or a semiconductor material, for example, it may be a silicon material, a metal material or a metal compound, etc., for example, it may be silicon, silicon germanium, tungsten, titanium silicide, titanium oxide or tungsten oxide, etc., and is not limited herein.

As shown in fig. 5, in step S130, a first etching process is performed on the reference semiconductor layer to reduce a distance between a boundary of the reference semiconductor layer and an edge of the array region.

The reference semiconductor layer 3 in the peripheral region and the open region may be subjected to a first etching process such that a boundary of the reference semiconductor layer 3 after the first etching process has a second distance from an edge of the array region, the second distance being smaller than the first distance, for example, the second distance may be 100 nm.

In the manufacturing process of products, due to the influence of an etching process, the etching rate of the film close to the middle area of the substrate 1 is usually greater than that of the film close to the edge area in the process of etching the film, in order to ensure that the film close to the middle area of the substrate 1 and the film close to the edge area can be etched to the surface of the substrate 1 at the same time, the reference semiconductor layer 3 located in the peripheral area can be etched back by adopting a first etching treatment before the reference semiconductor layer 3 is integrally etched, the reference semiconductor layer 3 still remains in the peripheral area after etching back, and the surface of the residual reference semiconductor layer 3 in the peripheral area is lower than that of the reference semiconductor layer 3 in the open area.

In an exemplary embodiment of the disclosure, the first etching process includes a wet etching process, for example, the reference semiconductor layer 3 in the peripheral region may be wet etched to reduce the thickness of the reference semiconductor layer 3 in the peripheral region, so as to ensure that the reference semiconductor layer 3 in the peripheral region and the reference semiconductor layer 3 in the open region can be simultaneously etched to the surface of the substrate 1 in the subsequent etching process, thereby exposing the conductive contact plug 11 on the surface of the substrate 1, ensuring that the interconnection structure formed in the subsequent region can be in contact connection with the conductive contact plug 11, thereby avoiding short circuit of the interconnection structure, and the structure after step S130 is completed is as shown in fig. 14.

For example, wet etching may be performed using an acidic solution, which may be a mixed solution of hydrofluoric acid and nitric acid.

As shown in fig. 5, in step S140, a second etching process is performed on the reference semiconductor layer to form a target semiconductor layer having a flat surface in a direction perpendicular to the substrate.

The reference semiconductor layer 3 may be subjected to a second etching process to completely remove the reference semiconductor layer 3 on the surface of the peripheral region, so as to form a target semiconductor layer 4, where the target semiconductor layer 4 has a flat surface in a direction perpendicular to the substrate 1, and a boundary of the target semiconductor layer 4 away from the array region has a target distance from an edge of the array region. It should be noted that the height of the protrusion 210 at the edge portion of the capacitor array 2 is not greater than the target distance, the target semiconductor layer 4 can completely cover the protrusion 210, and the structure after the step S140 is completed is as shown in fig. 15.

In an exemplary embodiment of the present disclosure, the second etching process includes a dry etching process, and the second etching process is performed on the reference semiconductor layer 3 to form a target semiconductor layer 4, and the target semiconductor layer 4 has a flat surface in a direction perpendicular to the substrate 1, that is: step S140 may include step S1410 and step S1420, wherein:

step 1410, a photolithography process is performed on the array region to form a mask pattern, and the target distance is defined by the mask pattern.

The photoresist layer 240 may be formed on the surface of the reference semiconductor layer 3 away from the substrate 1 by spin coating, or chemical vapor deposition, and the photoresist layer 240 may be exposed and developed to form a mask pattern. The mask pattern may expose at least the reference semiconductor layer 3 in the peripheral region, and of course, the mask pattern may also expose a portion of the open region adjacent to the peripheral region, which is not particularly limited herein.

For example, the orthographic projection of the photoresist layer 240 on the substrate 1 can at least cover the orthographic projection of the capacitor array 2 on the substrate 1. For example, in a direction perpendicular to the substrate 1, the end of the photoresist layer 240 may be aligned with at least the boundary of the capacitor array 2, and may also extend from the array region into the open region. Note that the photoresist layer 240 does not extend to be located in the peripheral region, i.e.: the orthographic projection of the photoresist layer 240 on the substrate 1 does not overlap with the conductive contact plug 11 located in the peripheral region, and the structure after the step S1410 is completed is as shown in fig. 16.

Step S1420, using the mask pattern as a mask, performs the second etching process.

And taking the substrate 1 as an etching stop layer, and carrying out anisotropic etching on the region which is not covered by the photoresist layer 240 by adopting a dry etching process and taking the mask pattern as a mask to remove the reference semiconductor layer 3 which is covered outside the array region so as to form a target semiconductor layer 4, wherein in the process, the reference semiconductor layer 3 in the peripheral region can be completely removed so as to expose the conductive contact plug 11 in the peripheral region.

As shown in fig. 5, in step S150, an insulating layer covering the peripheral region and the target semiconductor layer is formed.

An insulating layer 5 may be formed on the peripheral region and the surface of the target semiconductor layer 4 by using an atomic layer deposition or chemical vapor deposition process, and the capacitor array 2 may be separated from other structures by the insulating layer 5, thereby preventing short circuits between the structures. Meanwhile, in this process, since the edge portion of the target semiconductor layer 4 has a flat structure, an air gap is not generated at the edge portion of the array region when the insulating layer 5 is formed, and the structure after the completion of step S150 is as shown in fig. 17.

In an exemplary embodiment of the present disclosure, the insulating layer 5 covering the peripheral region and the target semiconductor layer 4 is formed, that is: step S150 may include step S1510 and step S1520, as shown in fig. 18, wherein:

in step S1510, an insulating material layer is formed on the surface of the target semiconductor layer and the peripheral region.

An insulating material layer may be formed on the surface of the target semiconductor layer 4 away from the substrate 1 and the surface of the region of the substrate 1 not covered by the target semiconductor layer 4 by vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or atomic layer deposition, and the insulating material layer may be made of an insulating material, for example, silicon dioxide, but the material of the insulating material layer may also be other insulating materials, which is not limited herein.

Step S1520, a planarization process is performed on the surface of the insulating material layer.

The surface of the insulating-material layer facing away from the substrate 1 may be planarized so that the insulating-material layer at the surface of the target semiconductor layer 4 is flush with the insulating-material layer at the surface of the peripheral region of the substrate 1, thereby forming the insulating layer 5.

In an exemplary embodiment of the present disclosure, the forming method of the present disclosure may further include step S160 and step S170, as shown in fig. 19, wherein:

step S160, forming a first interconnection structure in the peripheral region, where the first interconnection structure is formed in the insulating layer and is in contact connection with the conductive contact plug.

As shown in fig. 20, a first interconnection structure 501 may be formed in the insulating layer 5 on the surface of the peripheral region, and may be in contact connection with the conductive contact plug 11 of the peripheral region, so as to electrically lead out the capacitor array 2. The material of the first interconnect structure 501 may be a conductive material, for example, the material thereof may be titanium nitride or tungsten.

Step S170, forming a second interconnection structure in the insulating layer on the surface of the target semiconductor layer, the second interconnection structure being in communication with the target semiconductor layer.

The second interconnection structure 502 may be formed in the insulating layer 5 on the surface of the target semiconductor layer 4, and may be connected in contact with the target semiconductor layer 4. The second interconnect structures 502 may be plural, and the plural second interconnect structures 502 may be spaced apart and may be respectively connected in contact with the target semiconductor layer 4. The material of the second interconnect structure 502 may be a conductive material, for example, the material thereof may be titanium nitride or tungsten.

In an exemplary embodiment of the present disclosure, forming the first interconnect structure 501 and the second interconnect structure 502 may include steps S310 to S340, as shown in fig. 21, wherein:

step S310, etching the insulating layer by using the conductive contact plug of the peripheral region as an etching stop layer to form a first via hole.

As shown in fig. 22, the insulating layer 5 in the peripheral region may be etched by a photolithography process to form a first via hole 51 in the insulating layer 5, and the first via hole 51 may be disposed opposite to the conductive contact plug 11 in the peripheral region, may be a through hole, and may expose the conductive contact plug 11 in the peripheral region.

Step S320, a first interconnection structure is formed in the first via hole.

The first interconnect structure 501 may be formed in the first via hole 51 by a chemical vapor deposition process, and the first interconnect structure 501 may communicate with the conductive contact plug 11 of the peripheral region through the first via hole 51, so as to electrically lead out the capacitor array 2.

The first interconnect structure 501 may include a connection layer and a lead-out layer, the connection layer may be attached to the hole wall and the bottom surface of the first via hole 51 in a conformal manner and may be communicated with the conductive contact plug 11 in the peripheral region, and the lead-out layer may be located on the connection layer and may fill up the first via hole 51. The material of the connection layer and the extraction layer can be conductive materials, for example, the material of the connection layer can be titanium nitride, and the material of the extraction layer can be tungsten.

Step S330, etching the insulating layer on the surface of the target semiconductor layer by using the target semiconductor layer as an etching stop layer to form a second via hole.

The insulating layer 5 on the surface of the target semiconductor layer 4 is etched by a photolithography process using the target semiconductor layer 4 as an etch stop layer to form a second via 52 in the insulating layer 5, and the second via 52 may be a through hole and may be in contact with the surface of the target semiconductor layer 4.

Step S340, forming a second interconnect structure in the second via hole.

The second interconnect structure 502 may be the same as the first interconnect structure 501 in structure and material, for example, the second interconnect structure 502 may also include a connection layer and a lead-out layer, the connection layer may be attached to the hole wall and the bottom surface of the second via 52 in a conformal manner and may be in contact with the target semiconductor layer 4, and the lead-out layer may fill the second via 52.

The embodiment of the disclosure also provides a semiconductor structure, which can be formed by the method for forming the semiconductor structure of any one of the above embodiments.

The specific details, the forming process and the beneficial effects of each part in the semiconductor structure are described in detail in the corresponding forming method of the semiconductor structure, and therefore, the details are not repeated herein.

For example, the semiconductor structure may be a Dynamic Random Access Memory (DRAM), and of course, other Memory devices may be used, which are not listed here.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims (15)

1. A method of forming a semiconductor structure, comprising:

providing a substrate comprising an array region and an open area surrounding the array region;

forming a reference semiconductor layer covering the open region;

performing a first etching process on the reference semiconductor layer to reduce a distance between a boundary of the reference semiconductor layer and an edge of the array region;

and carrying out second etching treatment on the reference semiconductor layer to form a target semiconductor layer, wherein the target semiconductor layer has a flat surface in a direction vertical to the substrate.

2. The method of claim 1, wherein a boundary of the reference semiconductor layer away from the array region has a first distance from an edge of the array region in a direction parallel to the substrate; after the first etching treatment is carried out on the reference semiconductor layer, the boundary of the reference semiconductor layer has a second distance with the edge of the array region; the boundary of the target semiconductor layer far away from the array region and the edge of the array region have a target distance, and the difference between the second distance and the target distance is smaller than the difference between the first distance and the second distance.

3. The method as claimed in claim 2, wherein the array region is formed with a capacitor array, the capacitor array has an outer edge with irregular profile in a direction perpendicular to the substrate, and the outer edge with irregular profile has at least one protrusion in a direction parallel to the substrate, the height of the protrusion is not greater than the target distance, and the target semiconductor layer can completely cover the protrusion.

4. The method of claim 1, wherein the first etching process comprises a wet etching process and the second etching process comprises a dry etching process.

5. The method according to claim 2, wherein the reference semiconductor layer is subjected to a second etching process to form a target semiconductor layer having a flat surface in a direction perpendicular to the substrate:

performing a photoetching process on the array region to form a mask pattern, and defining the target distance by using the mask pattern;

and performing the second etching treatment by taking the mask pattern as a mask.

6. The method as claimed in claim 1, wherein the array region is disposed adjacent to the open region, and the target semiconductor layer covers both the array region and the open region.

7. The method as claimed in claim 6, wherein the substrate further comprises a peripheral region, the open region is located between the peripheral region and the array region, and the reference semiconductor layer is formed in the peripheral region simultaneously when the reference semiconductor layer covering the open region is formed.

8. The method as claimed in claim 7, wherein after the first etching process is performed on the reference semiconductor layer, the reference semiconductor layer remains in the peripheral region, and a surface of the reference semiconductor layer remaining in the peripheral region is lower than a surface of the reference semiconductor layer in the open region.

9. The method as claimed in claim 8, wherein the reference semiconductor layer in the peripheral region is completely removed after the second etching process is performed on the reference semiconductor layer.

10. The method as claimed in claim 3, wherein the array region comprises a plurality of capacitor plugs arranged at intervals, and the forming the capacitor array on the array region comprises:

forming a sacrificial layer and a supporting layer which are sequentially distributed in an overlapped mode on the surface of the array area;

etching the sacrificial layer and the support layer by taking the substrate as an etching stop layer so as to form a plurality of capacitor holes which are distributed at intervals in the sacrificial layer and the support layer, wherein each capacitor hole is communicated with each capacitor plug in a one-to-one correspondence manner;

forming a first electrode layer in the capacitor hole, wherein the first electrode layer is in contact connection with the capacitor plug;

removing each sacrificial layer;

forming a dielectric layer on the outer surface and the inner surface of a structure formed by the first electrode layer and the support layer;

and forming a second electrode layer on the surface of the dielectric layer.

11. The method of claim 7, further comprising:

an insulating layer is formed overlying the peripheral region and the target semiconductor layer.

12. The method of claim 11, wherein the peripheral region comprises a conductive contact plug, the method further comprising:

and forming a first interconnection structure in the peripheral region, wherein the first interconnection structure is formed in the insulating layer and is in contact connection with the conductive contact plug.

13. The method of forming as claimed in claim 12, further comprising:

and forming a second interconnection structure in the insulating layer on the surface of the target semiconductor layer, wherein the second interconnection structure is communicated with the target semiconductor layer.

14. The method of forming of claim 13, wherein forming the first interconnect structure and the second interconnect structure comprises:

etching the insulating layer by using the conductive contact plug of the peripheral area as an etching stop layer to form a first via hole;

forming a first interconnect structure in the first via;

etching the insulating layer on the surface of the target semiconductor layer by taking the target semiconductor layer as an etching stop layer to form a second through hole;

and forming a second interconnection structure in the second via hole.

15. A semiconductor structure formed by the method of forming a semiconductor structure of any of claims 1-14.

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