CN113157143B

CN113157143B - Display panel and display device

Info

Publication number: CN113157143B
Application number: CN202110576674.6A
Authority: CN
Inventors: 何帆; 张顺
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-05-26
Filing date: 2021-05-26
Publication date: 2024-04-23
Anticipated expiration: 2041-05-26
Also published as: CN113157143A

Abstract

The disclosure provides a display panel and a display device, and belongs to the technical field of display. The display panel comprises a substrate, a driving circuit layer, a pixel layer and a touch control functional layer which are sequentially stacked; the touch functional layer comprises a touch wiring layer; in the peripheral area of the display panel, the touch wiring layer is provided with two reference voltage wires and a plurality of touch wires; each touch control wire is arranged between two reference voltage wires; the area of any one of the reference voltage wires is larger than that of any one of the touch wires. The display panel provided by the disclosure can reduce the probability of touch failure.

Description

Display panel and display device

Technical Field

The disclosure relates to the technical field of display, in particular to a display panel and a display device.

Background

In FMLOC (Flexible Multi-Layer On Cell) products, a touch functional Layer can be directly prepared On the surface of the display back plate, so that the thickness of the touch display panel is reduced. In FMLOC products, the touch signal wiring and the wiring of the display backboard are both connected to the binding area; this results in the touch signal traces being susceptible to crosstalk from the signals of the display backplane, increasing the probability of touch failure.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The disclosure aims to overcome the defects of the prior art, and provide a display panel and a display device, which reduce the probability of touch failure.

According to one aspect of the present disclosure, there is provided a display panel including a substrate base plate, a driving circuit layer, a pixel layer, and a touch function layer, which are sequentially stacked;

The touch functional layer comprises a touch wiring layer; in the peripheral area of the display panel, the touch wiring layer is provided with two reference voltage wires and a plurality of touch wires; each touch control wire is arranged between two reference voltage wires;

The area of any one of the reference voltage wires is larger than that of any one of the touch wires.

According to one embodiment of the disclosure, the reference voltage trace has a width that is greater than a width of the touch trace.

According to one embodiment of the present disclosure, the peripheral zone includes a binding zone; in the binding area, the display panel is provided with a plurality of binding sub-bonding pads;

The width of the reference voltage wiring is not smaller than the width of the binding sub-bonding pad;

the width of the touch control wiring is smaller than the width of the binding sub-bonding pad.

According to one embodiment of the present disclosure, the reference voltage trace includes a main reference voltage sub-trace and at least one auxiliary reference voltage sub-trace disposed side-by-side with the main reference voltage sub-trace; both ends of any one auxiliary reference voltage sub-wiring are connected to the main reference voltage sub-wiring.

According to one embodiment of the present disclosure, the main reference voltage sub-trace and the auxiliary reference voltage sub-trace have the same width and are both equal to the width of the touch trace.

According to one embodiment of the disclosure, in the peripheral area of the display panel, the touch wiring layer is further provided with two shielding wirings; each touch control wire is positioned between two shielding wires, and any one shielding wire is positioned between the reference voltage wire and the touch control wire;

The area of any one shielding wire is larger than that of any one touch wire.

According to one embodiment of the disclosure, the width of the shielding wire is greater than the width of the touch wire.

the width of the shielding wire is equal to the width of the binding sub-bonding pad.

According to one embodiment of the present disclosure, the pixel layer is provided with a common electrode; the driving circuit layer is provided with a second power bus in the peripheral area of the display panel; the second power bus is used for loading a second power voltage to the common electrode;

The peripheral zone includes a binding zone; the display panel is provided with a plurality of binding pads which are arranged in a straight line in the binding area;

The binding pads comprise a plurality of touch binding pads which are connected with the touch wiring in a one-to-one correspondence manner, two reference voltage pads which are connected with the two reference voltage wirings in a one-to-one correspondence manner, and a second power supply pad which is connected with the second power supply bus;

the distance between the reference voltage bonding pad and the second power supply bonding pad is larger than the distance between two adjacent touch bonding pads.

According to one embodiment of the disclosure, in the binding area, the display panel is provided with a plurality of binding sub-pads arranged in a straight line at equal intervals; any one of the bond pads includes at least one of the bond sub-pads;

The binding sub-pad having a floating connection between the reference voltage pad and the second power supply pad.

According to another aspect of the present disclosure, there is provided a display device including the above display panel.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the disclosure.

Fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the disclosure.

Fig. 3 is a schematic partial structure of a touch electrode layer according to an embodiment of the disclosure.

Fig. 4 is a schematic cross-sectional structure diagram of the touch functional layer at the P1P2 position of fig. 3.

Fig. 5 is a schematic view of a partial structure of a peripheral region in an embodiment of the present disclosure.

Fig. 6 is a schematic diagram of a partial structure of a touch wiring layer and a source drain metal layer near an outer bending region in an embodiment of the disclosure.

Fig. 7 is a schematic diagram of a partial structure of a touch wiring layer near a binding area in an embodiment of the disclosure.

Fig. 8 is a schematic diagram of a partial structure of a touch wiring layer and a source drain metal layer near a bonding area in an embodiment of the disclosure.

Fig. 9 is a schematic view of a partial structure of a source-drain metal layer near a bonding area in an embodiment of the disclosure.

Fig. 10 is a schematic view of a partial structure of a touch wiring layer near a binding area in an embodiment of the disclosure.

Fig. 11 is a schematic diagram of a partial structure of a touch wiring layer and a source drain metal layer near a bonding area in an embodiment of the disclosure.

Fig. 12 is a schematic view of a partial structure of a source-drain metal layer near a bonding area in an embodiment of the disclosure.

Fig. 13 is a schematic view of a partial structure of a touch wiring layer near a binding area in an embodiment of the disclosure.

Reference numerals illustrate:

AA. A display area; BB. A peripheral region; b1, binding area; b2, a peripheral bending area; C. binding the bonding pad; c01, binding the sub-bonding pad; c02, auxiliary bonding pads; c03, floating binding sub-bonding pads; l1, touch wiring; l2, a reference voltage wiring; l21, main reference voltage sub-wiring; l22, auxiliary reference voltage sub-wiring; l3, shielding wiring; l4, bridging wiring; LVDD, first power bus; LVSS, second power bus; h1, row direction; h2, column direction; f100, a substrate base plate; f200, driving circuit layer; f200M, transistors; f201, barrier layer; f202, a buffer layer; f203, a semiconductor layer; f204 gate insulating layer; f205 gate layer; f206, interlayer dielectric layer; f207, source drain metal layer; f208, planarizing layer; f300, a pixel layer; f301, pixel electrode layer; f302, a pixel definition layer; f303, a support column layer; f304, organic light emitting functional layer; f305 common electrode layer; f400, a film packaging layer; f401, a first inorganic encapsulation layer; f402, an organic packaging layer; f403, a second inorganic packaging layer; f500, a reflection reducing layer; f600, a touch functional layer; f501, a touch wiring layer; f502, a touch insulating layer; f503, a touch electrode layer; f510, a touch electrode; f511, row touch electrodes; f5111, arranging the touch sub-electrodes; f512, row touch electrodes; f5121, a row touch sub-electrode; f5131, bridging connection.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

The terms "a," "an," "the," and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first" and "second" and the like are used merely as labels, and are not intended to limit the number of their objects.

The present disclosure provides a display panel and a display device based on the display panel. Referring to fig. 1, the display panel PNL includes a display area AA and a peripheral area BB surrounding the display area AA from a top view. On one side of the display area AA, the peripheral area BB has a binding area B1. Referring to fig. 8, the display panel is provided with a plurality of bonding pads C within the bonding region B1 so that an external circuit is bonded to the display panel through the bonding pads C. The external circuit may be a Chip On Film (COF), a flexible circuit board, or other type of circuit structure.

In some embodiments of the present disclosure, within the bonding region B1, the respective bonding pads C may be aligned along a first direction. In this way, alignment and binding between the external circuit and the binding pad C is facilitated. The binding pads C may be rectangular or parallelogram in shape as a whole. For example, referring to fig. 8, the bond pad C is generally parallelogram-shaped, including two first edges disposed opposite and extending in a first direction, and including two second edges disposed opposite and extending in a second direction. The first edges of the same ends of the binding pads C are located on the same line, or may not be located on the same line.

Alternatively, the width between any two bond pads C may be the same or different. In the present disclosure, the width of the bonding pad C refers to the dimension of the bonding pad C in the first direction.

Optionally, any binding pad C may be an integral plate-shaped pad, or may be a hollowed-out pad with a slit. For example, referring to fig. 8, at least one bonding pad C may be a hollowed-out pad, where the hollowed-out pad includes a plurality of bonding sub-pads C01 disposed in parallel and sequentially adjacent to each other along the first direction, and the bonding sub-pads C01 are connected to the same wire and further serve as the bonding pads C connected to the wire.

In one embodiment of the present disclosure, the display panel may include a plurality of binding sub-pads C01 within the binding region B1. The binding sub-pads C01 may be aligned in a straight line along the first direction and disposed at equal intervals, and the widths of the respective binding sub-pads C01 are the same. The binding pad C of the present disclosure may include one binding sub-pad C01, or include a plurality of binding sub-pads C01 disposed adjacently. For example, one wire is connected to one bonding sub-pad C01, and then the bonding sub-pad C01 serves as the bonding pad C connected to the wire. For another example, one trace may be connected to an adjacent plurality of bond pads C01, and the plurality of bond pads C01 may form the bond pad C of the trace. Optionally, the binding sub-pad C01 is parallelogram-shaped, comprising two first edges arranged opposite and extending in a first direction, and comprising two second edges arranged opposite and extending in a second direction.

Referring to fig. 2, the display panel includes a substrate F100, a driving circuit layer F200, a pixel layer F300, and a touch functional layer F500, which are sequentially stacked from the perspective of a film layer.

In the present disclosure, the substrate F100 may be an inorganic substrate F100 or an organic substrate F100. For example, in one embodiment of the present disclosure, the material of the substrate base plate F100 may be a glass material such as soda lime glass (soda-LIME GLASS), quartz glass, sapphire glass, or a metal material such as stainless steel, aluminum, nickel, or the like. In another embodiment of the present disclosure, the material of the substrate F100 may be polymethyl methacrylate (Polymethyl methacrylate, PMMA), polyvinyl alcohol (Polyvinyl alcohol, PVA), polyvinyl phenol (Polyvinyl phenol, PVP), polyethersulfone (Polyether sulfone, PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (Polyethylene terephthalate, PET), polyethylene naphthalate (Polyethylene naphthalate, PEN), or a combination thereof. In another embodiment of the present disclosure, the substrate F100 may also be a flexible substrate F100, for example, the material of the substrate F100 may be Polyimide (PI). The substrate F100 may also be a composite of multiple layers of materials, for example, in one embodiment of the present disclosure, the substrate F100 may include a base Film layer (Bottom Film), a pressure sensitive adhesive layer, a first polyimide layer, and a second polyimide layer, which are sequentially stacked.

It is understood that when the substrate of the present disclosure is a flexible substrate, the display panel of the present disclosure may be a flexible display panel.

Alternatively, in the driving circuit layer F200, any one of the pixel driving circuits may include a transistor F200M and a storage capacitor. Further, the transistor F200M may be a thin film transistor, which may be a top gate thin film transistor, a bottom gate thin film transistor, or a double gate thin film transistor; the material of the active layer of the thin film transistor may be an amorphous silicon semiconductor material, a low temperature polysilicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material or other types of semiconductor materials; the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor. In one embodiment of the present disclosure, the thin film transistor is a low temperature polysilicon transistor.

It will be appreciated that the type between any two transistors in the individual transistors in the pixel drive circuit may be the same or different. Illustratively, in one embodiment, in one pixel driving circuit, a portion of the transistors may be N-type transistors and a portion of the transistors may be P-type transistors. Still further illustratively, in another embodiment of the present disclosure, in one pixel driving circuit, the material of the active layer of the partial transistor may be a low temperature polysilicon semiconductor material, and the material of the active layer of the partial transistor may be a metal oxide semiconductor material.

Alternatively, the driving circuit layer F200 may include a semiconductor layer F203, a gate insulating layer F204, a gate layer F205, an interlayer dielectric layer F206, a source drain metal layer F207, and the like stacked between the substrate F100 and the pixel layer F300. Each of the thin film transistors and the storage capacitor may be formed of a film layer such as the semiconductor layer F203, the gate insulating layer F204, the gate layer F205, the interlayer dielectric layer F206, the source/drain metal layer F207, or the like. The positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor. For example, in one embodiment of the present disclosure, the driving circuit layer F200 may include a semiconductor layer F203, a gate insulating layer F204, a gate layer F205, an interlayer dielectric layer F206, and a source-drain metal layer F207, which are sequentially stacked, so that the thin film transistor formed is a top gate thin film transistor. For another example, in another embodiment of the present disclosure, the driving circuit layer F200 may include a gate layer F205, a gate insulating layer F204, a semiconductor layer F203, an interlayer dielectric layer F206, and a source drain metal layer F207, which are sequentially stacked, so that the thin film transistor formed is a bottom gate thin film transistor. The driving circuit layer F200 may also adopt a dual gate layer F205 structure, i.e., the gate layer F205 may include a first gate layer and a second gate layer, and the gate insulating layer F204 may include a first gate insulating layer for isolating the semiconductor layer F203 from the first gate layer, and a second gate insulating layer for isolating the first gate layer from the second gate layer. For example, in one embodiment of the present disclosure, the driving circuit layer F200 may include a semiconductor layer F203, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer F206, and a source drain metal layer F207, which are sequentially stacked on one side of the substrate F100.

Alternatively, the driving circuit layer may also be provided with different tracks in order to load the required driving signals to the pixel driving circuits. For example, a data wire for applying a data voltage to the pixel driving circuit, a first power wire for applying a first power voltage to the pixel driving circuit, a scan wire for applying a scan signal to the pixel driving circuit, and the like may be provided in the driving circuit layer. In some embodiments, referring to fig. 5, the driving circuit layer may further be provided with a first power bus LVDD in the peripheral region, and the first power bus LVDD may be connected to and load a first power voltage to each first power trace.

Optionally, the driving circuit layer F200 may further include a passivation layer, where the passivation layer may be disposed on a surface of the source drain metal layer F207 remote from the substrate F100, so as to protect the source drain metal layer F207.

Alternatively, the driving circuit layer F200 may further include a buffer material layer disposed between the substrate F100 and the semiconductor layer F203, the gate layer F205, and the like are located on a side of the buffer material layer away from the substrate F100. The material of the buffer material layer may be an inorganic insulating material such as silicon oxide or silicon nitride. The buffer material layer may be one inorganic material layer or a plurality of inorganic material layers stacked. Illustratively, in one embodiment of the present disclosure, referring to fig. 3, the buffer material layer may include a barrier layer F201 on a side of the substrate F100 and a buffer layer F202 on a side of the barrier layer F201 away from the substrate F100. The barrier layer F201 is used to block permeation of components such as ions in the substrate base plate F100 to the driving circuit layer F200, so that the driving circuit layer F200 maintains stable performance. The buffer layer F202 may improve the coupling force between the driving circuit layer F200 and the substrate F100 and provide a stable environment for the driving circuit layer F200.

Optionally, the driving circuit layer F200 may further include a planarization layer F208 between the source drain metal layer F207 and the pixel layer F300, and the planarization layer F208 may provide a planarized surface for the pixel electrode. Alternatively, the material of the planarization layer F208 may be an organic material.

The pixel layer F300 may be provided with a light emitting element corresponding to the pixel driving circuit and electrically connected thereto, and the light emitting element may serve as a sub-pixel of the display panel. In this way, the pixel layer is provided with light emitting elements distributed in an array, and each light emitting element emits light under the control of the pixel driving circuit. In the present disclosure, the light emitting element may be an Organic Light Emitting Diode (OLED), a Micro light emitting diode (Micro LED), a quantum dot-organic light emitting diode (QD-OLED), or other type of light emitting element. Illustratively, in one embodiment of the present disclosure, the light emitting element is an Organic Light Emitting Diode (OLED), and the display panel is an OLED display panel. As follows, an example of a possible structure of the pixel layer is described using the light emitting element as an organic electroluminescent diode.

Referring to fig. 2, in the exemplary OLED display panel, a pixel layer may be disposed at a side of the driving circuit layer F200 remote from the substrate F100, and may include a pixel electrode layer F301, a pixel defining layer F302, a support column layer F303, an organic light emitting functional layer F304, and a common electrode layer F305, which are sequentially stacked. The pixel electrode layer F301 has a plurality of pixel electrodes in the display area AA of the display panel; the pixel defining layer F302 has a plurality of through pixel openings in the display area AA, each through pixel opening being disposed in one-to-one correspondence with a plurality of pixel electrodes, and any one of the pixel openings exposes at least a portion of the corresponding pixel electrode. The support pillar layer F303 includes a plurality of support pillars in the display area AA, and the support pillars are located on a surface of the pixel defining layer F302 away from the substrate F100, so as to support the fine metal mask (FINE METAL MASK, FMM) during the evaporation process. The organic light emitting functional layer F304 covers at least the pixel electrode exposed by the pixel defining layer F302. The organic light emitting functional layer F304 may include an organic electroluminescent material layer, and may include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. Each film layer of the organic light emitting functional layer F304 may be prepared by an evaporation process, and a fine metal Mask or an Open Mask (Open Mask) may be used to define a pattern of each film layer during evaporation. The common electrode layer F305 may cover the organic light emitting functional layer F304 in the display area AA. In this way, the pixel electrode, the common electrode layer F305, and the organic light emitting functional layer F304 located between the pixel electrode and the common electrode layer F305 form the organic light emitting diode F300D, and any one of the organic light emitting diodes may serve as one sub-pixel of the display panel.

Alternatively, the common electrode layer is provided with a common electrode connected to each light emitting element, multiplexed as an electrode of each light emitting element. In this way, the second power supply voltage can be applied to the common electrode, and the second power supply voltage is applied to each light emitting element. In some embodiments of the present disclosure, the driving circuit layer may be provided with a second power bus line LVSS at the peripheral region BB, the second power bus line LVSS being electrically connected to the common electrode. As such, the second power supply bus LVSS may apply a second power supply voltage to the common electrode.

In some embodiments, referring to fig. 2, the pixel layer F300 may further include a light extraction layer on a side of the common electrode layer F305 remote from the substrate F100 to enhance the light extraction efficiency of the organic light emitting diode.

It will be appreciated that the above exemplary description of the pixel layer is only one possible example, and that the pixel layer of the OLED display panel may have other structures. When the type of the light emitting element in the pixel layer is changed, the structure of the pixel layer of the display panel may also be changed.

In some embodiments, referring to fig. 2, the display panel may further include a thin film encapsulation layer F400. The thin film encapsulation layer F400 is disposed on a surface of the pixel layer F300 remote from the substrate F100, and may include an inorganic encapsulation layer and an organic encapsulation layer alternately stacked. The inorganic packaging layer can effectively block external moisture and oxygen, and material degradation caused by invasion of the moisture and the oxygen into the organic light-emitting functional layer F304 is avoided. Alternatively, the edges of the inorganic encapsulation layer may be located in the peripheral region BB. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers in order to achieve planarization and to attenuate stresses between the inorganic encapsulation layers. Wherein, the edge of the organic encapsulation layer may be located between the edge of the display area AA and the edge of the inorganic encapsulation layer. Illustratively, the thin film encapsulation layer F400 includes a first inorganic encapsulation layer F401, an organic encapsulation layer F402, and a second inorganic encapsulation layer F403 sequentially stacked on a side of the pixel layer F300 remote from the substrate F100.

In some embodiments, the touch functional layer F500 may be disposed on a side of the thin film encapsulation layer F400 away from the substrate F100, for implementing a touch operation of the display panel.

In some embodiments, the display panel may further include a reflection reducing layer F600, where the reflection reducing layer F600 may be disposed on a side of the thin film encapsulation layer F400 away from the pixel layer F300, for reducing reflection of ambient light by the display panel, and further reducing an influence of the ambient light on a display effect. In one embodiment of the present disclosure, the reflection reducing layer F600 may include a color film layer and a black matrix layer that are stacked, so that the light transmittance of the display panel may be prevented from being reduced while the ambient light interference is reduced. In another embodiment of the present disclosure, the anti-reflection layer F600 may be a polarizer, for example, may be a patterned coated circular polarizer. Further, the anti-reflection layer F600 may be disposed on a side of the touch functional layer F500 away from the substrate F100.

In the display panel of the present disclosure, referring to fig. 4, the touch functional layer may include a touch wiring layer F501, a touch insulating layer F502, and a touch electrode layer F503, which are sequentially stacked. The touch electrode layer F503 is located on a side of the touch wiring layer F501 away from the substrate. One or two layers of the touch wiring layer and the touch electrode layer are used for forming the touch electrode. In one embodiment of the present disclosure, referring to fig. 2, the touch functional layer F500 is disposed on a side of the thin film encapsulation layer F400 away from the substrate.

Optionally, a touch buffer layer may be further included between the touch wiring layer and the thin film encapsulation layer F400. The material of the touch buffer layer may be an inorganic material, for example, silicon nitride, silicon oxide, or silicon oxynitride. It is understood that in other embodiments of the present disclosure, the outermost inorganic encapsulation layer of the thin film encapsulation layer F400 may also be multiplexed as a touch buffer layer.

Optionally, a touch protection layer may be further included on a side of the touch electrode layer away from the substrate F100. The material of the touch protection layer may be an inorganic material, for example, silicon nitride, silicon oxide, or silicon oxynitride. It is understood that in other embodiments of the present disclosure, the side of the touch electrode layer away from the substrate F100 may also be directly provided with an organic layer, for example, an organic cover plate or an optical adhesive.

Alternatively, the touch wiring layer and the touch electrode layer may be light-transmitting film layers, so that the formed touch electrode F510 is a transparent electrode. In one embodiment of the present disclosure, the materials of the touch wiring layer and the touch electrode layer may be light-transmitting materials, for example, transparent conductive metal oxides (such as indium tin oxide, etc.). Of course, in other embodiments of the present disclosure, the touch wiring layer and the touch electrode layer may also be made of opaque materials, for example, may be a metal film layer; the patterns formed by the touch wiring layer and the touch electrode layer can expose each sub-pixel to avoid shielding the sub-pixels. Illustratively, the orthographic projection of the patterns of the touch wiring layer and the touch electrode layer on the substrate may be located within the orthographic projection of the surface of the pixel defining layer away from the substrate on the substrate; namely, each metal structure on the touch wiring layer and the touch electrode layer may be disposed between the pixel openings of the pixel defining layer.

The shape and position of the touch electrode can be set according to the requirement of the display panel, so that the touch functional layer F500 can determine the touch position based on the self-capacitance or mutual capacitance principle. The touch functional layer F500 may also be used to form a touch trace so as to conduct signals generated by the touch electrode in response to a touch operation.

For example, referring to fig. 3 and 4, in one embodiment of the present disclosure, the touch electrode F510 includes a plurality of row touch electrodes F512 extending along the row direction H1 and a plurality of column touch electrodes F511 extending along the column direction H2. The row touch electrodes F512 are sequentially arranged along the column direction H2, and the column touch electrodes F511 are sequentially arranged along the row direction H1. Any one of the column touch electrodes F511 is disposed on the touch electrode layer, and includes a plurality of column touch sub-electrodes F5111 sequentially arranged along the column direction H2, and ends of two adjacent column touch sub-electrodes F5111 are connected to each other. Thus, the row touch electrode F511 is completely disposed on the touch electrode layer. Any one of the row touch electrodes F512 includes a plurality of row touch sub-electrodes F5121 sequentially arranged along the row direction H1, the row touch sub-electrodes F5121 are disposed on the touch electrode layer, and the edges of the row touch sub-electrodes F5121 are disposed adjacent to the edges of the column touch sub-electrodes F5111. In any one of the row touch electrodes F512, two adjacent row touch sub-electrodes F5121 are separated by the column touch electrode F511, and the two adjacent row touch sub-electrodes F5121 are connected by a bridging connection portion F5131 located in the touch wiring layer.

For example, in another embodiment of the present disclosure, the touch electrodes include a plurality of row touch electrodes extending in a row direction and a plurality of column touch electrodes extending in a column direction. Each row of touch electrodes is sequentially arranged along the column direction, and each column of touch electrodes is sequentially arranged along the row direction. Any one row of touch electrodes is arranged on the touch electrode layer and comprises a plurality of row of touch sub-electrodes which are sequentially arranged along the row direction, and the end parts of two adjacent row of touch sub-electrodes are mutually connected. Thus, the row touch electrode is completely arranged on the touch electrode layer. Any one of the column touch electrodes comprises a plurality of column touch sub-electrodes which are sequentially arranged along the column direction, wherein the column touch sub-electrodes are arranged on the touch electrode layer, and the edges of the column touch sub-electrodes are adjacent to the edges of the row touch sub-electrodes. In any one column touch electrode, two adjacent column touch sub-electrodes are isolated by a row touch electrode, and the two adjacent column touch sub-electrodes are connected through a bridging connection part positioned on a touch wiring layer.

For example, in another embodiment of the present disclosure, the touch electrode includes a plurality of row touch electrodes extending along a row direction and a plurality of column touch electrodes extending along a column direction. Each row of touch electrodes is arranged in sequence along the row direction, and each row of touch electrodes is arranged in sequence along the row direction. One of the row touch electrodes and the column touch electrodes is arranged on the touch wiring layer, and the other is arranged on the touch electrode layer. Thus, the row touch electrodes and the column touch electrodes are overlapped with each other to form mutual capacitance. When the touch control functional layer is pressed by a touch control object such as a finger, the mutual capacitance between the row touch control electrode and the column touch control electrode is changed.

For example, in another embodiment of the present disclosure, the touch electrode array is distributed on the touch electrode layer, and the touch trace L1 extends to be connected to each touch electrode through the via hole through the touch wiring layer.

For example, in another embodiment of the present disclosure, the touch electrodes include a plurality of row touch electrodes extending in a row direction and a plurality of column touch electrodes extending in a column direction. Each row of touch electrodes is sequentially arranged along the column direction, and each column of touch electrodes is sequentially arranged along the row direction. Any one row of touch electrodes is arranged on the touch electrode layer and is positioned between the pixel openings of the pixel definition layer. Any one of the column touch electrodes comprises a plurality of column touch sub-electrodes which are sequentially arranged along the column direction, and the column touch sub-electrodes are arranged on the touch electrode layer and are positioned between the pixel openings of the pixel definition layer. In any one column touch electrode, two adjacent column touch sub-electrodes are connected through a bridging connection part positioned on the touch wiring layer. Wherein the bridging connection part is also positioned between the pixel openings.

For example, in another embodiment of the present disclosure, the touch electrodes include a plurality of row touch electrodes extending in a row direction and a plurality of column touch electrodes extending in a column direction. Each row of touch electrodes is sequentially arranged along the column direction, and each column of touch electrodes is sequentially arranged along the row direction. Any one row of touch electrodes is arranged on the touch electrode layer and is positioned between the pixel openings of the pixel definition layer. Any one row touch electrode comprises a plurality of row touch sub-electrodes which are sequentially arranged along the row direction, and the row touch sub-electrodes are arranged on the touch electrode layer and are positioned between pixel openings of the pixel definition layer. In any one row touch electrode, two adjacent row touch sub-electrodes are connected through a bridging connection part positioned on the touch wiring layer. Wherein the bridging connection part is also positioned between the pixel openings.

In the display panel provided in the disclosure, referring to fig. 5, the touch wiring layer is formed with a plurality of traces in the peripheral area BB, and the area where the traces are distributed is a touch trace area LAD. These traces on the touch routing layer may be connected to bond pads on bond region B1. Referring to fig. 6,7 and 8, the traces on the touch wiring layer may include two reference voltage traces L2 (only one is shown in the drawings) and a plurality of touch traces L1, where each touch trace L1 is disposed between two reference voltage traces L2. The touch trace L1 may connect the touch electrode and the bonding pad C, so as to transmit a touch signal generated by the touch electrode to the bonding pad C. In some embodiments of the present disclosure, referring to fig. 8 and 10, at one end near the bonding area B1, the respective touch traces L1 may be arranged side by side and connected to the respective bonding pads C in a one-to-one correspondence.

It can be appreciated that, in the display panel of the present disclosure, the driving circuit layer and the touch function layer both load or transmit signals, and the signals on the driving circuit layer may generate crosstalk to the touch signals on the touch trace L1, which may further cause touch failure, for example, cause the display panel to not respond to touch actions, respond to touch action errors, and so on. In the present disclosure, each touch trace L1 is located between two reference voltage traces L2. The reference voltage trace L2 may be loaded with a reference voltage, and since the reference voltage is a constant voltage signal (for example, ground voltage GND), the reference voltage trace L2 may shield signals on the driving circuit layer at two sides of each touch trace L1, so as to weaken crosstalk of signals on the driving circuit layer on the touch trace L1, reduce probability of touch failure, and improve stability and accuracy of touch.

In some embodiments of the present disclosure, the area of any one of the reference voltage traces L2 may be larger than the area of any one of the reference voltage traces L2. Therefore, the reference voltage wiring L2 can more effectively balance crosstalk of signals on the driving circuit layer, so that the crosstalk degree of the signals on the driving circuit layer to the touch wiring L1 is weakened, and the risk of touch failure is reduced. In the present disclosure, the area of a trace refers to the area of the orthographic projection of the trace on a substrate. It will be appreciated that the wider the trace, the longer the trace, the larger the area of the trace.

Illustratively, in one embodiment of the present disclosure, referring to fig. 10, the reference voltage trace L2 has a width greater than the width of the touch trace L1. Therefore, compared with the scheme that the widths of the reference voltage wire L2 and the touch wire L1 are equal, the embodiment can enable the area of the reference voltage wire L2 to be larger than that of the touch wire L1. Alternatively, referring to fig. 10, the touch trace L1 and the reference voltage trace L2 are each connected to one binding sub-pad C01. The width of the touch control wires L1 is smaller than that of the binding sub-pads C01, so that the interval between the touch control wires L1 can be increased, and crosstalk between the touch control wires L1 is reduced. The width of the reference voltage trace L2 is not smaller than the width of the binding sub-pad C01, for example, the width of the reference voltage trace L2 is equal to the width of the binding sub-pad C01. Thus, the reference voltage trace L2 has a larger width, so that crosstalk of signals on the driving circuit layer to the touch trace L1 can be better shielded. Further, the width of the reference voltage trace L2 may be 1.5-3 times the width of the touch trace L1.

Still further exemplary, in another embodiment of the present disclosure, referring to fig. 6 and 7, the reference voltage trace L2 includes a plurality of reference voltage sub-traces disposed side by side; the plurality of reference voltage sub-wires comprise a main reference voltage sub-wire L21 and an auxiliary reference voltage sub-wire L22; both ends of any one of the auxiliary reference voltage sub-wires L22 are connected to the main reference voltage sub-wire L21. Therefore, by arranging the plurality of parallel reference voltage sub-wires, the area of the reference voltage wire L2 can be increased, and the shielding effect on signals on the driving circuit layer is further improved.

Optionally, the auxiliary reference voltage sub-trace L22 is located on a side of the main reference voltage sub-trace L21 away from the touch trace L1, so as to avoid compressing gaps between different traces on the touch wiring layer.

Optionally, the width of the auxiliary reference voltage sub-trace L22 is the same as the width of the main reference voltage sub-trace L21. Further, the widths of the auxiliary reference voltage sub-trace L22, the main reference voltage sub-trace L21 and the touch control trace L1 are the same.

Optionally, the length of the auxiliary reference voltage sub-trace L22 is smaller than the length of the main reference voltage sub-trace L21.

Optionally, the number of auxiliary reference voltage sub-wirings L22 is one or two, for example, may be one.

In some embodiments of the present disclosure, referring to fig. 6 and 7, in the peripheral area BB of the display panel, the touch wiring layer is further provided with two shielding traces L3 (only one is shown in the drawings); each touch control wire L1 is located between two shielding wires L3, and any one shielding wire L3 is located between the reference voltage wire L2 and the touch control wire L1. In other words, the shielding trace L3 and the reference voltage trace L2 are sequentially disposed outside each touch trace L1, so as to shield crosstalk of signals on the driving circuit layer on the touch trace L1.

Referring to fig. 7, the shield trace L3 may be connected with the bonding pad C. Alternatively, the bonding pad C connected to the shielding trace L3 may be one bonding sub-pad C01.

In one embodiment of the present disclosure, an area of any one of the shielding traces L3 is larger than an area of any one of the touch traces L1. Therefore, the shielding wiring L3 has a larger area, and the shielding effect on signals of the pixel driving circuit layer can be improved.

Optionally, referring to fig. 8 and 10, the width of the shielding trace L3 is greater than the width of the touch trace L1. Therefore, the shielding wire L3 has a larger width, and can weaken the crosstalk of the transverse signal to the touch wire L1. Further, the width of the shielding trace L3 is not smaller than the width of the binding sub-pad C01. Illustratively, in one particular embodiment of the present disclosure, the width of the shield trace L3 is equal to the width of the binding sub-pad C01.

In the present disclosure, according to the trace to which the bonding pad C is connected, the bonding pad C may include a touch bonding pad connected to the touch trace L1, a reference voltage pad connected to the reference voltage trace L2, and a shielding bonding pad connected to the shielding trace L3. The number of the touch binding pads is multiple, and the touch binding pads are connected with each touch routing L1 in a one-to-one correspondence manner. The number of the reference voltage pads is two, and the reference voltage pads are connected with the two reference voltage wirings L2 in a one-to-one correspondence. The number of the shielding binding pads is two, and the shielding binding pads are connected with the two shielding wires L3 in a one-to-one correspondence manner.

In some embodiments, referring to fig. 5, the driving circuit layer is provided with a second power bus LVSS at the peripheral region BB, and the bonding pad C connected to the second power bus LVSS is a second power pad. The number of the second power supply pads is two, and the second power supply pads are respectively positioned on one side of the reference voltage pad far away from the touch binding pad. Because the second power supply voltage with constant voltage is loaded on the second power supply pad, the second power supply pad can shield crosstalk of other wires on the driving circuit layer to the touch pad. Referring to fig. 8, in one embodiment of the present disclosure, the second power pad may include a plurality of binding sub-pads C01, for example, may include a plurality of binding sub-pads C01 that are sequentially adjacent. Illustratively, the second power supply pad includes eight binding sub-pads C01 that are sequentially adjacent, each of the eight binding sub-pads C01 being connected to the second power supply bus LVSS.

In one embodiment of the present disclosure, referring to fig. 8, a distance between the reference voltage pad and the second power supply pad is greater than a distance between two adjacent touch binding pads. Therefore, the distance between the reference voltage pad and the second power supply pad can be increased, so that the transverse crosstalk of signals on the second power supply pad to the reference voltage pad is reduced, and the crosstalk to the touch wiring L1 and the touch pad is reduced.

Optionally, a floating binding sub-pad C03 is provided between the reference voltage pad and the second power supply pad; the floating binding sub-pad C03 is not connected to each trace. In this way, the floating binding sub-pad C03 may increase the spacing between the reference voltage pad and the second power pad, thereby reducing lateral crosstalk. In one particular embodiment of the present disclosure, there are two floating binding sub-pads C03 between the reference voltage pad and the second power supply pad.

In one embodiment of the present disclosure, referring to fig. 8, the touch trace L1, the reference voltage trace L2, and the shielding trace L3 at least partially overlap the second power bus LVSS. In this way, the second power bus LVSS may play a role of shielding the touch trace L1. In a specific embodiment of the present disclosure, a majority of the length of the touch trace L1 overlaps the second power bus LVSS.

In some embodiments, referring to fig. 5, the driving circuit layer of the display panel further includes a first power bus LVDD at the peripheral region BB, and the first power bus LVDD is used to load the first power voltage VDD to the display region AA. The first power supply bus LVDD may be connected to at least one first power supply pad, where the first power supply pad is located at a side of the second power supply pad away from the touch pad. Referring to fig. 11, in one embodiment of the present disclosure, the first power pad may include a plurality of binding sub-pads C01, for example, may include a plurality of binding sub-pads C01 that are sequentially adjacent. Illustratively, the first power supply pad includes eight binding sub-pads C01 that are sequentially adjacent, each of the eight binding sub-pads C01 being connected to the first power supply bus LVDD.

Optionally, the binding sub-pad C03 is floating between the second power pad and the first power pad; the floating binding sub-pad C03 is not connected to each trace. In this way, the floating binding sub-pad C03 can increase the distance between the first power pad and the second power pad, thereby facilitating the alignment and binding of the external circuit. In one particular embodiment of the present disclosure, there are two floating bond sub-pads C03 between the first power pad and the second power pad.

In some embodiments, at a position near the display area AA, the touch trace L1, the shielding trace L3, and the reference voltage trace L2 may be used for overlapping the common electrode, so that the common electrode may provide electromagnetic shielding for the touch trace L1, the shielding trace L3, and the reference voltage trace L2, so as to reduce crosstalk of signals generated by the driving circuit layer on the touch trace L1.

In some embodiments, referring to fig. 1, the display panel may further include a peripheral inflection region B2, where the peripheral inflection region B2 is located in the peripheral region BB and between the bonding region B1 and the display region AA. The display panel can be bent at the peripheral bending area B2, so that the binding area B1 is bent to the back surface of the display panel. Therefore, the frame of the display device applying the display panel can be reduced, and the screen occupation ratio of the display device can be improved.

Alternatively, referring to fig. 5 and 6, the touch trace L1, the reference voltage trace L2, and the shielding trace L3 may be interrupted at an external bending region and connected through the bridging trace L4 located in the bending region. The bridging line L4 may be located in the driving circuit layer, for example, may be located in the source-drain metal layer. Therefore, the thickness of the display panel in the peripheral bending area B2 can be reduced, the flexibility of the display panel can be improved, and the display panel can be bent in the peripheral bending area B2. Further, referring to fig. 5, the second power bus LVSS may be hollowed out in the peripheral bending area B2, and a bridging avoidance space LBD is surrounded; each crossover trace L4 may be located within the crossover relief space LBD. In this way, the second power bus LVSS can provide electromagnetic shielding for each bridging line L4 in the peripheral bending region B2, so as to reduce crosstalk of other signals to each bridging line L4.

In some embodiments, the touch electrode layer may also form auxiliary wirings corresponding to each of the touch wirings L1, each of the reference voltage wirings L2, and each of the shielding wirings L3 one by one. The touch control wiring L1 and the corresponding auxiliary wiring are connected through the through holes and are arranged in parallel, so that the impedance of the touch control wiring L1 can be reduced, the voltage drop of a touch control signal on the touch control wiring L1 is reduced, and the touch control precision and sensitivity are improved. The reference voltage wire L2 and the corresponding auxiliary wire are connected through the via hole and are arranged in parallel, so that the impedance of the reference voltage wire L2 can be reduced, the parasitic capacitance of the reference voltage wire L2 can be improved, and the shielding effect of the reference voltage wire L2 on transverse crosstalk signals can be further improved. The shielding wire L3 is connected with the corresponding auxiliary wire through the via hole and is arranged in parallel, so that the impedance of the shielding wire L3 can be reduced, the parasitic capacitance of the shielding wire L3 can be improved, and the shielding effect of the shielding wire L3 on transverse crosstalk signals can be improved.

In the present disclosure, the bonding pad may be provided with a driving circuit layer or a touch function layer. Illustratively, referring to fig. 8, 10, 11, and 13, in one embodiment of the present disclosure, the bonding pad C is disposed at the touch wiring layer. At the driving circuit layer, for example, at the source-drain metal layer, referring to fig. 9, 10, 11 and 12, the display panel is further provided with an auxiliary pad C02 overlapping the bonding pad C at the bonding area B1, and the auxiliary pad C02 is disposed at the same layer as the second power bus LVSS and the first power bus LVDD and is connected to the bonding pad C through a via hole. In this way, the surfaces of the bonding pads C can be guaranteed to be at the same height, and bonding with an external circuit is utilized. The touch control wire L1, the reference voltage wire L2 and the shielding wire L3 are arranged on the same layer as the binding pad C and are connected. The second power supply bus LVSS is connected to the auxiliary pad C02, and the first power supply bus LVDD is connected to the auxiliary pad C02. In one embodiment of the present disclosure, the second power pad includes a plurality of binding sub-pads C01, and the auxiliary pads C02 to which the binding sub-pads C01 are connected to each other. The first power supply pad includes a plurality of binding sub-pads C01, and auxiliary pads C02 to which the binding sub-pads C01 are connected to each other.

The disclosed embodiments also provide a display device including any one of the display panels described in the above display panel embodiments. The display device may be a smart phone, tablet computer, or other type of display device. Since the display device has any one of the display panels described in the above embodiments of the display panel, the display device has the same beneficial effects, and the disclosure is not repeated here.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A display panel comprises a substrate, a driving circuit layer, a pixel layer and a touch control functional layer which are sequentially stacked;

The area of any one of the reference voltage wires is larger than that of any one of the touch wires;

The pixel layer is provided with a common electrode; the driving circuit layer is provided with a second power bus in the peripheral area of the display panel; the second power bus is used for loading a second power voltage to the common electrode;

the distance between the reference voltage bonding pad and the second power supply bonding pad is larger than the distance between two adjacent touch bonding pads;

in the binding area, the display panel is provided with a plurality of binding sub-bonding pads which are linearly and equidistantly arranged; any one of the bond pads includes at least one of the bond sub-pads;

2. The display panel of claim 1, wherein the reference voltage trace has a width that is greater than a width of the touch trace.

3. The display panel of claim 2, wherein the peripheral region comprises a binding region; in the binding area, the display panel is provided with a plurality of binding sub-bonding pads;

4. The display panel of claim 1, wherein the reference voltage trace comprises a main reference voltage sub-trace and at least one auxiliary reference voltage sub-trace disposed side-by-side with the main reference voltage sub-trace; both ends of any one auxiliary reference voltage sub-wiring are connected to the main reference voltage sub-wiring.

5. The display panel of claim 4, wherein the main reference voltage sub-trace and the auxiliary reference voltage sub-trace have the same width and are both equal to the width of the touch trace.

6. The display panel according to claim 1, wherein the touch wiring layer is further provided with two shielding wirings in a peripheral region of the display panel; each touch control wire is positioned between two shielding wires, and any one shielding wire is positioned between the reference voltage wire and the touch control wire;

The area of any one shielding wire is larger than that of any one touch wire.

7. The display panel of claim 6, wherein the width of the shielding trace is greater than the width of the touch trace.

8. The display panel of claim 7, wherein the peripheral region comprises a binding region; in the binding area, the display panel is provided with a plurality of binding sub-bonding pads;

9. A display device comprising the display panel of any one of claims 1 to 8.