CN113157143A

CN113157143A - Display panel and display device

Info

Publication number: CN113157143A
Application number: CN202110576674.6A
Authority: CN
Inventors: 何帆; 张顺
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-05-26
Filing date: 2021-05-26
Publication date: 2021-07-23
Anticipated expiration: 2041-05-26
Also published as: CN113157143B

Abstract

The disclosure provides a display panel and a display device, and belongs to the technical field of display. The display panel comprises a substrate base plate, a driving circuit layer, a pixel layer and a touch functional layer which are sequentially stacked; the touch function layer comprises a touch wiring layer; in the peripheral area of the display panel, the touch wiring layer is provided with two reference voltage wires and a plurality of touch wires; each touch wire is arranged between two reference voltage wires; the area of any one of the reference voltage traces is larger than that of any one of the touch traces. The display panel provided by the disclosure can reduce the probability of touch failure.

Description

Display panel and display device

Technical Field

The disclosure relates to the technical field of display, in particular to a display panel and a display device.

Background

In an FMLOC (Flexible Multi-Layer On Cell) product, a touch functional Layer can be directly prepared On the surface of a display back panel, so that the thickness of the touch display panel is reduced. In an FMLOC product, both touch signal routing and display back panel routing are connected to a binding region; this results in the touch signal routing easily receiving the signal of display backplate to crosstalk, has increased the probability of touch-control inefficacy.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure is directed to overcome the above disadvantages of the prior art, and provides a display panel and a display device, which reduce the probability of touch failure.

According to one aspect of the present disclosure, a display panel is provided, which includes a substrate, a driving circuit layer, a pixel layer, and a touch functional layer, which are sequentially stacked;

the touch function layer comprises a touch wiring layer; in the peripheral area of the display panel, the touch wiring layer is provided with two reference voltage wires and a plurality of touch wires; each touch wire is arranged between two reference voltage wires;

the area of any one of the reference voltage traces is larger than that of any one of the touch traces.

According to an embodiment of the present disclosure, a width of the reference voltage trace is greater than a width of the touch trace.

According to one embodiment of the present disclosure, the peripheral region includes a binding region; in the binding region, the display panel is provided with a plurality of binding sub-pads;

the width of the reference voltage routing is not less than that of the bonding pads of the binding stator;

the width of the touch routing is smaller than that of the binding sub-bonding pad.

According to one embodiment of the present disclosure, the reference voltage trace includes a main reference voltage sub-trace and at least one auxiliary reference voltage sub-trace arranged side by side with the main reference voltage sub-trace; both ends of any one of the auxiliary reference voltage sub-wirings are connected to the main reference voltage sub-wiring.

According to an embodiment of the present disclosure, the main reference voltage sub-trace and the auxiliary reference voltage sub-trace have the same width and are equal to the width of the touch trace.

According to one embodiment of the present disclosure, in a peripheral area of the display panel, the touch routing layer is further provided with two shielding traces; each touch wire is positioned between two shielding wires, and any one shielding wire is positioned between the reference voltage wire and the touch wire;

the area of any one of the shielding traces is larger than that of any one of the touch traces.

According to an embodiment of the present disclosure, the width of the shielding trace is greater than the width of the touch trace.

the width of the shielding routing is equal to the width of the binding sub-bonding pad.

According to one embodiment of the present disclosure, the pixel layer is provided with a common electrode; the driving circuit layer is provided with a second power supply bus in the peripheral area of the display panel; the second power supply bus is used for loading a second power supply voltage to the common electrode;

the peripheral region comprises a bonding region; the display panel is provided with a plurality of binding pads which are arranged in a straight line in the binding area;

the binding pads comprise a plurality of touch binding pads which are correspondingly connected with the touch wires one by one, two reference voltage pads which are correspondingly connected with the two reference voltage wires one by one, and a second power supply pad which is connected with the second power supply bus;

and the distance between the reference voltage bonding pad and the second power supply bonding pad is larger than the distance between two adjacent touch binding bonding pads.

According to one embodiment of the present disclosure, in the bonding area, the display panel is provided with a plurality of bonding sub-pads arranged in a straight line at equal intervals; any one of the bonding pads comprises at least one of the bonding sub-pads;

the bonding sub-pad having a floating connection between the reference voltage pad and the second power supply pad.

According to another aspect of the present disclosure, a display device is provided, which includes the display panel described above.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.

Fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the disclosure.

Fig. 3 is a schematic view of a partial structure of a touch electrode layer according to an embodiment of the disclosure.

Fig. 4 is a schematic cross-sectional structure diagram of the touch functional layer at position P1P2 in fig. 3.

Fig. 5 is a schematic partial structure diagram of a peripheral region according to an embodiment of the disclosure.

Fig. 6 is a schematic view of a local structure of the touch wiring layer and the source drain metal layer near the external bending region in an embodiment of the present disclosure.

Fig. 7 is a schematic view of a local structure of a touch routing layer near a bonding area according to an embodiment of the disclosure.

Fig. 8 is a schematic view of a local structure of a touch wiring layer and a source drain metal layer near a bonding region in an embodiment of the present disclosure.

Fig. 9 is a schematic view of a local structure of a source drain metal layer near a bonding region in an embodiment of the present disclosure.

Fig. 10 is a schematic view of a local structure of a touch routing layer near a bonding area according to an embodiment of the disclosure.

Fig. 11 is a schematic view of a local structure of a touch wiring layer and a source drain metal layer near a bonding region in an embodiment of the present disclosure.

Fig. 12 is a schematic view of a local structure of a source drain metal layer near a bonding region in an embodiment of the present disclosure.

Fig. 13 is a schematic view of a local structure of a touch routing layer near a bonding area according to an embodiment of the disclosure.

Description of reference numerals:

AA. A display area; BB. A peripheral region; b1, a binding area; b2, peripheral bending zone; C. bonding pads; c01, binding sub-pad; c02, auxiliary pad; c03, floating binding sub-pad; l1, touch routing; l2, reference voltage trace; l21, main reference voltage sub-trace; l22, auxiliary reference voltage sub-trace; l3, shield routing; l4, jumper trace; LVDD, a first power bus; LVSS, second power bus; h1, row direction; h2, column direction; f100, a substrate base plate; f200, a driving circuit layer; F200M, transistor; f201, a barrier layer; f202, a buffer layer; f203, a semiconductor layer; f204, a gate insulating layer; f205, a gate layer; f206, an interlayer dielectric layer; f207, a source drain metal layer; f208, a planarization layer; f300, a pixel layer; f301, a pixel electrode layer; f302, a pixel definition layer; f303, supporting a column layer; f304, an organic light-emitting functional layer; f305, a common electrode layer; f400, a thin film packaging layer; f401, a first inorganic packaging layer; f402, an organic packaging layer; f403, a second inorganic packaging layer; f500, reducing the reflection layer; f600, a touch functional layer; f501, touch control wiring layers; f502, touch control insulating layer; f503, a touch electrode layer; f510, touch control electrodes; f511, arranging touch electrodes; f5111, column touch sub-electrodes; f512, row touch electrodes; f5121, a row touch sub-electrode; f5131, bridge connection.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

The terms "a," "an," "the," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first" and "second", etc. are used merely as labels, and are not limiting on the number of their objects.

The present disclosure provides a display panel and a display device based on the same. Referring to fig. 1, the display panel PNL includes a display area AA and a peripheral area BB surrounding the display area AA from a top view. On one side of the display area AA, the peripheral area BB has a binding area B1. Referring to fig. 8, the display panel is provided with a plurality of bonding pads C in a bonding area B1 so that an external circuit is bonded to the display panel through the bonding pads C. The external circuit may be a Chip On Film (COF), a flexible circuit board, or other types of circuit structures.

In some embodiments of the present disclosure, within the bonding region B1, the respective bonding pads C may be aligned in a first direction. In this way, alignment and bonding between the external circuit and the bonding pad C are facilitated. The bonding pad C may be rectangular or parallelogram as a whole. For example, referring to fig. 8, the bonding pad C has a parallelogram shape as a whole, which includes two first edges disposed opposite to each other and extending along the first direction, and includes two second edges disposed opposite to each other and extending along the second direction. The first edges of the same end of each bonding pad C are located on the same straight line, or may not be located on the same straight line.

Alternatively, the widths between any two bonding pads C may be the same or different. In the present disclosure, the width of the bonding pad C refers to a dimension of the bonding pad C in the first direction.

Optionally, any one of the bonding pads C may be an integral plate-shaped bonding pad, or may be a hollow bonding pad having a slit. For example, referring to fig. 8, at least one of the bonding pads C may be a stencil pad, the stencil pad includes a plurality of bonding sub-pads C01 arranged in parallel and adjacent to each other in sequence along a first direction, and the bonding sub-pads C01 are connected to a same trace and then serve as the bonding pads C connected to the trace.

In one embodiment of the present disclosure, within the bonding region B1, the display panel may include a plurality of bonding sub-pads C01. The binding sub-pads C01 may be arranged in a straight line in the first direction and equally spaced, and the width of each binding sub-pad C01 is the same. The bonding pad C of the present disclosure may include one bonding sub-pad C01, or include a plurality of bonding sub-pads C01 disposed adjacently. For example, if a trace is connected to a bond sub-pad C01, the bond sub-pad C01 serves as the bond pad C connected to the trace. As another example, a trace is connected to a plurality of adjacent bonding pads C01, and the plurality of bonding pads C01 may constitute the bonding pad C of the trace. Optionally, the bonding sub-pad C01 has a parallelogram shape including two first edges disposed opposite to each other and extending along the first direction, and two second edges disposed opposite to each other and extending along the second direction.

Referring to fig. 2, the display panel includes a substrate F100, a driving circuit layer F200, a pixel layer F300, and a touch functional layer F500, which are sequentially stacked from the viewpoint of film layers.

In the present disclosure, the base substrate F100 may be an inorganic base substrate F100 or an organic base substrate F100. For example, in one embodiment of the present disclosure, the material of the substrate F100 may be a glass material such as soda-lime glass (soda-lime glass), quartz glass, or sapphire glass, or may be a metal material such as stainless steel, aluminum, or nickel. In another embodiment of the present disclosure, the material of the substrate F100 may be Polymethyl methacrylate (PMMA), Polyvinyl alcohol (PVA), Polyvinyl phenol (PVP), Polyether sulfone (PES), polyimide, polyamide, polyacetal, Polycarbonate (PC), Polyethylene terephthalate (PET), Polyethylene naphthalate (PEN), or a combination thereof. In another embodiment of the present disclosure, the substrate F100 may also be a flexible substrate F100, for example, the material of the substrate F100 may be Polyimide (PI). The substrate F100 may also be a composite of multiple layers of materials, for example, in an embodiment of the present disclosure, the substrate F100 may include a Bottom Film layer (Bottom Film), a pressure sensitive adhesive layer, a first polyimide layer, and a second polyimide layer, which are sequentially stacked.

It is to be understood that, when the substrate of the present disclosure is a flexible substrate, the display panel of the present disclosure may be a flexible display panel.

Alternatively, in the driver circuit layer F200, any one of the pixel driver circuits may include the transistor F200M and a storage capacitor. Further, the transistor F200M may be a thin film transistor, which may be a top gate type thin film transistor, a bottom gate type thin film transistor, or a double gate type thin film transistor; the material of the active layer of the thin film transistor can be an amorphous silicon semiconductor material, a low-temperature polysilicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material or other types of semiconductor materials; the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor. In one embodiment of the present disclosure, the thin film transistor is a low temperature polysilicon transistor.

It is to be understood that the type between any two transistors in the respective transistors in the pixel driving circuit may be the same or different. For example, in one embodiment, in one pixel driving circuit, part of the transistors may be N-type transistors and part of the transistors may be P-type transistors. Still illustratively, in another embodiment of the present disclosure, in one pixel driving circuit, the material of the active layer of a part of the transistors may be a low temperature polysilicon semiconductor material, and the material of the active layer of a part of the transistors may be a metal oxide semiconductor material.

Alternatively, the driving circuit layer F200 may include a semiconductor layer F203, a gate insulating layer F204, a gate layer F205, an interlayer dielectric layer F206, a source-drain metal layer F207, and the like, which are stacked between the substrate F100 and the pixel layer F300. Each thin film transistor and storage capacitor may be formed of a semiconductor layer F203, a gate insulating layer F204, a gate layer F205, an interlayer dielectric layer F206, a source-drain metal layer F207, and the like. The position relation of each film layer can be determined according to the film layer structure of the thin film transistor. For example, in one embodiment of the present disclosure, the driving circuit layer F200 may include a semiconductor layer F203, a gate insulating layer F204, a gate electrode layer F205, an interlayer dielectric layer F206, and a source-drain metal layer F207, which are sequentially stacked, and the thin film transistor thus formed is a top gate thin film transistor. For another example, in another embodiment of the present disclosure, the driving circuit layer F200 may include a gate electrode layer F205, a gate insulating layer F204, a semiconductor layer F203, an interlayer dielectric layer F206, and a source-drain metal layer F207, which are sequentially stacked, and the thin film transistor formed in this way is a bottom gate thin film transistor. The driving circuit layer F200 may further adopt a double gate layer F205 structure, that is, the gate layer F205 may include a first gate layer and a second gate layer, and the gate insulating layer F204 may include a first gate insulating layer for isolating the semiconductor layer F203 from the first gate layer and a second gate insulating layer for isolating the first gate layer from the second gate layer. For example, in one embodiment of the present disclosure, the driving circuit layer F200 may include a semiconductor layer F203, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer F206, and a source-drain metal layer F207, which are sequentially stacked on one side of the substrate F100.

Optionally, the driving circuit layer may further be provided with different traces so as to load the pixel driving circuit with the required driving signal. For example, the driving circuit layer may be provided with a data trace for applying a data voltage to the pixel driving circuit, a first power trace for applying a first power voltage to the pixel driving circuit, a scan trace for applying a scan signal to the pixel driving circuit, and the like. In some embodiments, referring to fig. 5, the driving circuit layer may further be provided with a first power supply bus LVDD in the peripheral region, and the first power supply bus LVDD may be connected to each first power supply line and apply a first power supply voltage to each first power supply line.

Optionally, the driving circuit layer F200 may further include a passivation layer, and the passivation layer may be disposed on a surface of the source-drain metal layer F207 away from the substrate base plate F100, so as to protect the source-drain metal layer F207.

Alternatively, the driving circuit layer F200 may further include a buffer material layer disposed between the substrate F100 and the semiconductor layer F203, the gate layer F205, and the like are disposed on a side of the buffer material layer away from the substrate F100. The material of the buffer material layer may be an inorganic insulating material such as silicon oxide or silicon nitride. The buffer material layer may be a single inorganic material layer or a plurality of inorganic material layers stacked. Illustratively, in one embodiment of the present disclosure, referring to fig. 3, the buffer material layer may include a barrier layer F201 on a side close to the substrate F100 and a buffer layer F202 on a side of the barrier layer F201 away from the substrate F100. The barrier layer F201 is used to block ions and other components in the base substrate F100 from permeating into the driving circuit layer F200, so that the driving circuit layer F200 maintains stable performance. The buffer layer F202 may improve the bonding force between the driving circuit layer F200 and the substrate F100 and provide a stable environment for the driving circuit layer F200.

Optionally, the driving circuit layer F200 may further include a planarization layer F208 between the source-drain metal layer F207 and the pixel layer F300, and the planarization layer F208 may provide a planarized surface for the pixel electrode. Alternatively, the material of the planarization layer F208 may be an organic material.

The pixel layer F300 may be provided with light emitting elements electrically connected corresponding to the pixel driving circuit, and the light emitting elements may serve as sub-pixels of the display panel. In this way, the pixel layer is provided with light emitting elements distributed in an array, and each light emitting element emits light under the control of the pixel driving circuit. In the present disclosure, the light emitting element may be an organic electroluminescent diode (OLED), a Micro light emitting diode (Micro LED), a quantum dot-organic electroluminescent diode (QD-OLED), or other type of light emitting element. Illustratively, in one embodiment of the present disclosure, the light emitting element is an organic electroluminescent diode (OLED), and the display panel is an OLED display panel. As follows, taking the light emitting element as an organic electroluminescent diode as an example, a possible structure of the pixel layer is exemplarily described.

Referring to fig. 2, in the exemplary OLED display panel, a pixel layer may be disposed on a side of a driving circuit layer F200 away from a substrate F100, and may include a pixel electrode layer F301, a pixel defining layer F302, a support column layer F303, an organic light emitting function layer F304, and a common electrode layer F305, which are sequentially stacked. The pixel electrode layer F301 has a plurality of pixel electrodes in the display area AA of the display panel; the pixel defining layer F302 has a plurality of through pixel openings in the display area AA, which are disposed in one-to-one correspondence with the plurality of pixel electrodes, and any one of the pixel openings exposes at least a partial region of the corresponding pixel electrode. The support pillar layer F303 includes a plurality of support pillars in the display area AA, and the support pillars are located on the surface of the pixel defining layer F302 away from the substrate F100, so as to support a Fine Metal Mask (FMM) during an evaporation process. The organic light emitting functional layer F304 covers at least the pixel electrode exposed by the pixel defining layer F302. The organic light emitting functional layer F304 may include an organic electroluminescent material layer, and may include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. Each film layer of the organic light emitting functional layer F304 may be prepared by an evaporation process, and a pattern of each film layer may be defined by using a fine metal Mask or an Open Mask (Open Mask) during evaporation. The common electrode layer F305 may cover the organic light emitting functional layer F304 in the display area AA. In this way, the pixel electrode, the common electrode layer F305, and the organic light emitting function layer F304 between the pixel electrode and the common electrode layer F305 form the organic light emitting diode F300D, and any one of the organic electroluminescent diodes may serve as one sub-pixel of the display panel.

Alternatively, the common electrode layer is provided with a common electrode, and the common electrode is connected to the respective light emitting elements and multiplexed as an electrode of the respective light emitting elements. In this way, the common electrode can be applied with the second power voltage, and the second power voltage can be applied to each light emitting element. In some embodiments of the present disclosure, the driving circuit layer may be provided with a second power supply bus line LVSS at the peripheral area BB, the second power supply bus line LVSS being electrically connected to the common electrode. Thus, the second power supply bus line LVSS may apply the second power supply voltage to the common electrode.

In some embodiments, referring to fig. 2, the pixel layer F300 may further include a light extraction layer on a side of the common electrode layer F305 away from the substrate F100 to enhance the light extraction efficiency of the organic light emitting diode.

It is to be understood that the above exemplary description of the pixel layer is merely an example of one possible way, and the pixel layer of the OLED display panel may have other structures. When the type of light emitting element in the pixel layer is changed, the structure of the pixel layer of the display panel may also be changed.

In some embodiments, referring to fig. 2, the display panel may further include a thin film encapsulation layer F400. The thin film encapsulation layer F400 is disposed on a surface of the pixel layer F300 away from the substrate F100, and may include an inorganic encapsulation layer and an organic encapsulation layer alternately stacked. The inorganic packaging layer can effectively block outside moisture and oxygen, and prevents the organic light-emitting functional layer F304 from being invaded by the moisture and the oxygen to cause material degradation. Alternatively, the edge of the inorganic encapsulation layer may be located in the peripheral area BB. The organic encapsulation layer is positioned between two adjacent inorganic encapsulation layers so as to achieve planarization and reduce stress between the inorganic encapsulation layers. Wherein, the edge of the organic encapsulation layer may be located between the edge of the display area AA and the edge of the inorganic encapsulation layer. Illustratively, the thin film encapsulation layer F400 includes a first inorganic encapsulation layer F401, an organic encapsulation layer F402, and a second inorganic encapsulation layer F403, which are sequentially stacked on the side of the pixel layer F300 away from the substrate F100.

In some embodiments, the touch functional layer F500 may be disposed on a side of the thin film encapsulation layer F400 away from the substrate F100, for implementing a touch operation of the display panel.

In some embodiments, the display panel may further include a reflection reducing layer F600, and the reflection reducing layer F600 may be disposed on a side of the film encapsulation layer F400 away from the pixel layer F300, for reducing reflection of ambient light by the display panel, so as to reduce an influence of the ambient light on a display effect. In an embodiment of the present disclosure, the reflection reducing layer F600 may include a color film layer and a black matrix layer stacked on each other, so that the reduction of the transmittance of the display panel may be avoided while the reduction of the ambient light interference is achieved. In another embodiment of the present disclosure, the reflection reducing layer F600 may be a polarizer, for example, a patterned coated circular polarizer. Further, the reflection reducing layer F600 may be disposed on a side of the touch function layer F500 away from the base substrate F100.

In the display panel of the present disclosure, referring to fig. 4, the touch functional layer may include a touch wiring layer F501, a touch insulating layer F502, and a touch electrode layer F503, which are sequentially stacked. The touch electrode layer F503 is located on a side of the touch wiring layer F501 away from the substrate. One or two layers of the touch wiring layer and the touch electrode layer are used for forming a touch electrode. In one embodiment of the present disclosure, referring to fig. 2, the touch functional layer F500 is disposed on a side of the thin film encapsulation layer F400 away from the substrate.

Optionally, a touch buffer layer may be further included between the touch wiring layer and the thin film encapsulation layer F400. The touch buffer layer may be made of an inorganic material, such as silicon nitride, silicon oxide, or silicon oxynitride. It is understood that in other embodiments of the present disclosure, the outermost inorganic encapsulation layer of the thin film encapsulation layer F400 may also be reused as a touch buffer layer.

Optionally, a touch protection layer may be further included on a side of the touch electrode layer away from the base substrate F100. The material of the touch protection layer may be an inorganic material, and for example, may be silicon nitride, silicon oxide, silicon oxynitride, or the like. It is understood that in other embodiments of the present disclosure, the side of the touch electrode layer away from the substrate F100 may also be directly provided with an organic layer, for example, an organic cover plate or an optical adhesive.

Optionally, the touch wiring layer and the touch electrode layer may be transparent film layers, so that the formed touch electrode F510 is a transparent electrode. In one embodiment of the present disclosure, the material of the touch wiring layer and the touch electrode layer may be a light-transmitting material, for example, a transparent conductive metal oxide (such as indium tin oxide). Of course, in other embodiments of the present disclosure, the touch wiring layer and the touch electrode layer may also be made of an opaque material, for example, a metal film layer; the pattern formed by the touch wiring layer and the touch electrode layer can expose each sub-pixel so as to avoid shielding each sub-pixel. For example, the orthographic projection of the patterns of the touch wiring layer and the touch electrode layer on the substrate base plate can be positioned in the orthographic projection of the surface of the pixel definition layer away from the substrate base plate on the substrate base plate; that is, the metal structures on the touch wiring layer and the touch electrode layer may be disposed between the pixel openings of the pixel definition layer.

The shape and position of the touch electrode can be set according to the needs of the display panel, so that the touch functional layer F500 can determine the touch position based on the principle of self-capacitance or mutual capacitance. The touch function layer F500 can also be used to form touch traces so as to conduct out signals generated by the touch electrodes in response to a touch action.

For example, referring to fig. 3 and 4, in one embodiment of the present disclosure, the touch electrode F510 includes a plurality of row touch electrodes F512 extending along a row direction H1 and a plurality of column touch electrodes F511 extending along a column direction H2. The row touch electrodes F512 are sequentially arranged along the column direction H2, and the column touch electrodes F511 are sequentially arranged along the row direction H1. Any one of the row touch electrodes F511 is disposed on the touch electrode layer, and includes a plurality of row touch sub-electrodes F5111 sequentially arranged along the row direction H2, and ends of two adjacent row touch sub-electrodes F5111 are connected to each other. Thus, the row touch electrode F511 is completely disposed on the touch electrode layer. Any one of the row touch electrodes F512 includes a plurality of row touch sub-electrodes F5121 sequentially arranged along the row direction H1, and the row touch sub-electrodes F5121 are disposed on the touch electrode layer and have edges adjacent to the edges of the column touch sub-electrodes F5111. In any row touch electrode F512, two adjacent row touch sub-electrodes F5121 are isolated by the column touch electrode F511, and the two adjacent row touch sub-electrodes F5121 are connected by a bridge connection portion F5131 located on the touch wiring layer.

For another example, in another embodiment of the present disclosure, the touch electrode includes a plurality of row touch electrodes extending along a row direction and a plurality of column touch electrodes extending along a column direction. The row touch electrodes are sequentially arranged along the column direction, and the column touch electrodes are sequentially arranged along the row direction. Any one row touch electrode is arranged on the touch electrode layer and comprises a plurality of row touch sub-electrodes which are sequentially arranged along the row direction, and the end parts of two adjacent row touch sub-electrodes are mutually connected. Thus, the row touch electrodes are completely arranged on the touch electrode layer. Any one of the column touch electrodes includes a plurality of column touch sub-electrodes sequentially arranged along the column direction, the column touch sub-electrodes are disposed on the touch electrode layer, and the edges of the column touch sub-electrodes are disposed adjacent to the edges of the row touch sub-electrodes. In any one column of touch electrodes, two adjacent columns of touch sub-electrodes are isolated by the row touch electrode, and the two adjacent columns of touch sub-electrodes are connected by a bridging connection part located on the touch wiring layer.

For another example, in another embodiment of the present disclosure, the touch electrode includes a plurality of row touch electrodes extending along a row direction and a plurality of column touch electrodes extending along a column direction. The row touch electrodes are sequentially arranged along the column direction, and the column touch electrodes are sequentially arranged along the row direction. One of the row touch electrode and the column touch electrode is arranged on the touch wiring layer, and the other is arranged on the touch electrode layer. Therefore, the row touch electrodes and the column touch electrodes are mutually overlapped and form mutual capacitance. When the touch functional layer is pressed by a touch object such as a finger, the mutual capacitance between the row touch electrode and the column touch electrode changes.

For another example, in another embodiment of the present disclosure, the touch electrode array is distributed on the touch electrode layer, and the touch trace L1 extends through the touch wiring layer to connect with each touch electrode through the via hole.

For another example, in another embodiment of the present disclosure, the touch electrode includes a plurality of row touch electrodes extending along a row direction and a plurality of column touch electrodes extending along a column direction. The row touch electrodes are sequentially arranged along the column direction, and the column touch electrodes are sequentially arranged along the row direction. Any one of the rows of touch electrodes is disposed on the touch electrode layer and located between the pixel openings of the pixel definition layer. Any one of the column touch electrodes includes a plurality of column touch sub-electrodes sequentially arranged along the column direction, and the column touch sub-electrodes are disposed on the touch electrode layer and located between the pixel openings of the pixel definition layer. In any one column of touch electrodes, two adjacent columns of touch sub-electrodes are connected through a bridging connection part located in the touch wiring layer. Wherein the bridge connection is also located between the pixel openings.

For another example, in another embodiment of the present disclosure, the touch electrode includes a plurality of row touch electrodes extending along a row direction and a plurality of column touch electrodes extending along a column direction. The row touch electrodes are sequentially arranged along the column direction, and the column touch electrodes are sequentially arranged along the row direction. Any one of the row touch electrodes is disposed on the touch electrode layer and located between the pixel openings of the pixel definition layer. Any one of the row touch electrodes includes a plurality of row touch sub-electrodes sequentially arranged along the row direction, and the row touch sub-electrodes are disposed on the touch electrode layer and located between the pixel openings of the pixel definition layer. In any row of touch electrodes, two adjacent row of touch sub-electrodes are connected through a bridging connection part located in the touch wiring layer. Wherein the bridge connection is also located between the pixel openings.

In the display panel provided by the present disclosure, referring to fig. 5, the touch routing layer is formed with a plurality of traces in the peripheral area BB, and the area where the traces are distributed is the touch trace area LAD. These traces at the touch routing layer may be connected to the bond pads at the bonding area B1. Referring to fig. 6, 7 and 8, the traces on the touch routing layer may include two reference voltage traces L2 (only one is shown in the drawings) and a plurality of touch traces L1, wherein each of the touch traces L1 is disposed between two of the reference voltage traces L2. The touch trace L1 can connect the touch electrode and the bonding pad C, and further transmit a touch signal generated by the touch electrode to the bonding pad C. In some embodiments of the present disclosure, referring to fig. 8 and 10, at an end near the bonding area B1, each touch trace L1 may be arranged side by side and connected to each bonding pad C in a one-to-one correspondence.

It is understood that in the display panel of the present disclosure, the driving circuit layer and the touch function layer both load or transmit signals, and the signals on the driving circuit layer may generate crosstalk to the touch signals on the touch traces L1, which may result in touch failure, for example, causing the display panel to not respond to a touch action, respond to a touch action error, and the like. In the present disclosure, each touch trace L1 is located between two reference voltage traces L2. The reference voltage line L2 can be loaded with a reference voltage, and since the reference voltage is a constant voltage signal (e.g., a ground voltage GND), the reference voltage line L2 can shield signals on the driving circuit layer at two sides of each touch line L1, so as to weaken crosstalk of the signals on the driving circuit layer to the touch line L1, reduce the probability of touch failure, and improve the stability and accuracy of touch.

In some embodiments of the present disclosure, the area of any one of the reference voltage traces L2 may be larger than the area of any one of the reference voltage traces L2. Therefore, the reference voltage wire L2 can more effectively suppress crosstalk of signals on the driving circuit layer, so as to weaken the crosstalk degree of the signals on the driving circuit layer to the touch wire L1, and reduce the risk of touch failure. In the present disclosure, the area of a trace refers to the area of the orthographic projection of the trace on the substrate base plate. It will be appreciated that the wider the trace and the longer the trace, the greater the area of the trace.

Illustratively, in one embodiment of the present disclosure, referring to fig. 10, the width of the reference voltage trace L2 is greater than the width of the touch trace L1. Thus, compared to a solution in which the width of the reference voltage trace L2 is equal to that of the touch trace L1, the embodiment can make the area of the reference voltage trace L2 larger than that of the touch trace L1. Optionally, referring to fig. 10, the touch trace L1 and the reference voltage trace L2 are both connected to one bonding sub-pad C01. The width of the touch trace L1 is smaller than the width of the bonding sub-pad C01, so that the distance between the touch traces L1 can be increased, and the crosstalk between the touch traces L1 can be reduced. The width of the reference voltage trace L2 is not less than the width of the bonding sub-pad C01, e.g., the width of the reference voltage trace L2 is equal to the width of the bonding sub-pad C01. Thus, the reference voltage trace L2 has a larger width, so as to better shield the crosstalk of the signal on the driving circuit layer to the touch trace L1. Further, the width of the reference voltage trace L2 may be 1.5 to 3 times the width of the touch trace L1.

Still illustratively, in another embodiment of the present disclosure, referring to fig. 6 and 7, the reference voltage trace L2 includes a plurality of reference voltage sub-traces arranged side by side; the plurality of reference voltage sub-traces includes a main reference voltage sub-trace L21 and an auxiliary reference voltage sub-trace L22; both ends of any one of the auxiliary reference voltage sub-traces L22 are connected to the main reference voltage sub-trace L21. Therefore, the area of the reference voltage wiring L2 can be increased by arranging the plurality of reference voltage sub-wirings connected in parallel, and the shielding effect on signals on the driving circuit layer is further improved.

Optionally, the auxiliary reference voltage sub-line L22 is located on a side of the main reference voltage sub-line L21 away from the touch line L1, so as to avoid compressing gaps between different lines on the touch wiring layer.

Optionally, the width of the auxiliary reference voltage sub-line L22 is the same as the width of the main reference voltage sub-line L21. Further, the auxiliary reference voltage sub-line L22, the main reference voltage sub-line L21 and the touch line L1 have the same width.

Optionally, the length of the auxiliary reference voltage sub-trace L22 is less than the length of the main reference voltage sub-trace L21.

Optionally, the number of the auxiliary reference voltage sub-traces L22 is one or two, and may be one, for example.

In some embodiments of the present disclosure, referring to fig. 6 and 7, in a peripheral area BB of the display panel, the touch routing layer is further provided with two shielding traces L3 (only one is shown in the drawings); each of the touch traces L1 is located between two of the shielding traces L3, and any one of the shielding traces L3 is located between the reference voltage trace L2 and the touch trace L1. In other words, the shielding trace L3 and the reference voltage trace L2 are sequentially disposed outside each touch trace L1, so as to shield crosstalk of signals on the driving circuit layer to the touch trace L1.

Referring to fig. 7, the shield trace L3 may be connected with the bonding pad C. Alternatively, the bonding pad C connected to the shield trace L3 may be a bonding sub-pad C01.

In an embodiment of the disclosure, an area of any one of the shielding traces L3 is larger than an area of any one of the touch traces L1. Thus, the shielding trace L3 has a larger area, and the shielding effect on the signal of the pixel driving circuit layer can be further improved.

Optionally, referring to fig. 8 and 10, the width of the shielding trace L3 is greater than the width of the touch trace L1. Thus, the shielding trace L3 has a larger width, and can reduce crosstalk of the transverse signal to the touch trace L1. Further, the width of the shield trace L3 is not less than the width of the bonding sub-pad C01. Illustratively, in a specific embodiment of the present disclosure, the width of the shield trace L3 is equal to the width of the bonding sub-pad C01.

In the present disclosure, the bonding pads C may include a touch bonding pad connected with the touch trace L1, a reference voltage pad connected with the reference voltage trace L2, and a shield bonding pad connected with the shield trace L3 according to the trace to which the bonding pads C are connected. The number of the touch bonding pads is multiple, and the touch bonding pads are connected to the touch traces L1 in a one-to-one correspondence manner. The number of the reference voltage pads is two, and the reference voltage pads are connected to the two reference voltage traces L2 in a one-to-one correspondence. The number of the shielding bonding pads is two, and the shielding bonding pads are connected with the two shielding traces L3 in a one-to-one correspondence manner.

In some embodiments, referring to fig. 5, the driving circuit layer is provided with a second power supply bus line LVSS in a peripheral area BB, and a bonding pad C connected to the second power supply bus line LVSS is a second power supply pad. The number of the second power supply pads is two, and the second power supply pads are respectively located on one side of the reference voltage pad far away from the touch binding pad. Because the second power supply pad is loaded with the second power supply voltage with the constant voltage, the second power supply pad can shield crosstalk of other wires on the driving circuit layer to the touch pad. Referring to fig. 8, in one embodiment of the present disclosure, the second power supply pad may include a plurality of binding sub-pads C01, for example, may include a plurality of binding sub-pads C01 that are sequentially adjacent. Illustratively, the second power supply pad includes eight binding sub-pads C01 that are adjacent in sequence, and the eight binding sub-pads C01 are each connected to the second power supply bus line LVSS.

In an embodiment of the present disclosure, referring to fig. 8, a distance between the reference voltage pad and the second power supply pad is greater than a distance between two adjacent touch bonding pads. Therefore, the distance between the reference voltage pad and the second power supply pad can be increased, and then the transverse crosstalk of the signal on the second power supply pad to the reference voltage pad is reduced, and further the crosstalk to the touch trace L1 and the touch pad is reduced.

Optionally, a floating bonding sub-pad C03 between the reference voltage pad and the second power supply pad; the floating bonding sub-pad C03 is not connected to each trace. As such, the floating bonding sub-pad C03 may increase the spacing between the reference voltage pad and the second power supply pad, thereby reducing lateral crosstalk. In a specific embodiment of the present disclosure, there are two floating bonding sub-pads C03 between the reference voltage pad and the second power supply pad.

In one embodiment of the present disclosure, referring to fig. 8, the touch trace L1, the reference voltage trace L2, and the shield trace L3 at least partially overlap the second power bus LVSS. Thus, the second power bus LVSS can shield the touch trace L1. In an embodiment of the present disclosure, most of the length of the touch trace L1 overlaps the second power bus LVSS.

In some embodiments, referring to fig. 5, the driving circuit layer of the display panel further includes a first power supply bus line LVDD in the peripheral area BB, the first power supply bus line LVDD being for applying a first power supply voltage VDD to the display area AA. The first power supply bus LVDD may be connected to at least one first power supply pad, and the first power supply pad is located on a side of the second power supply pad away from the touch pad. Referring to fig. 11, in one embodiment of the present disclosure, the first power supply pad may include a plurality of binding sub-pads C01, for example, may include a plurality of binding sub-pads C01 that are sequentially adjacent. Illustratively, the first power supply pad includes eight binding sub-pads C01 that are adjacent in sequence, the eight binding sub-pads C01 each being connected to the first power supply bus line LVDD.

Optionally, the bond sub pad C03 is floating between the second power supply pad and the first power supply pad; the floating bonding sub-pad C03 is not connected to each trace. As such, the floating binding sub-pad C03 may increase the distance between the first power supply pad and the second power supply pad, thereby facilitating the alignment and binding of the external circuit. In a specific embodiment of the present disclosure, there are two floating bonding sub-pads C03 between the first power supply pad and the second power supply pad.

In some embodiments, at a position close to the display area AA, the touch trace L1, the shielding trace L3, and the reference voltage trace L2 may be used for overlapping common electrodes, so that the common electrodes may provide electromagnetic shielding for the touch trace L1, the shielding trace L3, and the reference voltage trace L2, and crosstalk of a signal generated by the driving circuit layer to the touch trace L1 is reduced.

In some embodiments, referring to fig. 1, the display panel may further include a peripheral bending region B2, and the peripheral bending region B2 is located in the peripheral region BB and between the binding region B1 and the display region AA. The display panel can be bent at the peripheral bending region B2, so that the binding region B1 is bent to the back of the display panel. Therefore, the frame of the display device using the display panel can be reduced, and the screen occupation ratio of the display device is improved.

Alternatively, referring to fig. 5 and 6, the touch trace L1, the reference voltage trace L2, and the shield trace L3 may be interrupted at the outer bending region and connected by the crossover trace L4 located in the bending region. The crossover trace L4 may be located in a driver circuit layer, for example, may be located in a source-drain metal layer. Therefore, the thickness of the display panel in the peripheral bending region B2 can be reduced, the flexibility of the display panel can be improved, and the display panel can be bent in the peripheral bending region B2. Further, referring to fig. 5, the second power bus LVSS may be hollowed out in the peripheral bending region B2 to surround a bridging avoidance space LBD; each crossover trace L4 may be located within the crossover avoidance space LBD. Thus, the second power bus LVSS at the peripheral inflection region B2 can provide electromagnetic shielding for each crossover trace L4, thereby reducing crosstalk of other signals to each crossover trace L4.

In some embodiments, the touch electrode layer may also form auxiliary traces corresponding to the respective touch traces L1, the respective reference voltage traces L2 and the respective shielding traces L3 one to one. The touch trace L1 and the corresponding auxiliary trace are connected by the via hole and are arranged in parallel, so that the impedance of the touch trace L1 can be reduced, the voltage drop of the touch signal on the touch trace L1 can be reduced, and the touch precision and sensitivity can be improved. The reference voltage wiring L2 and the corresponding auxiliary wiring are connected through a via hole and are arranged in parallel, so that the impedance of the reference voltage wiring L2 can be reduced, the parasitic capacitance of the reference voltage wiring L2 can be improved, and the shielding effect of the reference voltage wiring L2 on the transverse crosstalk signal can be improved. The shielding wiring L3 and the corresponding auxiliary wiring are connected through a via hole and arranged in parallel, so that the impedance of the shielding wiring L3 can be reduced, the parasitic capacitance of the shielding wiring L3 can be improved, and the shielding effect of the shielding wiring L3 on the transverse crosstalk signal can be improved.

In the present disclosure, the bonding pad may be provided with a driving circuit layer or a touch function layer. Illustratively, referring to fig. 8, 10, 11, and 13, in one embodiment of the present disclosure, the bonding pad C is disposed at the touch wiring layer. In the driver circuit layer, for example, in the source-drain metal layer, referring to fig. 9, 10, 11, and 12, the display panel is further provided with an auxiliary pad C02 overlapping the bonding pad C in the bonding region B1, and the auxiliary pad C02 is disposed in the same layer as the second power supply bus LVSS and the first power supply bus LVDD and is connected to the bonding pad C through a via. Thus, the surfaces of the bonding pads C can be ensured to be at the same height, and the bonding with an external circuit is utilized. The touch trace L1, the reference voltage trace L2, and the shielding trace L3 are disposed on the same layer as and connected to the bonding pad C. Second power supply bus line LVSS is connected to auxiliary pad C02, and first power supply bus line LVDD is connected to auxiliary pad C02. In one embodiment of the present disclosure, the second power supply pad includes a plurality of binding sub-pads C01, and the auxiliary pads C02 to which the binding sub-pads C01 are connected to each other. The first power supply pad includes a plurality of binding sub-pads C01, and the auxiliary pads C02 to which the binding sub-pads C01 are connected to each other.

Embodiments of the present disclosure also provide a display device including any one of the display panels described in the above display panel embodiments. The display device may be a smartphone, tablet, or other type of display device. Since the display device has any one of the display panels described in the above display panel embodiments, the same advantages are achieved, and the details of the disclosure are not repeated herein.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A display panel comprises a substrate base plate, a driving circuit layer, a pixel layer and a touch functional layer which are sequentially stacked;

2. The display panel of claim 1, wherein the width of the reference voltage trace is greater than the width of the touch trace.

3. The display panel of claim 2, wherein the peripheral region comprises a bonding region; in the binding region, the display panel is provided with a plurality of binding sub-pads;

4. The display panel of claim 1, wherein the reference voltage trace includes a main reference voltage sub-trace and at least one auxiliary reference voltage sub-trace disposed alongside the main reference voltage sub-trace; both ends of any one of the auxiliary reference voltage sub-wirings are connected to the main reference voltage sub-wiring.

5. The display panel of claim 4, wherein the main reference voltage sub-trace and the auxiliary reference voltage sub-trace have the same width and are equal to the width of the touch trace.

6. The display panel according to claim 1, wherein the touch routing layer is further provided with two shielding traces in a peripheral region of the display panel; each touch wire is positioned between two shielding wires, and any one shielding wire is positioned between the reference voltage wire and the touch wire;

7. The display panel of claim 6, wherein the width of the shielding trace is greater than the width of the touch trace.

8. The display panel of claim 7, wherein the peripheral region comprises a bonding region; in the binding region, the display panel is provided with a plurality of binding sub-pads;

9. The display panel according to claim 1, wherein the pixel layer is provided with a common electrode; the driving circuit layer is provided with a second power supply bus in the peripheral area of the display panel; the second power supply bus is used for loading a second power supply voltage to the common electrode;

10. The display panel of claim 9, wherein in the bonding region, the display panel is provided with a plurality of bonding sub-pads arranged in a line at equal intervals; any one of the bonding pads comprises at least one of the bonding sub-pads;

11. A display device comprising the display panel according to any one of claims 1 to 10.