CN113157079A

CN113157079A - Method and device for controlling processor and processor thereof

Info

Publication number: CN113157079A
Application number: CN202010014945.4A
Authority: CN
Inventors: 不公告发明人
Original assignee: Shanghai Cambricon Information Technology Co Ltd
Current assignee: Shanghai Cambricon Information Technology Co Ltd
Priority date: 2020-01-07
Filing date: 2020-01-07
Publication date: 2021-07-23

Abstract

The disclosure discloses a method for controlling a processor, an integrated circuit device and a corresponding processor thereof. Wherein the processor may be included in a processing device of a combined processing device that may also include a universal interconnect interface and other processing devices. The processing device interacts with other processing devices to jointly complete the calculation operation designated by the user. The combined processing device may further comprise a storage device, which is connected with the processing device and the other processing device, respectively, for storing data of the processing device and the other processing device. The scheme disclosed by the invention can evaluate the power consumption of the processing device and adjust the processing circuit with high power consumption overhead, thereby improving the performance of the whole system.

Description

Method and device for controlling processor and processor thereof

Technical Field

The present disclosure relates generally to the field of processors. More particularly, the present disclosure relates to a method for controlling a processor, an integrated circuit device and a corresponding processor thereof.

Background

The board card currently containing the arithmetic device may have a plurality of chips, and each chip may contain a plurality of computing core clusters. When the power consumption of the board card is controlled, the actual value of the power consumption of the board card is usually collected and observed, and the clock frequency of the board card is not reduced until the power consumption value exceeds a set threshold value. This passive tuning approach can result in a system that is too slow to respond to the demands for reduced overall board power consumption. In addition, although the power consumption of the whole board can be reduced by reducing the clock frequency of the board, the frequency of each computing core cluster in the board is also reduced, and particularly the computing core cluster with low power consumption overhead is reduced. Furthermore, such a way of reducing power consumption uniformly by the whole board also causes performance degradation of the scalar calculation circuit, the vector calculation circuit, and the input/output circuit corresponding to the same calculation core cluster, which is not favorable for virtualization of system devices.

Disclosure of Invention

To address at least the problems described in the background section above, the present disclosure provides the following technical solutions in one or more aspects.

In one aspect, the present disclosure proposes a processor comprising: a plurality of processing circuits, wherein each processing circuit is configured to perform an arithmetic operation; a plurality of clocked circuits, wherein each clocked circuit is connected to a corresponding one or more of the plurality of processing circuits and is configured to adjust a clock signal of the connected processing circuit; and a control circuit configured to operate some or all of the plurality of clocked circuits according to an instruction so as to instruct the operated clocked circuits to perform the adjustment on the clock signal of the processing circuit connected thereto.

In another aspect, the present disclosure also discloses an integrated circuit device comprising the aforementioned processor.

In yet another aspect, the present disclosure further discloses a method for controlling a processor, wherein the processor comprises a plurality of processing circuits, a plurality of clocked circuits, and a control circuit, wherein the processing circuits are configured to perform arithmetic operations, and each clocked circuit is connected with a corresponding one or more processing circuits, the method comprising: instructing the control circuit to control part or all of the plurality of time control circuits according to the instruction; and in response to manipulation by the control circuit, instructing the manipulated timing circuit to adjust a clock signal of a processing circuit connected thereto.

By using the method for controlling the processor, the integrated circuit device and the processor thereof provided by the disclosure, the power consumption of the whole board is optimally adjusted in an active frequency modulation mode, so that the over-high power consumption of the whole board can be avoided, and the influence on the performances of other computing core clusters with low power consumption overhead and scalar quantity, vector computing circuits and input/output circuits in the same computing core cluster can be avoided.

Drawings

The above-described features of the present invention can be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The drawings in the following description are merely exemplary embodiments of the disclosure and other drawings may be derived by those skilled in the art without inventive effort, wherein:

FIG. 1 is a block diagram illustrating a processor according to an embodiment of the present disclosure;

FIG. 2 is a flow chart illustrating a method for controlling a processor according to an embodiment of the present disclosure;

FIG. 3 is a detailed flow chart illustrating a method for controlling a processor according to an embodiment of the present disclosure;

FIG. 4 is a timing diagram illustrating the manipulation of clock signals according to an embodiment of the present disclosure;

FIG. 5 is a simplified flow diagram illustrating a method of controlling a processor according to an embodiment of the present disclosure;

FIG. 6 is a detailed flow chart illustrating a method of controlling a processor according to an embodiment of the present disclosure;

FIG. 7 is a block diagram illustrating a processor according to an embodiment of the present disclosure;

FIG. 8 is a block diagram illustrating a combined treatment device according to an embodiment of the present disclosure; and

fig. 9 is a schematic diagram illustrating a structure of a board according to an embodiment of the disclosure.

Detailed Description

The technical scheme of the disclosure provides a method for controlling a processor, an integrated circuit device and a corresponding processor. In particular, the processor comprises a number of processing circuits, each for performing an arithmetic operation, a timing circuit and a control circuit. The method is different from the scheme of reducing the power consumption of the processor by adopting a passive frequency modulation mode in the prior art. The method adopts an active frequency reduction mode, only aims at a processing circuit with high power consumption to execute frequency reduction, shortens the response time of a system, and does not influence the performances of other processors or scalar quantity calculating circuits, vector quantity calculating circuits and input and output circuits in the same processor.

The technical solution of the present disclosure and its various embodiments will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the present disclosure sets forth numerous specific details in order to provide a thorough understanding of the described embodiments of the present disclosure. However, it will be apparent to one of ordinary skill in the art having had the benefit of the present disclosure that the various embodiments described in the present disclosure may be practiced without the specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to unnecessarily obscure the embodiments described in this disclosure. Moreover, this description is not to be taken as limiting the scope of the embodiments described in this disclosure.

Fig. 1 is a schematic diagram illustrating a processor 100 according to an embodiment of the present disclosure. As shown in fig. 1, the processor may include, among other things, a plurality of processing circuits 101, each for performing arithmetic operations, such as operations relating to the field of artificial intelligence. The processor further comprises a plurality of clocked circuits 102, each clocked circuit being connected to a corresponding one or more of the plurality of processing circuits and configured to adjust a clock signal of the connected processing circuit to perform a corresponding adjustment to the power consumption of the processor. According to aspects of the present disclosure, the processing circuit herein may be a compute core including circuits such as scalar compute circuits, vector compute circuits, etc., and a plurality of processing circuits may form a compute core cluster.

Further, the processor further comprises a control circuit 103 configured to operate some or all of the plurality of clocked circuits according to the instruction, so as to instruct the operated clocked circuits to adjust the clock signal of the processing circuit connected thereto. The instructions herein may be obtained in a variety of ways depending on the implementation scenario. For example, the instruction may be an instruction received from an external input to the processor. For another example, the instruction may be an instruction generated by the processor according to one or more of an operation mode, a data type, and an operation mode to be performed. Additionally, the instructions may also be instructions generated based on a current workload of the processor.

In one embodiment, in adjusting the clock signal of the connected processing circuit, the clocked circuit is configured to lower or raise the frequency of the clock signal of the processing circuit in accordance with manipulation of the control circuit. For example, the control circuit may operate the timing circuit to remove at least one clock edge signal from the clock signals of one or more processing circuits connected thereto to reduce the frequency of the clock signals. Conversely, the control circuit may also operate the timing circuit to recover the clock edge signal cancelled by the one or more processing circuits connected thereto to increase the frequency of the clock signal. Examples of clock edge signals and details thereof will be described later in connection with fig. 4.

In the operation of eliminating at least one clock edge signal in the clock signal to reduce the frequency of the clock signal, the situation that the noise is too large due to the switching of a plurality of processing circuits from full load to idle or from high load to low load can be avoided. Here, the ranges of the high load and the low load may be determined by combining the measured result and the empirical value, for example, according to a specific application scenario. In one embodiment, each of the clocked circuits is configured to enable the clock edge signal cancelled by the clocked circuit to be non-overlapped or slightly overlapped with the clock edge signal cancelled by the other clocked circuit under the control of the control circuit. Further, the non-overlapping or less-overlapping condition may include the eliminated clock edge signals being staggered at predetermined intervals from the eliminated clock edge signals of other clocked circuits.

In one or more embodiments, the processor of the present disclosure may further include a mode circuit 104 configured to associate each of a plurality of predetermined clock edge intervals with a cancellation mode that cancels the clock edge signal. Thus, the mode circuit may include multiple cancellation modes. In some application scenarios, these cancellation modes may be determined based on empirical values and preconfigured in the mode circuit. As an example of implementation, it is assumed that the mode circuit may be configured with five cancellation modes, "1", "7/8", "3/4", "1/2", and "1/4", respectively, where each cancellation mode represents a mode in which the clocked circuit performs clock signal adjustment. Specifically, a first cancellation mode "1" indicates that the clock edge signal does not need to be cancelled; a second elimination pattern "7/8" indicates elimination of one clock edge signal in eight consecutive clock edge signals; a third elimination pattern "3/4" indicates elimination of one clock edge signal in four consecutive clock edge signals; a fourth elimination pattern "1/2" indicates elimination of one clock edge signal in two consecutive clock edge signals; and a fifth elimination pattern "1/4" indicates elimination of three clock edge signals in a succession of four clock edge signals.

In some application scenarios, the control circuit may query the mode circuit for a corresponding cancellation mode according to the instruction to determine whether to instruct the clocked circuit to operate in the cancellation mode. Further, the control circuit may also compare the acquired cancellation pattern with the current cancellation pattern of the clocked circuit to determine if the two are the same. When the two are determined to be different, the control circuit can instruct the time control circuit to change the current elimination mode to the obtained elimination mode so as to correspondingly adjust the clock signal of the processing circuit connected with the time control circuit; conversely, when the two are the same, the control circuit may instruct the clocked circuit to remain in the current cancellation mode. In some embodiments, the control circuit may be further configured to perform a synchronization operation on the manipulated plurality of processing circuits before a corresponding adjustment of the clock signals of the plurality of processing circuits is made. Further, in the synchronous operation, the control circuit may also determine whether the plurality of processing circuits are in an idle state. When, in response to determining that a plurality of processing circuits are in the idle state, the control circuit may instruct a corresponding plurality of clocked circuits to make respective adjustments to the clock signals of the plurality of processing circuits, e.g., to eliminate or recover certain clock edge signals, in order to make respective adjustments to the power consumption of the processor.

The structure of a processor in which the technical solution of the present disclosure can be implemented is described above with reference to fig. 1. Based on the above description, those skilled in the art will appreciate that the processor shown in fig. 1 may also be implemented in an integrated circuit device or a board. Thus, the present disclosure also contemplates, in effect, an integrated circuit device or board that includes one or more of the aforementioned processors. In addition, it is noted that the above description of processor structures and arrangements is illustrative and not restrictive, and that appropriate modifications may be made in the structures and arrangements shown by those skilled in the art without departing from the spirit and scope of the disclosed aspects.

FIG. 2 is a flow chart illustrating a method 200 for controlling a processor according to an embodiment of the present disclosure. Here, the processor controlled by the method 200 may be the processor described in connection with fig. 1, which again comprises a plurality of processing circuits, a plurality of clocked circuits and control circuits, and optionally also mode circuits. In view of this, the description of the processor in fig. 1 also applies to the processor controlled by the method 200, and thus is not repeated.

As shown in fig. 2, at step 201, the method 200 instructs the control circuit to operate some or all of the plurality of clocked circuits according to the instruction. The instructions described herein are identical in nature to the instructions described in connection with FIG. 1 and may have different origins. For example, the received instruction may be an input instruction from outside the processor. As another example, the received instructions may also be instructions generated based on the current workload of the processor. In one embodiment, the received instruction may be generated by the processor according to one or more of an operation mode to be performed, a data type (e.g., integer, fixed-point, or floating-point), a work mode (e.g., single-core, dual-core, or quad-core). For example, the aforementioned operation mode may be an operation mode configured by at least one or more of one or more multipliers, one or more adders, an addition tree composed of adders, a scalar processing circuit, a vector processing circuit, an input-output circuit, and the like.

Next, at step 202, the method 200 responds to the manipulation of the control circuit, instructing the manipulated clocked circuit to adjust the clock signal of the processing circuit connected thereto, thereby enabling control of power consumption.

Although not shown in fig. 2, as previously described, adjusting the clock signal includes lowering or raising the frequency of the clock signal of the processing circuit in accordance with manipulation of the control circuit. Specifically, the frequency of the clock signal may be reduced by eliminating at least one clock edge signal in the clock signal; alternatively, the clock edge signal that is eliminated is recovered to raise the frequency of the clock signal. In addition, in the process of eliminating clock edges, the clock edge signals eliminated by the controlled time control circuit can be instructed not to overlap or slightly overlap with the clock edge signals eliminated by other time control circuits, for example, the eliminated clock edge signals can be staggered at a predetermined interval in terms of time.

The method for controlling the processor is briefly described above in connection with fig. 2 and is described in further detail below in connection with fig. 3.

FIG. 3 is a detailed flow chart illustrating a method 300 for controlling a processor according to an embodiment of the present disclosure. Those skilled in the art will appreciate from the following description that fig. 3 is a further refinement of the method of controlling a processor shown in fig. 2, and that the description with respect to fig. 2 applies equally to that shown in fig. 3.

As shown in FIG. 3, at step 301, method 300 fetches an instruction. The instructions may be received from an instruction input external to the processor, the same or similar to that described above in connection with fig. 1-2. For example, the externally input instructions may be software outputs originating from different levels. Additionally, the instructions may also be instructions generated based on a current workload or operating mode of the processor. When generating the above instructions according to the operating mode of the processor, different operating modes of the processor may correspond to different numbers of processor cores (e.g., the aforementioned dual core or quad core). Based on these operating modes, the processor may generate associated instructions to adjust its clock signal accordingly.

The method 300 then proceeds to

steps

302 and 303, respectively. Specifically, at step 302, the method 300 causes the control circuit to query the mode circuit for a corresponding cancellation mode in accordance with the input instructions to determine whether the clocked circuit is instructed to operate in the cancellation mode. Here, the mode circuit is the same as the mode circuit shown in fig. 1, and may be configured to associate each of a plurality of predetermined intervals with a corresponding one of a plurality of cancellation modes that cancel the clock edge signal.

At step 303, method 300 causes the control circuit to query a portion of or a plurality of clocked circuits connected to the one or more processing circuits for a current existing cancellation mode. Next, at step 304, the method 300 causes the control circuit to compare the cancellation pattern obtained from the pattern circuit with the current cancellation pattern of the clocked circuit to determine if the two are the same. When the two are the same, the control circuit instructs the clocked circuit to remain in the current cancellation mode and flow may return to step 301 to begin operation to re-fetch the instruction. However, when it is determined at step 304 that the two are different, the flow advances to step 305. Here, the method 300 causes the control circuit to perform a pre-operation before adjusting the clock signal of the processing circuit according to the obtained cancellation mode. For example, the control circuit may perform a synchronization operation on a plurality of manipulated processing circuits that require adjustment before a corresponding adjustment of the clock signals of the plurality of processing circuits is performed. Additionally or alternatively, in the synchronous operation, the control circuit may determine whether the plurality of processing circuits are in an idle state. For ease of understanding, assuming that there are 4 clocked circuits that need to adjust the clock signal of the processing circuit connected to it, the control circuit may perform synchronization on the 4 clock signals of the processing circuit at the first clock edge signal, i.e. perform adjustment of the 4 clock signals only after determining that the processing circuit is in an idle state. The advantage of introducing idle detection here is that the processing circuit does not work with arithmetic at this time, and thus the power consumption overhead is low. Further, at this time, the noise introduced when the timing circuit performs the clock signal adjustment is relatively small.

After completing the exemplary pre-operations described above, flow proceeds to step 306 where the method 300 causes the control circuitry to instruct the clocked circuitry to make corresponding adjustments to the clock signal of the processing circuitry to which it is connected. Specifically, the control circuit instructs the timing circuit to lower or raise the frequency of the clock signal of the processing circuit connected thereto, according to the elimination pattern obtained in the pattern circuit. For example, the control circuit may instruct the clocked circuit to perform a blanking of at least one clock edge signal of the clock signal to reduce the frequency of the clock signal. For example, when the obtained cancellation pattern is "3/4" as described earlier, it indicates that the clocked circuit will lower the frequency of the clock signal of the processing circuit connected thereto. To this end, the control circuit may instruct the timing circuit to remove one clock edge signal from four consecutive clock edge signals of the processing circuit. Unlike the aforementioned downconversion, the control circuit may also instruct the clocked circuit to perform a recovery of the cancelled clock edge signal to increase the frequency of the clock signal.

In one implementation scenario, assuming that the cancellation pattern obtained by the control circuit from the pattern circuit is "7/8" and the cancellation pattern in the currently clocked circuit is "1", it may be determined that the two results are different by comparing the cancellation patterns obtained by the control circuit from the pattern circuit and the clocked circuit, respectively. The control circuit may now instruct the clocked circuit to change the current cancellation mode "1" to the obtained cancellation mode "7/8". Based on this obtained cancellation pattern, the clocked circuit will reduce the clock signal frequency of the processing circuit. In particular, the clocked circuit may perform the elimination of one clock edge signal among eight consecutive clock edge signals to reduce the clock signal frequency of the processing circuit.

In another implementation scenario, assuming that the cancellation pattern in the acquired mode circuit is "1" and the cancellation pattern in the currently clocked circuit is "7/8", it may be determined that the two results are different by comparing the cancellation patterns obtained by the control circuit from the mode circuit and the clocked circuit, respectively. The control circuit may now instruct the clocked circuit to change the current cancellation mode "7/8" to the resulting cancellation mode "1". Based on the obtained cancellation pattern, the clocked circuit may raise the clock signal frequency of the processing circuit. In particular, the clocked circuit may perform recovery of the one clock edge signal that was eliminated to raise the clock signal frequency of the processing circuit.

As described above, in the clock signal cancellation performed by the clock circuit, the control circuit instructs the clock signal cancelled by the clock circuit to be non-overlapped or less overlapped with the clock edge signals cancelled by the other clock circuits, for example, to be arranged alternately at predetermined intervals. Therefore, through the crossing in time, the problem that all processing circuits needing to adjust the frequency of the clock signal are switched from full load to no load or high load to low load at the same time to cause high noise can be avoided.

Alternatively, when the input instruction is an instruction input externally from the processor, the control circuit may query the mode circuit to obtain a corresponding cancellation mode at step 302, and thereafter the flow may also proceed directly to step 305, i.e., the control circuit performs pre-processing before adjusting the clock signal of the processing circuit according to the obtained cancellation mode. Next, at step 306, the control circuitry will instruct the timing circuitry to make corresponding adjustments to the clock signal of the processing circuitry connected thereto in accordance with the cancellation pattern obtained at step 302. Alternatively, step 306 may be performed directly after completion of step 302.

FIG. 4 is a timing diagram illustrating the manipulation of clock signals according to an embodiment of the disclosure. The clock signals 0, 1, 2 and 3 shown, four clock signals (each comprising a respective exemplary clock edge signal 1-6) may be the clock signals of the processing circuits described above in connection with fig. 1-3, and thus may correspond to clocked

circuits

0, 1, 2 and 3, respectively. As can be seen from fig. 4, the current cancellation mode is the aforementioned "3/4", i.e., one clock edge signal is cancelled out of four consecutive clock edge signals. The operation of the present disclosure will be described below based on the cancellation mode.

First, the control circuit instructs the way in which the clocked circuit performs clock signal adjustment, based on the acquired cancellation pattern "3/4". Before the adjustment operation is performed, preprocessing of idle detection of a plurality of processing circuits may be performed as necessary. After the preprocessing is performed, the clock signal of the processing circuit connected thereto is subjected to a clock edge signal elimination operation in an elimination mode "3/4" by the clocked circuit (the eliminated clock edge signal is shown in the figure by a dotted line).

Specifically, the control circuit instructs the clocked circuit 0 to clock signal 0 to remove one clock edge signal after every third consecutive clock signal, starting with the second clock edge signal 401 (i.e., clock edge signal 2), according to the removal pattern "3/4" described above. Next, the clocked circuit 1 performs an operation of removing one clock edge signal for the clock signal 1 from the third clock edge signal 403 (i.e., the clock edge signal 3). Similarly, the clocked circuit 2 performs an operation of eliminating one clock edge signal for the clock signal 2 starting from the fourth clock edge signal 404 (i.e., clock edge signal 4), and the clocked circuit 3 for the clock signal 3 starting from the fifth clock edge signal 405 (i.e., clock edge signal 5). When each of the four clock signals completes one clock edge signal cancellation, it is said that one cancellation cycle is completed.

After the above first erase cycle is performed, the next erase cycle may be performed. To do so, the control circuit instructs the timing circuit 0 to continue to perform the operation of clock signal 0 from the sixth clock edge signal 402 (i.e., clock edge signal 6) to remove the next clock edge signal. By analogy, subsequent cancellation operations will continue to be performed sequentially by the sequence number of the clock signal. The cancellation operation will continue until the cancellation operation in the current cancellation mode will stop when the control circuit receives a new instruction and the cancellation mode obtained from the mode circuit is different from the current cancellation mode of the clocked circuit. Then, the control circuit continues to perform the erasing operation in the new erasing mode according to the newly obtained erasing mode.

It should be understood that the above description of the clock signal adjustment mode in fig. 4 is merely exemplary and not limiting, and that one skilled in the art can vary the number of clock signals in fig. 4 and their cancellation modes depending on the number of processing circuits under the teachings of the present disclosure.

FIG. 5 is a simplified flow diagram illustrating a method 500 of controlling a processor according to an embodiment of the present disclosure. As will be appreciated by those skilled in the art, the processor referred to in fig. 5 may be the processor described in connection with fig. 1 and comprise a plurality of clocked circuits and one or more processing circuits connected thereto. Thus, the description made with respect to the processor of FIG. 1 applies equally to the processor involved in method 500.

As shown in FIG. 5, at step 501, method 500 obtains an instruction on a processor to adjust power of the processor. In one embodiment, the processor may include one or more processing circuits, such that fetching the instruction includes fetching an instruction on the processor to adjust power to the one or more processing circuits. According to aspects of the present disclosure, the fetched instructions may be generated in a variety of ways. For example, the instructions are generated according to one or more of an operation mode, a data type and an operation mode to be executed by the processor. As another example, instructions may be generated based on a current workload of a processor. In some embodiments, the instruction may also be a microinstruction or a micro-operation, which may be a control signal or a finer-grained instruction or operation parsed from the instruction. In other embodiments, the fetched instructions may be program instructions received from within or outside the processor, or machine instructions formed by compiling the program instructions.

After receiving the instructions described above, at step 502, method 500 adjusts the power of the processor based on the instructions.

In some embodiments, when the processor includes a plurality of clocked circuits, each clocked circuit being coupled to one or more of the plurality of processing circuits, some or all of the plurality of clocked circuits may be manipulated according to instructions to instruct the clocked circuits to adjust the power of the one or more processing circuits coupled thereto. In one application scenario, adjusting the power of one or more processing circuits may include adjusting a clock signal of a connected processing circuit. In one embodiment, the aforementioned adjusting may include eliminating at least one clock edge signal of the processing circuit to reduce power of the processing circuit; or recovering the at least one clock edge signal that was removed to power up the processing circuit.

Based on the above description, those skilled in the art can understand that the power adjustment for the processing circuit in the method 500 can be performed in the same manner as described above with reference to fig. 1-4, and therefore the operations described above with respect to the clock edge adjustment are also applicable to the operations herein, and thus will not be described in detail.

FIG. 6 is a detailed flow chart illustrating a method 600 of controlling a processor according to an embodiment of the present disclosure. Those skilled in the art will appreciate from the following description that the method flow of fig. 6 is a further refinement of what is shown in fig. 5. Therefore, the technical description about fig. 5 is also equally applicable to what is shown in fig. 6.

As shown in FIG. 6, the method 600 performs one or more of

steps

601 and 604, respectively, to obtain instructions for adjusting processor power. Those skilled in the art will appreciate that the steps herein are not limited by the numbering order of the steps described, and that other orders may be used.

Specifically, when step 601 is performed, the method 600 generates instructions according to one or more of the operational mode, data type, and operational mode to be performed. In one embodiment, the operation mode may be an operation mode formed by at least one or more of one or more multipliers, one or more adders, an addition tree composed of adders, a scalar processing circuit, a vector processing circuit, an input-output circuit, and the like participating in an operation. In another embodiment, the data types include multiple data types, such as integer 16-bit data (denoted as int16), fixed-point 8-bit data (denoted as fix8), floating-point 16-bit data (denoted as float16), or floating-point 32-bit data (denoted as float32), among others.

At step 602, the method 600 may generate an instruction according to a current workload of a processor. At step 603, the method 600 may receive a program instruction from outside the processor or a machine instruction formed by mutating the program instruction. In parallel, at step 604, the method 600 may receive a micro-instruction or micro-operation instruction, which may be a control signal or a finer grained instruction or operation parsed from the instruction.

After performing any of the

above steps

601, 602, 603, and 604, the method 600 proceeds to step 605 where the method 600 may select one of a plurality of cancellation modes based on the instruction, such as by the aforementioned mode circuitry. After selecting one of the cancellation modes, at step 606, method 600 may determine whether the selected cancellation mode is the same as the current cancellation mode of the processing circuit. When they are not the same, then method 600 instructs the timing circuit to change the current cancellation mode to the selected cancellation mode, for which steps 607 and 608 will be performed; otherwise, when the two are the same, the clocked circuit is instructed to remain in the current cancellation mode and the flow returns to step 605.

In step 607, the method 600 performs a synchronization operation on the plurality of processing circuits according to the instruction to determine whether the plurality of processing circuits are in an idle state, i.e., the optional preprocessing operation described above in connection with fig. 3. Next, when it is determined that the plurality of processing circuits are in an idle state, at step 608, method 600 instructs the corresponding plurality of clocked circuits to make respective adjustments to the clock signals of the plurality of processing circuits. For example, at least one clock edge signal of the processing circuit is eliminated to reduce power of the processing circuit; alternatively, the eliminated at least one clock edge signal is recovered to power up the processing circuitry. For clock edge elimination operations, the present disclosure proposes that the clock edge signal eliminated by each clocked circuit is non-overlapping or less overlapping in time with the clock edge signals eliminated by the other clocked circuits. Further, in the non-overlapping or less-overlapping scenario, the present disclosure also proposes that the clock edge signals to be eliminated and the clock edge signals to be eliminated by other timing control circuits may be arranged in a staggered manner at predetermined intervals. In addition, in some implementation scenarios, step 607 may not be executed, and step 608 may also be directly executed.

FIG. 7 is a block diagram illustrating a processor according to an embodiment of the present disclosure. It will be appreciated that the processor described herein may perform the embodiments described above in connection with fig. 5-6, and that the technical details described in relation to fig. 5-6 also apply to the description of fig. 7.

As shown in fig. 7, the processor of the present disclosure may generally include an instruction fetch circuit 702 and an instruction execution circuit 704. In one or more embodiments, instruction fetch circuitry 702 may be configured to fetch instructions for adjusting the power of a processor. Further, when the processor includes one or more processing circuits, the instruction fetch circuit 702 may be configured to fetch, on the processor, instructions for adjusting power of the one or more processing circuits.

In one or more embodiments, the instruction execution circuitry 704 may be configured to adjust the power of the processor based on the instruction. In particular, when the processor further comprises a plurality of clocked circuits, wherein each clocked circuit is connected to one or more of the plurality of processing circuits, the instruction execution circuit 704 may be configured to manipulate some or all of the plurality of clocked circuits according to the instruction to instruct the clocked circuits to adjust the power of the one or more processing circuits connected thereto.

Based on the above description in conjunction with fig. 7, those skilled in the art will also appreciate that the processor shown in fig. 7 may also be implemented in an integrated circuit device. Accordingly, the present disclosure also discloses an integrated circuit device including the aforementioned processor.

Fig. 8 is a block diagram illustrating a combined processing device 800 according to an embodiment of the present disclosure. As shown, the combined processing device 800 includes a processing device 802, which may include the aforementioned processor of the present disclosure and may be configured to perform the aforementioned control method described in conjunction with the drawings. In one or more embodiments, the processing device may also be the aforementioned chip, integrated circuit device. In addition, the combined processing device includes a general interconnect interface 804 and other processing devices 806. The processing device 802 according to the present disclosure may interact with other processing devices 806 via the universal interconnect interface 804 to collectively perform user-specified operations.

According to aspects of the present disclosure, the other processing devices may include one or more types of general and/or special purpose processors such as a central processing unit ("CPU"), a graphics processing unit ("GPU"), an artificial intelligence processor, etc., and the number thereof may be determined not by limitation but by actual needs. In one or more embodiments, the other processing device can be used as an interface of the processing device (which can be embodied as an artificial intelligence-related computing device) of the present disclosure and external data and control, and can perform basic control including, but not limited to, data handling, and completion of starting, stopping, and the like of the machine learning computing device; other processing devices may cooperate with the machine learning related computing device to perform computing tasks.

In accordance with aspects of the present disclosure, the universal interconnect interface may be used to transfer data and control instructions between a processing device and other processing devices. For example, the processing device may obtain required input data from other processing devices via the universal interconnect interface, and write the required input data into a storage device (or memory) on the processing device chip. Further, the processing device may obtain the control instruction from another processing device via the universal interconnection interface, and write the control instruction into the control cache on the processing device chip. Alternatively or optionally, the universal interconnect interface may also read data in a memory module of the processing device and transmit to other processing devices.

Optionally, the combined processing device may further comprise a storage device 808, which may be connected to the processing device and the other processing device, respectively. In one or more embodiments, the memory device may be used to store data for the processing device and the other processing devices, particularly data that may not be stored in its entirety within or in on-chip memory devices of the processing device or the other processing devices.

According to different application scenes, the combined processing device disclosed by the invention can be used as an SOC (system on chip) system of equipment such as a mobile phone, a robot, an unmanned aerial vehicle and video acquisition equipment, so that the core area of a control part is effectively reduced, the processing speed is increased, and the overall power consumption is reduced. In this case, the general interconnection interface of the combined processing apparatus is connected with some components of the device. Some components such as a camera, a display, a mouse, a keyboard, a network card, or a wifi interface.

In some embodiments, the present disclosure also discloses a chip comprising the above-described processing device or combined processing device. In other embodiments, the present disclosure also discloses a chip packaging structure, which includes the above chip.

In some embodiments, the disclosure also discloses a board card comprising the chip packaging structure. Referring to fig. 9, the aforementioned exemplary board is provided, and the board may include other accessories besides the chip 902, including but not limited to: a memory device 904, an interface device 906, and a control device 908.

The memory device is connected with the chip in the chip packaging structure through a bus and used for storing data. The memory device may include a plurality of sets of memory cells 910. Each group of the storage units is connected with the chip through a bus. It is understood that each group of the memory cells may be a ddr SDRAM ("Double Data Rate SDRAM").

DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM. In one embodiment, the memory device may include 4 groups of the memory cells. Each group of the memory cells may include a plurality of DDR4 particles (chips). In one embodiment, the chip may internally include 4 72-bit DDR4 controllers, and 64 bits of the 72-bit DDR4 controller are used for data transmission, and 8 bits are used for ECC check.

In one embodiment, each group of the memory cells includes a plurality of double rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice in one clock cycle. And a controller for controlling DDR is arranged in the chip and is used for controlling data transmission and data storage of each memory unit.

The interface device is electrically connected with a chip in the chip packaging structure. The interface means are used for enabling data transmission between the chip and an external device 912, such as a server or a computer. For example, in one embodiment, the interface device may be a standard PCIE interface. For example, the data to be processed is transmitted to the chip by the server through the standard PCIE interface, so as to implement data transfer. In another embodiment, the interface device may also be another interface, and the disclosure does not limit the concrete expression of the other interface, and the interface unit may implement the switching function. In addition, the calculation result of the chip is still transmitted back to an external device (e.g., a server) by the interface device.

The control device is electrically connected with the chip. The control device is used for monitoring the state of the chip. Specifically, the chip and the control device may be electrically connected through an SPI interface. The control device may include a single chip Microcomputer (MCU). In one or more embodiments, the chip may include a plurality of processing chips, a plurality of processing cores, or a plurality of processing circuits, which may carry a plurality of loads. Therefore, the chip can be in different working states such as multi-load and light load. The control device can realize the regulation and control of the working states of a plurality of processing chips, a plurality of processing and/or a plurality of processing circuits in the chip.

In some embodiments, the present disclosure also discloses an electronic device or apparatus, which includes the above board card. According to different application scenarios, the electronic device or apparatus may include a data processing apparatus, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a vehicle data recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, an earphone, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device. The vehicle comprises an airplane, a ship and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph.

It is noted that while for simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present disclosure is not limited by the order of acts, as some steps may, in accordance with the present disclosure, occur in other orders and concurrently. Further, those skilled in the art will also appreciate that the embodiments described in the specification are exemplary embodiments and that acts and modules referred to are not necessarily required by the disclosure.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some interfaces, and may be in an electrical, optical, acoustic, magnetic or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment. In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may be implemented in the form of a software program module.

The integrated units, if implemented in the form of software program modules and sold or used as stand-alone products, may be stored in a computer readable memory. With this understanding, when the technical solution of the present disclosure can be embodied in the form of a software product stored in a memory, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present disclosure. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

The foregoing may be better understood in light of the following clauses:

clause a1, a processor, comprising:

a plurality of processing circuits, wherein each processing circuit is configured to perform an arithmetic operation;

a plurality of clocked circuits, wherein each clocked circuit is connected to a corresponding one or more of the plurality of processing circuits and is configured to adjust a clock signal of the connected processing circuit; and

a control circuit configured to operate some or all of the plurality of clocked circuits according to an instruction so as to instruct the operated clocked circuits to perform the adjustment on the clock signal of the processing circuit connected thereto.

Clause a2, the processor of clause a1, wherein in adjusting the clock signal of connected processing circuitry, the clocked circuitry is configured to:

reducing the frequency of the clock signal of the processing circuit according to the manipulation of the control circuit; or

Raising the frequency of the clock signal of the processing circuit in accordance with manipulation of the control circuit.

Clause A3, the processor of clause a2, wherein in lowering or raising the frequency of the clock signal, the clocked circuit is configured to perform, in accordance with manipulation of the control circuit:

eliminating at least one clock edge signal in a clock signal to reduce the frequency of the clock signal; or

Recovering the clock edge signal that is cancelled to raise the frequency of the clock signal.

Clause a4, the processor of clause A3, wherein in cancelling at least one of the clock edge signals, each clocked circuit is configured under the control of the control circuit to have its cancelled clock edge signal non-overlapping or less overlapping with the clock edge signals cancelled by the other clocked circuits.

Clause a5, the processor of clause a4, wherein the eliminated clock edge signal being non-overlapping or less overlapping with the clock edge signals eliminated by the other timing circuits comprises the eliminated clock edge signal being staggered from the clock edge signals eliminated by the other timing circuits by a predetermined interval.

Clause a6, the processor of clause a5, further comprising:

a mode circuit configured to associate each of a plurality of the predetermined intervals with a cancellation mode that cancels a clock edge signal,

wherein the control circuit is further configured to query the mode circuit for a corresponding cancellation mode in accordance with the instruction to determine whether to instruct the clocked circuit to operate in the cancellation mode.

Clause a7, the processor of clause a6, wherein in determining whether the clocked circuit is indicated to operate in the cancellation mode, the control circuit is further configured to:

comparing the obtained cancellation pattern with a current cancellation pattern of the clocked circuit to determine if the two are the same; and

in response to the obtained cancellation mode being different from the current cancellation mode, instructing the clocked circuit to change the current cancellation mode to the obtained cancellation mode to make a corresponding adjustment to the clock signal of the processing circuit.

Clause A8, the processor of clause a7, wherein in response to the obtained cancellation mode being the same as the current cancellation mode, the control circuit is further configured to:

instructing the clocked circuit to remain in the current cancellation mode.

Clause a9, the processor of any one of clauses a1-A8, wherein in manipulating the portion or all of the plurality of clocked circuits in accordance with the instructions, the control circuit is further configured to:

and performing synchronous operation on the plurality of processing circuits under control before performing corresponding adjustment on the clock signals of the plurality of processing circuits.

Clause a10, the processor of clause a9, wherein in the synchronous operation, the control circuit is further configured to:

determining whether the plurality of processing circuits are in an idle state; and

in response to determining that a plurality of processing circuits are in the idle state, instructing a corresponding plurality of clocked circuits to make respective adjustments to clock signals of the plurality of processing circuits.

Clause a11, the processor of clause a10, wherein the instruction is an instruction to receive an external input from the processor.

Clause a12, the processor of clause a10, wherein the instruction is an instruction generated by the processor according to one or more of a mode of operation to be performed, a type of data, a mode of operation.

Clause a13, the processor of clause a10, wherein the instructions are instructions generated based on a current workload of the processor.

Clause a14, an integrated circuit device comprising the processor of any one of clauses a1-a 13.

Clause a15, a method for controlling a processor, wherein the processor includes a plurality of processing circuits, a plurality of clocked circuits, and a control circuit, wherein the processing circuits are configured to perform arithmetic operations, and each clocked circuit is connected with a corresponding one or more processing circuits, the method comprising:

instructing the control circuit to control part or all of the plurality of time control circuits according to the instruction; and

in response to a manipulation of the control circuit, the manipulated clocked circuit is instructed to adjust a clock signal of a processing circuit connected thereto.

Clause a16, the method of clause a15, wherein in adjusting the clock signal of connected processing circuits, the method further comprises instructing the clocked circuits to perform:

Clause a17, the method of clause a16, wherein in lowering or raising the frequency of the clock signal, the method further comprises instructing the clocked circuit to perform:

Clause a18, the method of clause a17, wherein in cancelling at least one of the clock edge signals, the method includes, in response to manipulation of the control circuit, instructing the manipulated clocked circuit to cancel the clock edge signal that does not overlap or that is less than the clock edge signal that is cancelled by the other clocked circuit.

Clause a19, the method of clause a18, wherein the eliminated clock edge signal being non-overlapping or less overlapping with the clock edge signals eliminated by other clocked circuitry comprises the eliminated clock edge signal being staggered from the clock edge signals eliminated by other clocked circuitry at predetermined intervals.

Clause a20, the method of clause a19, wherein the processor further comprises a mode circuit, the method further comprising:

instructing the mode circuit to associate each of a plurality of the predetermined intervals with a corresponding one of a plurality of cancellation modes that cancels the clock edge signal; and

instructing the control circuitry to query the mode circuitry for a corresponding cancellation mode in accordance with the instruction to determine whether to instruct the clocked circuitry to operate in the cancellation mode.

Clause a21, the method of clause a20, wherein in determining whether to instruct the clocked circuit to operate in the cancellation mode, the method further comprises instructing the control circuit to perform:

Clause a22, the method of clause a21, wherein in response to the obtained cancellation mode being the same as the current cancellation mode, the method further comprises instructing control circuitry to perform:

instructing the clocked circuit to remain in the current cancellation mode.

Clause a23, the method of any one of clauses a15-a22, wherein in manipulating the portion or all of the plurality of clocked circuits in accordance with the instruction, the method further comprises instructing the control circuit to perform:

Clause a24, the method of clause a23, wherein in the synchronizing operation, the control circuit is further instructed to perform:

Clause a25, the method of clause a24, wherein the instruction is an instruction received from an external input to the processor.

Clause a26, the method of clause a24, wherein the instruction is an instruction generated by the processor according to one or more of a mode of operation to be performed, a type of data, a mode of operation.

Clause a27, the method of clause a24, wherein the instructions are instructions generated based on a current workload of the processor.

It should be understood that the terms "first," "second," "third," and "fourth," etc. in the claims, description, and drawings of the present disclosure are used to distinguish between different objects and are not used to describe a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this disclosure refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

The foregoing detailed description of the embodiments of the present disclosure has been presented for purposes of illustration and description and is intended to be exemplary only and is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Meanwhile, a person skilled in the art should, according to the idea of the present disclosure, change or modify the embodiments and applications of the present disclosure. In view of the above, this description should not be taken as limiting the present disclosure.

Claims

1. A processor, comprising:

2. The processor of claim 1, wherein in adjusting the clock signal of the connected processing circuit, the clocked circuit is configured to:

3. The processor of claim 2, wherein in lowering or raising the frequency of the clock signal, the clocked circuit is configured to perform, in accordance with manipulation of the control circuit:

4. A processor according to claim 3, wherein in cancelling at least one of the clock edge signals, each clocked circuit is configured under the control of the control circuit to have its cancelled clock edge signal non-overlapping or less overlapping with the clock edge signals cancelled by the other clocked circuits.

5. The processor of claim 4, wherein the eliminated clock edge signal being non-overlapping or less overlapping with the eliminated clock edge signals of the other clocked circuits comprises the eliminated clock edge signal being staggered from the eliminated clock edge signals of the other clocked circuits by a predetermined interval.

6. The processor of claim 5, further comprising:

7. The processor of claim 6, wherein in determining whether to indicate that the clocked circuit is operating in the cancellation mode, the control circuit is further configured to:

8. The processor of claim 7, wherein in response to the obtained cancellation mode being the same as the current cancellation mode, the control circuitry is further configured to:

instructing the clocked circuit to remain in the current cancellation mode.

9. The processor of any one of claims 1-8, wherein in manipulating the portion or all of the plurality of clocked circuits according to the instructions, the control circuit is further configured to:

10. The processor of claim 9, wherein in the synchronous operation, the control circuit is further configured to:

in response to determining that the plurality of processing circuits are in the idle state, instructing the corresponding plurality of clocked circuits to make respective adjustments to the clock signals of the plurality of processing circuits.

11. The processor of claim 10, wherein the instruction is an instruction received from an external input to the processor.

12. The processor of claim 10, wherein the instruction is an instruction generated by the processor according to one or more of a mode of operation to be performed, a data type, a mode of operation.

13. The processor of claim 10, wherein the instructions are instructions generated based on a current workload of the processor.

14. An integrated circuit device comprising a processor according to any of claims 1-13.

15. A method for controlling a processor, wherein the processor comprises a plurality of processing circuits, a plurality of clocked circuits, and a control circuit, wherein the processing circuits are configured to perform arithmetic operations, and each clocked circuit is connected to a corresponding one or more processing circuits, the method comprising: