CN111400341B

CN111400341B - Scalar lookup instruction processing method and device and related product

Info

Publication number: CN111400341B
Application number: CN201910001865.2A
Authority: CN
Inventors: 不公告发明人
Original assignee: Shanghai Cambricon Information Technology Co Ltd
Current assignee: Shanghai Cambricon Information Technology Co Ltd
Priority date: 2019-01-02
Filing date: 2019-01-02
Publication date: 2022-12-09
Anticipated expiration: 2039-01-02
Also published as: CN111400341A

Abstract

The disclosure relates to an operation method, an operation device and a related product. The machine learning device comprises one or more instruction processing devices, is used for acquiring data to be operated and control information from other processing devices, executing specified machine learning operation and transmitting an execution result to other processing devices through an I/O interface; when the machine learning arithmetic device includes a plurality of instruction processing devices, the plurality of instruction processing devices can be connected to each other by a specific configuration to transfer data. The command processing devices are interconnected through a Peripheral Component Interface Express (PCIE) bus and transmit data; the plurality of instruction processing devices share the same control system or own control system and share a memory or own memory; the interconnection mode of the plurality of instruction processing devices is an arbitrary interconnection topology. The operation method, the operation device and the related products provided by the embodiment of the disclosure have the advantages of wide application range, high instruction processing efficiency and high instruction processing speed.

Description

Scalar lookup instruction processing method, device and related product

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a scalar lookup instruction processing method and apparatus, and a related product.

Background

With the continuous development of science and technology, machine learning, especially neural network algorithms, are more and more widely used. The method is well applied to the fields of image recognition, voice recognition, natural language processing and the like. However, as the complexity of neural network algorithms is higher and higher, the types and the number of involved data operations are increasing. In the related art, the efficiency and the speed of performing lookup operation on scalar data are low.

Disclosure of Invention

In view of the above, the present disclosure provides a scalar lookup instruction processing method, apparatus and related product to improve efficiency and speed of performing a lookup operation on a scalar.

According to a first aspect of the present disclosure, there is provided a scalar lookup instruction processing apparatus, the apparatus comprising:

the control module is used for analyzing the received scalar searching instruction, obtaining an operation code and an operation domain of the scalar searching instruction, and determining a scalar to be searched, a designated value, a designated sequence and a target address which are required by executing the scalar searching instruction according to the operation code and the operation domain;

the operation module is used for sequentially determining whether numerical values of a plurality of numbers to be searched, which represent the scalars to be searched, are equal to the specified values, determining the numbers to be searched, which are equal to the specified values and are sorted into the specified sorting, as target numbers, and storing storage addresses of the target numbers as search results into the target addresses, wherein the operation codes are used for indicating that the operation of the scalar search instruction on scalar data is search operation, and the operation domain comprises the scalar addresses to be searched and the target addresses.

According to a second aspect of the present disclosure, there is provided a machine learning arithmetic device, the device including:

one or more scalar quantity search instruction processing devices described in the first aspect above, configured to obtain data to be operated and control information from another processing device, execute a specified machine learning operation, and transmit an execution result to the other processing device through an I/O interface;

when the machine learning arithmetic device comprises a plurality of scalar search instruction processing devices, the scalar search instruction processing devices can be connected through a specific structure and transmit data;

the scalar searching instruction processing devices are interconnected through a PCIE bus which is a fast peripheral equipment interconnection bus and transmit data so as to support operation of machine learning in a larger scale; a plurality of scalar lookup instruction processing devices share the same control system or own respective control systems; the scalar search instruction processing devices share a memory or own respective memories; the interconnection mode of the scalar lookup instruction processing devices is any interconnection topology.

According to a third aspect of the present disclosure, there is provided a combined processing apparatus, the apparatus comprising:

the machine learning arithmetic device, the universal interconnect interface, and the other processing device according to the second aspect;

and the machine learning arithmetic device interacts with the other processing devices to jointly complete the calculation operation designated by the user.

According to a fourth aspect of the present disclosure, there is provided a machine learning chip including the machine learning network operation device of the second aspect or the combination processing device of the third aspect.

According to a fifth aspect of the present disclosure, there is provided a machine learning chip package structure, which includes the machine learning chip of the fourth aspect.

According to a sixth aspect of the present disclosure, a board card is provided, which includes the machine learning chip packaging structure of the fifth aspect.

According to a seventh aspect of the present disclosure, there is provided an electronic device, which includes the machine learning chip of the fourth aspect or the board of the sixth aspect.

According to an eighth aspect of the present disclosure, there is provided a scalar lookup instruction processing method applied to a scalar lookup instruction processing apparatus, the method including:

analyzing a received scalar searching instruction to obtain an operation code and an operation domain of the scalar searching instruction, and determining a scalar to be searched, a designated value, a designated sequence and a target address which are required by executing the scalar searching instruction according to the operation code and the operation domain;

sequentially determining whether the numerical values of a plurality of numbers to be checked representing the scalars to be searched are equal to the appointed value, determining the numbers to be checked which are equal to the appointed value and are ordered to be the appointed ordering as target numbers, storing the storage addresses of the target numbers as search results into the target addresses,

the operation code is used for indicating that the operation of the scalar lookup instruction on scalar data is a lookup operation, and the operation domain comprises the scalar address to be looked up and the target address.

In some embodiments, the electronic device comprises a data processing apparatus, a robot, a computer, a printer, a scanner, a tablet, a smart terminal, a cell phone, a tachograph, a navigator, a sensor, a camera, a server, a cloud server, a camera, a camcorder, a projector, a watch, a headset, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device.

In some embodiments, the vehicle comprises an aircraft, a ship, and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance instrument, a B ultrasonic instrument and/or an electrocardiograph.

The scalar search instruction processing method, the scalar search instruction processing device and the related product provided by the embodiment of the disclosure comprise a control module and an operation module. The control module is used for analyzing the received scalar searching instruction, obtaining an operation code and an operation domain of the scalar searching instruction, and determining a scalar to be searched, a designated value, a designated sequence and a target address which are required by the scalar searching instruction according to the operation code and the operation domain. The operation module is used for sequentially determining whether the numerical values of the plurality of numbers to be checked representing the scalars to be searched are equal to the designated values, determining the numbers to be checked which are equal to the designated values and are sorted into the designated sorting as target numbers, and storing the storage addresses of the target numbers as search results into the target addresses. The scalar search instruction processing method, the scalar search instruction processing device and the related products provided by the embodiment of the disclosure have the advantages of wide application range, high processing efficiency and high processing speed of the scalar search instruction.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1 shows a block diagram of a scalar lookup instruction processing apparatus according to an embodiment of the present disclosure.

FIG. 2 shows a block diagram of a scalar lookup instruction processing apparatus according to an embodiment of the present disclosure.

3 a-3 c show schematic diagrams of an application scenario of a scalar lookup instruction processing apparatus according to an embodiment of the present disclosure.

Fig. 4a, 4b show block diagrams of a combined processing device according to an embodiment of the present disclosure.

Fig. 5 shows a schematic structural diagram of a board card according to an embodiment of the present disclosure.

FIG. 6 illustrates a flow diagram of a method of scalar lookup instruction processing according to an embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.

FIG. 1 shows a block diagram of a scalar lookup instruction processing apparatus according to an embodiment of the present disclosure. As shown in fig. 1, the apparatus includes a control module 11 and an operation module 12.

The control module 11 is configured to parse the received scalar search instruction, obtain an operation code and an operation domain of the scalar search instruction, and determine, according to the operation code and the operation domain, a scalar to be searched, a designated value, a designated sequence, and a target address required for executing the scalar search instruction. The operation code is used for indicating the scalar searching instruction to perform searching operation on the data, and the operation domain comprises a scalar address to be searched and a target address.

And the operation module 12 is configured to sequentially determine whether the numerical values of the multiple numbers to be checked representing the scalars to be searched are equal to the designated values, determine the numbers to be checked that are equal to the designated values and are sorted into the designated sorting as the target numbers, and store the storage addresses of the target numbers as the search results into the target addresses.

In this embodiment, the scalar to be searched may be a string of binary, hexadecimal, etc. For example, the binary representation of the scalar 87 to be looked up is "01010111", and the plurality of numbers to be looked up of the scalar 87 to be looked up are "0", "1", and "1". The control module can obtain the scalar to be searched from the scalar address to be searched. The scalar address to be looked up may be the first address where the scalar to be looked up is stored, etc. The control module can obtain the scalar searching instruction and the scalar to be searched through a data input and output unit, and the data input and output unit can be one or more data I/O interfaces or I/O pins.

In this embodiment, the operation code may be a part of an instruction or a field (usually indicated by code) specified in the computer program to be executed, and is an instruction sequence number used to inform a device executing the instruction which instruction needs to be executed specifically. The operation domain may be a source of all data required for executing the corresponding instruction, including parameter data, scalars to be looked up, corresponding operation methods, or addresses storing the parameter data, scalars to be looked up, corresponding operation methods, and so on. For a scalar lookup instruction it must include an opcode and an operation domain, where the operation domain includes at least the scalar address to be looked up and the target address.

It should be understood that the instruction format of the scalar lookup instruction and the included opcode and operation domain may be set as desired by one skilled in the art, and the disclosure is not limited thereto.

In this embodiment, the apparatus may include one or more control modules and one or more operation modules, and the number of the control modules and the number of the operation modules may be set according to actual needs, which is not limited in this disclosure.

The scalar search instruction processing device provided by the embodiment of the disclosure comprises a control module and an operation module. The control module is used for analyzing the received scalar searching instruction, obtaining an operation code and an operation domain of the scalar searching instruction, and determining a scalar to be searched, a designated value, a designated sequence and a target address which are required by the execution of the scalar searching instruction according to the operation code and the operation domain. The operation module is used for sequentially determining whether the numerical values of the plurality of numbers to be checked representing the scalars to be searched are equal to the designated values, determining the numbers to be checked which are equal to the designated values and are sorted into the designated sorting as target numbers, and storing the storage addresses of the target numbers as search results into the target addresses. The scalar search instruction processing device provided by the embodiment of the disclosure has the advantages of wide application range, high processing efficiency and high processing speed of scalar search instructions.

In one possible implementation, the specifying the ordering may include at least one of: the sorting of the numbers to be checked is the nth number of the numbers to be checked which is equal to the specified value, and n is a positive integer which is greater than or equal to 1; the sorting of the numbers to be checked is the mth from the last of the numbers to be checked which is equal to the specified value, and m is a positive integer which is greater than or equal to 1. And m and n are less than or equal to the number of the numbers to be searched in the scalars to be searched.

In this implementation, the specified orderings of the reciprocal and the positive numbers may be distinguished by setting different expressions to "nth of the numbers to be examined ranked so as to be equal to the specified value", "mth of the numbers to be examined ranked so as to be equal to the specified value", and the like. The expression in the scalar lookup instruction of "the nth of the numbers to be looked at in the designated order as being equal to the designated value" may be set to "0n", and the expression in the scalar lookup instruction of "the mth of the numbers to be looked at in the designated order as being equal to the designated value" may be set to "m0". The expression of the specified ordering can be set by the person skilled in the art according to the actual need, and the present disclosure does not limit this.

In one possible implementation, the specified value may be a numerical value of 0, 1, 2, 3, etc.

For example, if the scalar to be looked up is a hexadecimal string, the specified values may be 0-9, A-F. If the scalar to be looked up is a binary string, the specified value may be 0 or 1. The target number found by the scalar lookup instruction may be the first 1, the last 1, etc. of the plurality of numbers to be looked up for the scalar.

In one possible implementation, the operation field may further include an input length. The control module 11 is further configured to obtain a scalar to be searched from the scalar address to be searched according to the input length.

In this implementation, the length of the scalar to be searched, which is obtained from the scalar address to be searched according to the input length, needs to be equal to the input length, or needs to be smaller than the input length.

In a possible implementation manner, when the input length is not included in the operation domain, the scalar to be searched may be obtained according to a preset default input length. And all data in the scalar address to be searched can be acquired as the scalar to be searched.

In one possible implementation, the operation domain may further include a width of a number to be looked up. The operation module 12 is further configured to determine a plurality of numbers to be looked up from the scalar to be looked up according to the widths of the numbers to be looked up.

In this implementation, when the width of the number to be looked up is included in the operation domain, a plurality of numbers to be looked up with the width of the number to be looked up may be determined from the scalars to be looked up.

In this implementation, when the operation domain does not include the width of the to-be-checked number (which may refer to that a position corresponding to the width of the to-be-checked number in the scalar search instruction is empty or the width of the to-be-checked number does not exist), or the width of the to-be-checked number is 1, the multiple to-be-checked numbers of the to-be-checked scalar are multiple characters in the character string. For example, the scalar n to be searched is "01010111", and a plurality of numbers to be searched of the scalar n to be searched are "0", "1", and "1" when the number to be searched is 1 in width.

In this implementation, when the operation domain includes the width of the number to be looked up, and the width of the number to be looked up is greater than 1, the number to be looked up of the scalar to be looked up is a plurality of binary number strings with the width of the number to be looked up, and each binary number string with the width of the number to be looked up represents one number to be looked up. For example, if the width of the to-be-searched number is 3, the to-be-searched scalar m is "101110100", and the plurality of to-be-searched numbers of the to-be-searched scalar m are "101", "110", and "100".

In one possible implementation, the operation domain may also include a specified value and a specified ordering. The control module 11 is further configured to determine a specified value and a specified rank according to the operation domain.

In this implementation, when the specified value and the specified ordering are included in the operation domain, the specified value and the specified ordering in the operation domain may be directly obtained.

In a possible implementation, the control module 11 is further configured to determine the specified value and the specified ordering according to the operation code. Wherein the opcode is further to indicate a specified value and a specified ordering of the scalar lookup instruction.

In this implementation, different opcodes may be set to represent different specified values and specified orderings. In particular, the width of the number to be looked up can also be determined from the operation code or the default width.

For example, the opcode "Find _ bfirst" may be set to Find the first 1 of the plurality of the numbers to be looked up for the scalar (the number to be looked up has a width of 1, a specified value of 1, and 1 st of the numbers to be looked up ordered to equal the specified value). The opcode "Find _ blast" is the last 1 in the plurality of numbers to be looked up to Find the scalar to be looked up (width of number to be looked up is 1, value designated is 1, ordering of number to be looked up is designated as the 1 st from the number to be looked up equal to the designated value). When the operation code is 'Find _ bfirst' and 'Find _ blast', the width of the number to be checked can be further determined to be 1 according to the operation code, and then a plurality of numbers to be checked with the width of 1 of the scalar to be searched can be obtained.

FIG. 2 shows a block diagram of a scalar lookup instruction processing apparatus according to an embodiment of the present disclosure. In a possible implementation manner, as shown in fig. 2, the operation module 12 may include at least one comparator 121, configured to compare the numerical values of the plurality of numbers to be checked with the specified value to obtain a comparison result, so as to determine whether the numerical value of the number to be checked is equal to the specified value according to the comparison result.

For example, taking the designated value "1" and the designated sequence as "1 st of the numbers to be looked up in the sequence equal to the designated value", the comparator may sequentially compare the numerical values of the plurality of numbers to be looked up of the scalar to be looked up with the designated value "1" to obtain the comparison result. And then the operation module can determine whether the numerical value of the number to be checked is equal to the specified value 1 according to the comparison result, determine the 1 st number to be checked in the number to be checked, which is the numerical value equal to the specified value 1 and is sequenced to be equal to the specified value, as the target number, and store the storage address of the target number as the search result into the target address. The number of comparators may be set according to the size of the data amount to be compared, the processing speed, efficiency of comparison, and the like, which is not limited by the present disclosure.

In one possible implementation, as shown in fig. 2, the apparatus may further include a storage module 13. The storage module 13 is used for storing scalars to be searched.

In this implementation, the storage module may include one or more of a memory, a cache, and a register, and the cache may include a scratch pad cache. The scalar to be searched may be stored in a memory, a cache and/or a register of the storage module as needed, which is not limited by this disclosure.

In a possible implementation manner, the apparatus may further include a direct memory access module for reading or storing data from the storage module.

In one possible implementation, as shown in fig. 2, the control module 11 may include an instruction storage sub-module 111, an instruction processing sub-module 112, and a queue storage sub-module 113.

The instruction storage submodule 111 is used to store scalar look-up instructions.

The instruction processing sub-module 112 is configured to parse the scalar lookup instruction to obtain an operation code and an operation domain of the scalar lookup instruction.

The queue storage submodule 113 is configured to store an instruction queue, where the instruction queue includes multiple instructions to be executed that are sequentially arranged according to an execution order, and the multiple instructions to be executed may include a scalar lookup instruction.

In this implementation manner, the execution order of the multiple instructions to be executed may be arranged according to the receiving time, priority level, and the like of the instructions to be executed to obtain an instruction queue, so that the multiple instructions to be executed are sequentially executed according to the instruction queue.

In one possible implementation, as shown in fig. 2, the control module 11 may further include a dependency processing sub-module 114.

The dependency relationship processing submodule 114 is configured to cache the first to-be-executed instruction in the instruction storage submodule 112 when it is determined that an association relationship exists between the first to-be-executed instruction in the plurality of to-be-executed instructions and a zeroth to-be-executed instruction before the first to-be-executed instruction, and extract the first to-be-executed instruction from the instruction storage submodule 112 and send the first to-be-executed instruction to the operation module 12 after the zeroth to-be-executed instruction is executed. The first to-be-executed instruction and the zeroth to-be-executed instruction are instructions in the plurality of to-be-executed instructions.

The method for determining the zero-th instruction to be executed before the first instruction to be executed has an incidence relation with the first instruction to be executed comprises the following steps: the first storage address interval for storing the data required by the first to-be-executed instruction and the zeroth storage address interval for storing the data required by the zeroth to-be-executed instruction have an overlapped area. Conversely, the first to-be-executed instruction and the zeroth to-be-executed instruction have no association relationship therebetween, and the first storage address interval and the zeroth storage address interval have no overlapping region.

By the method, according to the dependency relationship among the instructions to be executed, after the previous instruction to be executed is executed, the subsequent instruction to be executed is executed, and the accuracy of the operation result is ensured.

In one possible implementation, the instruction format of the scalar lookup instruction may be as shown in table 1 below, and the opcode and the location of the opcode may be set. A conventional scalar quantity searching instruction (Find) is given in the table 2, and any number in the scalar quantity to be searched can be searched by using the conventional scalar quantity searching instruction; and four special scalar lookup instructions are given in table 2 and define the opcodes and operation domains that two special types of scalar lookup instructions (Find _ bfirst, find _ blast) need to include. The scalar to be searched is searched by using the special type scalar searching instruction, so that the instruction processing process can be simplified, and the searching time can be saved.

TABLE 1 instruction Format

Table 2 scalar lookup instruction example

The scalar lookup instruction of the operation code 'Find _ bfirst' has a corresponding specified value of 1, the specified ordering is the 1 st of the numbers to be looked up which are ordered to be the specified value, and the width of the numbers to be looked up is 1.

The operation code is a scalar search instruction of 'Find _ blast', the width of the corresponding number to be searched is 1, the designated value is 1, and the 1 st of the numbers to be searched which are sorted into the number to be searched and are sorted into the order equal to the designated value are designated.

It should be understood that the location of the opcode, the opcode in the instruction format, and the operand field of the scalar lookup instruction may be set as desired by one skilled in the art, and the disclosure is not limited thereto.

In one possible implementation manner, the apparatus may be disposed in one or more of a Graphics Processing Unit (GPU), a Central Processing Unit (CPU), and an embedded Neural Network Processor (NPU).

It should be noted that, although the scalar lookup instruction processing apparatus is described above by taking the above-described embodiment as an example, those skilled in the art will understand that the present disclosure should not be limited thereto. In fact, the user can flexibly set each module according to personal preference and/or actual application scene, as long as the technical scheme of the disclosure is met.

Application examples

An application example according to the embodiment of the present disclosure is given below in combination with "performing a search on a scalar to be searched by using a scalar search instruction processing apparatus" as an exemplary application scenario, so as to facilitate understanding of a flow of the scalar search instruction processing apparatus. It is to be understood by those skilled in the art that the following application examples are for the purpose of facilitating understanding of the embodiments of the present disclosure only and are not to be construed as limiting the embodiments of the present disclosure.

3 a-3 c show schematic diagrams of an application scenario of a scalar lookup instruction processing apparatus according to an embodiment of the present disclosure. As shown in fig. 3a to 3c, the scalar lookup instruction processing apparatus processes a scalar lookup instruction as follows.

First, assume that the scalar a to be looked up is "010110110001". The scalar a to be searched is a number in decimal, that is, the scalar a to be searched is 1457 in decimal. To facilitate the distinction between different scalar lookup instructions it is assumed that the memory address of the scalar a to be looked up is different in the different scalar lookup instructions.

Scalar lookup instructions that the device needs to process include:

scalar lookup instruction 1: @ Find #1# #100# #12# #01# #4

Scalar lookup instruction 4: @ Find _ bfirst #103#12#203

Scalar lookup instruction 5: @ Find _ blast #104#12#204

Example 1

As shown in fig. 3a, when receiving a scalar lookup instruction 1, the control module 11 parses the scalar lookup instruction 1 to obtain that the operation code of the scalar lookup instruction 1 is Find, and determines that the specified value of the scalar lookup instruction 1 is "1", the scalar address to be looked up is "100", the input length is "12", the target address is "200", the 1 st of the numbers to be looked up which are specified as "numbers to be looked up and ranked as equal to the specified value", and the number to be looked up width is "4" according to the operation domain. Further, the control module 11 obtains the scalar a to be looked up "010110001" with the input length of 12 from the scalar address 200 to be looked up.

The operation module 12 obtains a plurality of numbers to be searched in sequence from the scalar a to be searched according to the width of the number to be searched being "4", determines whether the numerical values of the plurality of numbers to be searched are equal to the designated value "1", determines the number to be searched of the 1 st number of the numbers to be searched, which is equal to the designated value "1" and is sorted to be equal to the designated value "1", as the target number, and stores the storage address of the target number as the search result in the target address 200.

In this example, the operation module 12 first obtains the first to-be-checked number "0101" with a width of 4 from the to-be-searched scalar a, and determines whether the numerical value of the to-be-checked number "0101" is equal to the specified value "1". Since the value of the number to be checked "0101" is not 1, the operation module 12 continues to obtain the next number to be checked "1011" from the scalar a to be checked, and determines whether the value of the number to be checked "1011" is equal to the specified value "1". Since the value of the number to be checked "1011" is not 1, the operation module 12 continues to obtain the next number to be checked "0001" from the scalar a to be checked, and determines whether the value of the number to be checked "0001" is equal to the specified value "1". Since the value of the number to be checked "0001" is equal to 1 and the rank thereof is the designated rank (i.e. the rank of the number to be checked is 1 in the number to be checked which is equal to the designated value), the number to be checked "0001" is determined as the target number, and the storage address 500 of the number to be checked "0001" is stored as the search result in the target address 200.

Example 2

As shown in fig. 3b, when receiving the scalar lookup instruction 4, the control module 11 parses the scalar lookup instruction 4, obtains that the opcode of the scalar lookup instruction 4 is Find _ bfirst, and determines that the scalar address to be looked up of the scalar lookup instruction 4 is "103", the input length is "12", and the target address is "203" according to the operation domain. And, it is determined from the opcode Find _ bfirst that the specified value of the scalar lookup instruction 4 is "1", that the ordering is "1 st of the numbers to be checked which are ordered to be equal to the specified value". Further, the control module 11 obtains the scalar a to be looked up "010110001" with the input length of 12 from the scalar address to be looked up 203.

The operation module 12 sequentially obtains a plurality of numbers to be searched from the scalar a to be searched, sequentially determines whether the numerical values of the plurality of numbers to be searched are equal to the designated value "1", determines the number to be searched of the 1 st number to be searched, which is equal to the designated value "1" and is sorted to be equal to the designated value "1", as the target number, and stores the storage address of the target number as the search result into the target address 203.

In this example, the operation module 12 first obtains a first number "0" to be checked from the scalar a to be searched, and determines whether the value of the number "0" to be checked is equal to the specified value "1". Since the value of the number "0" to be looked up is not 1, the operation module 12 continues to acquire the next number "1" to be looked up from the scalar a to be looked up, and determines whether the value of the number "1" to be looked up is equal to the designated value "1". Since the value of the number to be checked "1" is equal to 1 and the rank thereof is the designated rank (i.e. the rank of the number to be checked is 1 st of the number to be checked which is equal to the designated value), the number to be checked "1" is determined as the target number, and the storage address 503 of the number to be checked "1" is stored as the search result in the target address 203.

Example 3

As shown in fig. 3c, when receiving the scalar search instruction 5, the control module 11 parses the scalar search instruction 5, obtains that the operation code of the scalar search instruction 4 is Find _ blast, and determines that the scalar address to be searched of the scalar search instruction 5 is "104", the input length is "12", and the target address is "204" according to the operation domain. And, it is determined from the opcode Find _ blast that the designated value of the scalar lookup instruction 5 is "1", and that the ordering is "the 1 st from the numbers to be checked in the ordering equal to the designated value" of the numbers to be checked. Further, the control module 11 obtains the scalar a to be looked up "010110001" with the input length of 12 from the scalar address to be looked up 204.

The operation module 12 sequentially obtains a plurality of numbers to be searched from the scalar a to be searched, sequentially determines whether the numerical values of the plurality of numbers to be searched are equal to the specified value "1", determines the number to be searched, which is equal to the specified value "1" and is sequenced to be equal to the 1 st from the number to be searched of the specified value "1", as the target number, and stores the storage address of the target number as the search result in the target address 204.

In this example, the operation module 12 first obtains a first number "1" to be looked up from the scalar a to be looked up, and determines whether the value of the number "1" to be looked up is equal to the specified value "1". Since the value of the number to be searched "1" is equal to 1 and the rank thereof is the specified rank (i.e. the rank of the number to be searched is the 1 st from the number to be searched which is equal to the specified value), the number to be searched "1" is determined as the target number, and the storage address 504 of the number to be searched "1" is stored as the search result in the target address 204.

Thus, the scalar lookup instruction processing device can quickly and efficiently process the scalar lookup instruction.

The present disclosure provides a machine learning arithmetic device, which may include one or more of the above scalar search instruction processing devices, and is configured to acquire data to be operated and control information from other processing devices, and execute a specified machine learning operation. The machine learning arithmetic device can obtain a scalar search instruction from other machine learning arithmetic devices or non-machine learning arithmetic devices, and transmit an execution result to peripheral equipment (also called other processing devices) through an I/O interface. Peripheral devices such as cameras, displays, mice, keyboards, network cards, wifi interfaces, servers. When more than one scalar lookup instruction processing device is included, the scalar lookup instruction processing devices can be linked and transmit data through a specific structure, for example, the data is interconnected and transmitted through a PCIE bus, so as to support larger-scale operation of the neural network. At this time, the same control system may be shared, or there may be separate control systems; the memory may be shared or there may be separate memories for each accelerator. In addition, the interconnection mode can be any interconnection topology.

The machine learning arithmetic device has high compatibility and can be connected with various types of servers through PCIE interfaces.

Fig. 4a shows a block diagram of a combined processing device according to an embodiment of the present disclosure. As shown in fig. 4a, the combined processing device includes the machine learning arithmetic device, the universal interconnection interface, and other processing devices. The machine learning arithmetic device interacts with other processing devices to jointly complete the operation designated by the user.

Other processing devices include one or more of general purpose/special purpose processors such as Central Processing Units (CPUs), graphics Processing Units (GPUs), neural network processors, and the like. The number of processors included in the other processing devices is not limited. The other processing devices are used as interfaces of the machine learning arithmetic device and external data and control, and comprise data transportation to finish basic control of starting, stopping and the like of the machine learning arithmetic device; other processing devices may cooperate with the machine learning computing device to perform computing tasks.

And the universal interconnection interface is used for transmitting data and control instructions between the machine learning arithmetic device and other processing devices. The machine learning arithmetic device acquires required input data from other processing devices and writes the input data into a storage device on the machine learning arithmetic device; control instructions can be obtained from other processing devices and written into a control cache on a machine learning arithmetic device chip; the data in the storage module of the machine learning arithmetic device can also be read and transmitted to other processing devices.

Fig. 4b shows a block diagram of a combined processing device according to an embodiment of the present disclosure. In a possible implementation manner, as shown in fig. 4b, the combined processing device may further include a storage device, and the storage device is connected to the machine learning operation device and the other processing device respectively. The storage device is used for storing data stored in the machine learning arithmetic device and the other processing device, and is particularly suitable for data which is required to be calculated and cannot be stored in the internal storage of the machine learning arithmetic device or the other processing device.

The combined processing device can be used as an SOC (system on chip) system of equipment such as a mobile phone, a robot, an unmanned aerial vehicle and video monitoring equipment, the core area of a control part is effectively reduced, the processing speed is increased, and the overall power consumption is reduced. In this case, the universal interconnect interface of the combined processing device is connected to some component of the apparatus. Some parts are such as camera, display, mouse, keyboard, network card, wifi interface.

The present disclosure provides a machine learning chip, which includes the above machine learning arithmetic device or combined processing device.

The present disclosure provides a machine learning chip package structure, which includes the above machine learning chip.

Fig. 5 shows a schematic structural diagram of a board card according to an embodiment of the present disclosure. As shown in fig. 5, the board includes the above-mentioned machine learning chip package structure or the above-mentioned machine learning chip. The board may include, in addition to the machine learning chip 389, other kits including, but not limited to: memory device 390, interface device 391 and control device 392.

The memory device 390 is coupled to a machine learning chip 389 (or a machine learning chip within a machine learning chip package structure) via a bus for storing data. Memory device 390 may include multiple sets of memory cells 393. Each group of memory cells 393 is coupled to a machine learning chip 389 via a bus. It is understood that each group 393 of memory cells may be a DDR SDRAM (Double Data Rate SDRAM).

DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on the rising and falling edges of a clock pulse. DDR is twice as fast as standard SDRAM.

In one embodiment, memory device 390 may include 4 groups of memory cells 393. Each group of memory cells 393 may include multiple DDR4 particles (chips). In one embodiment, the machine learning chip 389 may internally include 4 72-bit DDR4 controllers, wherein 64 bits of the 72-bit DDR4 controllers are used for data transmission, and 8 bits of the 72-bit DDR4 controllers are used for ECC checking. It is appreciated that when DDR4-3200 particles are used in each group of memory cells 393, the theoretical bandwidth of data transfer may reach 25600MB/s.

In one embodiment, each group 393 comprises a plurality of double rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice in one clock cycle. A controller for controlling DDR is provided in the machine learning chip 389, and is used to control data transfer and data storage of each memory unit 393.

Interface device 391 is electrically coupled to machine learning chip 389 (or a machine learning chip within a machine learning chip package). The interface device 391 is used to implement data transfer between the machine learning chip 389 and an external device (e.g., a server or computer). In one embodiment, for example, the interface device 391 may be a standard PCIE interface. For example, the data to be processed is transmitted to the machine learning chip 289 by the server through the standard PCIE interface, so as to implement data transfer. Preferably, when PCIE 3.0X 16 interface is adopted for transmission, the theoretical bandwidth can reach 16000MB/s. In another embodiment, the interface device 391 may also be another interface, and the disclosure does not limit the specific representation of the other interface, and the interface device can implement the switching function. In addition, the calculation result of the machine learning chip is still transmitted back to the external device (e.g., server) by the interface device.

The control device 392 is electrically connected to the machine learning chip 389. The control device 392 is used to monitor the state of the machine learning chip 389. Specifically, the machine learning chip 389 and the control device 392 may be electrically connected through an SPI interface. The control device 392 may include a single chip Microcomputer (MCU). For example, machine learning chip 389 may include multiple processing chips, multiple processing cores, or multiple processing circuits, which may carry multiple loads. Therefore, the machine learning chip 389 can be in different operating states such as a multi-load and a light load. The control device can regulate and control the working states of a plurality of processing chips, a plurality of processing circuits and/or a plurality of processing circuits in the machine learning chip.

The present disclosure provides an electronic device, which includes the above machine learning chip or board card.

The electronic device may include a data processing apparatus, a robot, a computer, a printer, a scanner, a tablet, a smart terminal, a cell phone, a tachograph, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, an earphone, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device.

The vehicle may include an aircraft, a ship, and/or a vehicle. The household appliances may include televisions, air conditioners, microwave ovens, refrigerators, electric rice cookers, humidifiers, washing machines, electric lamps, gas cookers, and range hoods. The medical device may include a nuclear magnetic resonance apparatus, a B-mode ultrasound apparatus and/or an electrocardiograph.

FIG. 6 illustrates a flow diagram of a scalar lookup instruction processing method according to an embodiment of the present disclosure. As shown in fig. 6, the method is applied to the scalar search instruction processing apparatus described above, and includes step S51 and step S52.

In step S51, the received scalar lookup instruction is parsed to obtain an operation code and an operation domain of the scalar lookup instruction, and a scalar to be looked up, a designated value, a designated sequence, and a target address required for executing the scalar lookup instruction are determined according to the operation code and the operation domain. The operation code is used for indicating the operation of the scalar data by the scalar search instruction to be search operation, and the operation domain comprises a scalar address to be searched and a target address.

In step S52, it is sequentially determined whether or not the numerical values of the plurality of numbers to be looked up representing scalars to be looked up are equal to a specified value, and the numbers to be looked up which are equal to the specified value and ordered to a specified order are determined as target numbers, and the storage addresses of the target numbers are stored as the search results into the target addresses.

In one possible implementation, the operation field may further include an input length. Determining a scalar to be searched, a specified value, a specified ordering and a target address required for executing the scalar search instruction according to the operation code and the operation domain may include: and acquiring the scalar to be searched from the scalar address to be searched according to the input length.

In one possible implementation, the operational domain may also include a specified value and a specified ordering. Determining a scalar to be searched, a specified value, a specified ordering and a target address required for executing the scalar search instruction according to the operation code and the operation domain may include: the assigned value and the assigned ordering are determined according to the operation domain.

In one possible implementation, determining the scalar to be looked up, the specified value, the specified ordering and the target address required for executing the scalar look-up instruction according to the operation code and the operation domain may include:

the specified value and specified ordering are determined from an opcode, which is also used to indicate the specified value and specified ordering of the scalar lookup instruction.

In one possible implementation, sequentially determining whether a numerical value of a plurality of numbers to be looked up representing scalars to be looked up is equal to a specified value may include:

and comparing the numerical values of the plurality of numbers to be checked with the specified value by using at least one comparator to obtain a comparison result so as to determine whether the numerical values of the numbers to be checked are equal to the specified value or not according to the comparison result.

In one possible implementation, the specifying the ordering may include at least one of:

the sequence of the numbers to be checked is the nth number of the numbers to be checked which is equal to the specified value, and n is a positive integer which is greater than or equal to 1; the sequence of the numbers to be checked is the mth from the last of the numbers to be checked which is equal to the specified value, and m is a positive integer which is greater than or equal to 1. And m and n are less than or equal to the number of the numbers to be searched in the scalars to be searched.

In one possible implementation, the method may further include: and storing the scalar to be searched.

In a possible implementation manner, parsing the received scalar lookup instruction to obtain an operation code and an operation domain of the scalar lookup instruction may include:

storing a scalar lookup instruction;

analyzing the scalar searching instruction to obtain an operation code and an operation domain of the scalar searching instruction;

the method includes storing an instruction queue, the instruction queue including a plurality of instructions to be executed arranged in sequence according to an execution order, and the plurality of instructions to be executed may include scalar lookup instructions.

In one possible implementation, the method may further include:

when determining that the first to-be-executed instruction in the plurality of to-be-executed instructions has an association relation with a zeroth to-be-executed instruction before the first to-be-executed instruction, caching the first to-be-executed instruction, and after determining that the execution of the zeroth to-be-executed instruction is finished, controlling the execution of the first to-be-executed instruction,

the method for associating the first to-be-executed instruction with the zeroth to-be-executed instruction before the first to-be-executed instruction comprises the following steps of:

the first storage address interval for storing the data required by the first to-be-executed instruction and the zeroth storage address interval for storing the data required by the zeroth to-be-executed instruction have an overlapped area.

It should be noted that, although the scalar lookup instruction processing method is described above by taking the above embodiment as an example, those skilled in the art can understand that the present disclosure should not be limited thereto. In fact, the user can flexibly set each step according to personal preference and/or actual application scene, as long as the technical scheme of the disclosure is met.

The scalar search instruction processing method provided by the embodiment of the disclosure has the advantages of wide application range, high processing efficiency and high processing speed of the scalar search instruction.

It should be noted that for simplicity of description, the above-mentioned embodiments of the method are described as a series of acts, but those skilled in the art should understand that the present application is not limited by the described order of acts, as some steps may be performed in other orders or simultaneously according to the present application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are exemplary embodiments and that acts and modules referred to are not necessarily required by the disclosure.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present disclosure, it should be understood that the disclosed system and apparatus may be implemented in other ways. For example, the above-described embodiments of the system and apparatus are merely illustrative, and for example, the division of the apparatus, device and module is only one type of logical function division, and there may be another division manner in actual implementation, for example, a plurality of modules may be combined or may be integrated into another system or apparatus, or some features may be omitted, or not executed. In addition, the shown or discussed coupling or direct coupling or communication connection between each other may be through some interfaces, and the indirect coupling or communication connection between the devices, apparatuses or modules may be in an electrical or other form.

Modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, functional modules in the embodiments of the present disclosure may be integrated into one processing unit, or each module may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a form of hardware or a form of a software program module.

The integrated modules, if implemented in the form of software program modules and sold or used as a stand-alone product, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present disclosure may be embodied in the form of a software product, which is stored in a memory and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present disclosure. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

Those skilled in the art will appreciate that all or part of the steps of the methods of the above embodiments may be implemented by a program, which is stored in a computer-readable memory, the memory including: flash Memory disks, read-Only memories (ROMs), random Access Memories (RAMs), magnetic or optical disks, and the like.

The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. An apparatus for processing scalar lookup instructions, the apparatus comprising:

an operation module, configured to sequentially determine whether a numerical value of a plurality of numbers to be looked up representing the scalar to be looked up is equal to the specified value, determine the number to be looked up that is equal to the specified value and is sorted into the specified sort as a target number, store a storage address of the target number as a search result in the target address,

the operation code is used for indicating that the operation of the scalar lookup instruction on scalar data is a lookup operation, and the operation domain comprises the scalar address to be looked up and the target address;

the operation domain further comprises a width of the numbers to be searched, and the operation module is further used for determining the plurality of numbers to be searched from the scalar to be searched according to the width of the numbers to be searched;

the specified ordering includes at least one of:

the sequence of the numbers to be checked is the nth number of the numbers to be checked which is equal to the specified value, and n is a positive integer which is greater than or equal to 1;

the rank of the numbers to be looked at is the mth from the number to be looked at equal to the specified value, m is a positive integer greater than or equal to 1,

and m and n are less than or equal to the number of the numbers to be searched in the scalar to be searched.

2. The apparatus of claim 1, wherein the operation domain further comprises an input length,

the control module is further configured to obtain the scalar to be searched from the scalar address to be searched according to the input length.

3. The apparatus of claim 1, wherein the operational domain further comprises a specified value and a specified ordering,

the control module is further configured to determine the specified value and the specified rank according to the operation domain.

4. The apparatus of claim 1,

the control module is further configured to determine the specified value and the specified ordering according to the operation code, where the operation code is further configured to indicate the specified value and the specified ordering of the scalar lookup instruction.

5. The apparatus of claim 1, wherein the computing module comprises:

and the comparator is used for comparing the numerical values of the plurality of numbers to be checked with the specified value to obtain a comparison result so as to determine whether the numerical values of the numbers to be checked are equal to the specified value or not according to the comparison result.

6. The apparatus of claim 1,

the device further comprises: the storage module is used for storing the scalar to be searched;

wherein the control module comprises:

the instruction storage submodule is used for storing the scalar search instruction;

the instruction processing submodule is used for analyzing the scalar searching instruction to obtain an operation code and an operation domain of the scalar searching instruction;

a queue storage submodule, configured to store an instruction queue, where the instruction queue includes multiple instructions to be executed that are sequentially arranged according to an execution order, where the multiple instructions to be executed include the scalar lookup instruction,

wherein, the control module still includes:

the dependency relationship processing submodule is used for caching a first instruction to be executed in the instruction storage submodule when the fact that the first instruction to be executed in the plurality of instructions to be executed is associated with a zeroth instruction to be executed before the first instruction to be executed is determined, extracting the first instruction to be executed from the instruction storage submodule after the zeroth instruction to be executed is executed, and sending the first instruction to be executed to the operation module,

wherein the association relationship between the first to-be-executed instruction and a zeroth to-be-executed instruction before the first to-be-executed instruction comprises:

and a first storage address interval for storing the data required by the first instruction to be executed and a zeroth storage address interval for storing the data required by the zeroth instruction to be executed have an overlapped area.

7. A machine learning operation apparatus, characterized in that the apparatus comprises:

one or more scalar lookup instruction processing apparatuses as claimed in any one of claims 1 to 6, configured to obtain data to be operated and control information from other processing apparatuses, perform a specified machine learning operation, and transmit an execution result to the other processing apparatuses through the I/O interface;

the scalar search instruction processing devices are interconnected through a Peripheral Component Interface Express (PCIE) bus and transmit data so as to support larger-scale machine learning operation; the scalar searching instruction processing devices share the same control system or own respective control systems; the scalar search instruction processing devices share a memory or own respective memories; the interconnection mode of the scalar lookup instruction processing devices is any interconnection topology.

8. A combined processing apparatus, characterized in that the combined processing apparatus comprises:

the machine learning computing device, the universal interconnect interface, and the other processing device of claim 7;

the machine learning arithmetic device interacts with the other processing devices to jointly complete the calculation operation appointed by the user,

wherein the combination processing apparatus further comprises: and a storage device connected to the machine learning calculation device and the other processing device, respectively, for storing data of the machine learning calculation device and the other processing device.

9. A machine learning chip, the machine learning chip comprising:

the machine learning computation apparatus of claim 7 or the combined processing apparatus of claim 8.

10. An electronic device, characterized in that the electronic device comprises:

the machine learning chip of claim 9.

11. The utility model provides a board card, its characterized in that, the board card includes: a memory device, an interface apparatus and a control device and a machine learning chip according to claim 9;

the machine learning chip is respectively connected with the storage device, the control device and the interface device;

the storage device is used for storing data;

the interface device is used for realizing data transmission between the machine learning chip and external equipment;

and the control device is used for monitoring the state of the machine learning chip.

12. A scalar lookup instruction processing method is applied to a scalar lookup instruction processing apparatus, and includes:

analyzing a received scalar searching instruction to obtain an operation code and an operation domain of the scalar searching instruction, and determining a scalar to be searched, a specified value, a specified sequence and a target address which are required by executing the scalar searching instruction according to the operation code and the operation domain;

the operation code is used for indicating that the operation of the scalar lookup instruction on data is a lookup operation, and the operation domain comprises the scalar address to be looked up and the target address;

the operation domain further comprises a number width to be searched, and the method further comprises the step of determining the plurality of numbers to be searched from the scalar to be searched according to the number width to be searched;

the specified ordering includes at least one of:

the rank of the number to be looked at is the m-th from the number to be looked at which is equal to the specified value, m is a positive integer greater than or equal to 1,

13. The method of claim 12, wherein the operation field further comprises an input length,

determining a scalar to be searched, a specified value, a specified ordering and a target address required by executing the scalar search instruction according to the operation code and the operation domain, wherein the method comprises the following steps of:

and acquiring the scalar to be searched from the scalar address to be searched according to the input length.

14. The method of claim 12, wherein the operation domain further comprises a specified value and a specified ordering,

wherein determining a scalar to be looked up, a specified value, a specified ordering and a target address required for executing the scalar look-up instruction according to the operation code and the operation domain comprises:

determining the specified value and the specified ordering according to the operation domain.

15. The method of claim 12, wherein determining from the opcode and the operation domain a scalar to be looked up, a specified value, a specified ordering, and a target address required to execute the scalar lookup instruction comprises:

determining the specified value and the specified ordering according to the opcode, the opcode further to indicate the specified value and the specified ordering of the scalar lookup instruction.

16. The method of claim 12, wherein sequentially determining whether a number of numbers representing the scalar quantity to be looked up is equal to the specified value comprises:

and comparing the numerical values of the plurality of numbers to be checked with the specified value by using at least one comparator to obtain a comparison result so as to determine whether the numerical values of the numbers to be checked are equal to the specified value according to the comparison result.

17. The method of claim 12,

the method further comprises the following steps: the scalar to be looked up is stored and,

the method for analyzing the received scalar search instruction to obtain the operation code and the operation domain of the scalar search instruction comprises the following steps:

storing the scalar lookup instruction;

storing an instruction queue comprising a plurality of instructions to be executed arranged in order of execution, the plurality of instructions to be executed comprising the scalar lookup instruction,

wherein the method further comprises:

when determining that the first to-be-executed instruction in the plurality of to-be-executed instructions is associated with a zeroth to-be-executed instruction before the first to-be-executed instruction, caching the first to-be-executed instruction, and after determining that the zeroth to-be-executed instruction is completely executed, controlling to execute the first to-be-executed instruction,