CN113156431A - FPGA-based back projection rapid imaging architecture design method - Google Patents
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Abstract
The invention discloses a method for designing a back projection fast imaging architecture based on an FPGA (field programmable gate array), which executes the following steps in a pipeline mode: acquiring imaging grid information and echo data subjected to distance direction pulse compression processing, loading the echo data into an on-chip cache, and extracting the imaging grid information from the echo data; generating pixel point data according to the imaging grid information; performing bistatic distance operation of the radar array element according to the pixel point data to obtain bistatic distance data; calling bistatic distance data and echo data to perform parallel processing of back projection operation so as to obtain imaging intermediate data; and performing coherent accumulation on the imaging intermediate data to obtain imaging result data. The embodiment of the invention executes each step in a pipeline mode, is favorable for improving the data processing efficiency, carries out parallel processing of backward projection operation based on the transmitting-receiving separation characteristic of bistatic distance data of the radar array element, and is favorable for improving the backward projection imaging speed.
Description
Technical Field
The invention relates to the technical field of radar, in particular to a design method of a back projection fast imaging architecture based on an FPGA.
Background
With the continuous development of radar imaging technology, the radar imaging technology is gradually popularized in the military and civil fields, for example, the radar imaging technology is applied to millimeter wave human body imaging security inspection products. At present, the main algorithms of radar imaging technology are divided into a frequency domain imaging algorithm and a time domain imaging algorithm, wherein the time domain imaging algorithm mainly includes a Back Projection algorithm (BP for short).
Due to the large calculation amount of the BP algorithm, in order to meet the requirement of a user on the imaging speed, a hardware architecture for realizing the BP algorithm is gradually developed from a traditional hardware architecture based on a CPU to a hardware architecture based on a CPU + GPU. The hardware architecture based on the CPU and the GPU improves the imaging speed by combining serial processing of the CPU and parallel processing of the GPU. However, with the continuous development of the technology, the hardware architecture based on the CPU + GPU has not been able to meet the requirements of users on the imaging speed and the operation power consumption. Therefore, a back projection imaging architecture with faster imaging speed and lower operation power consumption is needed.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides a design method of a back projection fast imaging framework based on an FPGA, which can improve the back projection imaging speed.
On the first hand, according to the method for designing the back projection fast imaging architecture based on the FPGA, the following steps are executed in a pipeline mode:
acquiring imaging grid information and echo data subjected to distance direction pulse compression processing, and loading the echo data into an on-chip cache;
generating pixel point data of the imaging grid according to the imaging grid information;
performing bistatic distance operation of the radar array element according to the pixel point data to obtain bistatic distance data;
calling the bistatic distance data and the echo data to perform parallel processing of back projection operation so as to obtain imaging intermediate data;
and carrying out coherent accumulation on the imaging intermediate data to obtain imaging result data.
The method for designing the back projection fast imaging architecture based on the FPGA has the following beneficial effects:
the embodiment of the invention executes each step in a pipeline mode, is favorable for improving the data processing efficiency, carries out parallel processing of backward projection operation based on the transmitting-receiving separation characteristic of bistatic distance data of the radar array element, and is favorable for improving the backward projection imaging speed.
According to some embodiments of the invention, the on-chip buffer is divided into a first buffer region and a second buffer region, the first buffer region is used for accessing the echo data in a ping-pong access mode, and the second buffer region is used for accessing the imaging intermediate data in a ping-pong access mode.
According to some embodiments of the present invention, the first buffer area accesses the echo data in a manner that physical address coding is performed on two-dimensional quadrants of the radar receiving array element and the radar transmitting array element.
According to some embodiments of the invention, the second buffer accesses the imaging intermediate data in interleaved addresses.
According to some embodiments of the invention, the back projection operation is performed by using a plurality of cascaded back projection computation cores, the back projection computation cores comprise a plurality of parallel cascaded back projection computation basic units, and the bistatic distance data is stored in a cache of the back projection computation basic units in a crossed mode.
According to some embodiments of the present invention, each of the back-projection operation basic units includes a third buffer area and a fourth buffer area, the third buffer areas of the back-projection operation basic units located in the same column are used for storing the same receiving direction monostatic distance data, and the fourth buffer areas of the back-projection operation basic units located in the same row are used for storing the same transmitting direction monostatic distance data, wherein the receiving direction monostatic distance data is used for representing the distance between a radar receiving array element in the bistatic distance data and a corresponding pixel point, and the transmitting direction monostatic distance data is used for representing the distance between a radar transmitting array element in the bistatic distance data and a corresponding pixel point.
According to some embodiments of the invention, each of the back projection calculation basic units further comprises a fifth buffer for storing the echo data required for the back projection calculation.
According to some embodiments of the present invention, the back projection computation core further includes a cascade input unit and a cascade output unit, the cascade input unit is configured to receive and transmit the bistatic distance data, the echo data, and imaging intermediate data output by the back projection computation core of a previous stage to the back projection computation base unit of a first stage, respectively, and the cascade output unit is configured to receive and transmit the bistatic distance data, the echo data, and imaging intermediate data from the back projection computation base unit of a last stage to the back projection computation core of a next stage.
According to some embodiments of the invention, the back projection computation kernel is power consumption controlled by dynamically gating a clock.
In a second aspect, an FPGA architecture according to an embodiment of the present invention includes: a high bandwidth storage unit; the bus control unit is used for acquiring imaging grid information and echo data compressed to the pulse through the distance; the memory management unit is used for receiving the echo data and storing the echo data to the high-bandwidth storage unit; the pixel grid generation control unit is used for receiving the imaging grid information and generating pixel point data according to the imaging grid information; the bistatic distance calculation unit is used for performing bistatic distance calculation of the radar array element according to the pixel point data to obtain bistatic distance data; the backward projection calculation kernel is used for calling the bistatic distance data and the echo data to perform parallel processing of backward projection calculation so as to obtain imaging intermediate data; the memory management unit is further configured to perform coherent accumulation on the imaging intermediate data to obtain imaging result data.
The FPGA architecture provided by the embodiment of the invention at least has the following beneficial effects:
the FPGA-based hardware architecture has more flexible pipeline design, the FPGA module can be internally configured with corresponding logic architectures according to different functional requirements, corresponding functions are realized on different FPGA modules, the functions are absorbed, the flexible reconfiguration characteristics of the FPGA module can be fully utilized to maintain and manage the functions and architectures of the first FPGA module and the second FPGA module respectively, the FPGA module and the second FPGA module are matched with each other and can be designed independently, and the design difficulty is reduced.
According to some embodiments of the present invention, the number of the back projection computation cores is plural, a plurality of the back projection computation cores are connected in cascade, the back projection computation cores include a plurality of back calculation basic units cascaded in parallel, and the bistatic distance data is stored in a cache of the back calculation basic units in a crossed manner.
According to some embodiments of the present invention, each of the back-projection operation basic units includes a third buffer area and a fourth buffer area, the third buffer areas of the back-projection operation basic units located in the same column are used for storing the same receiving direction monostatic distance data, and the fourth buffer areas of the back-projection operation basic units located in the same row are used for storing the same transmitting direction monostatic distance data, wherein the receiving direction monostatic distance data is used for representing the distance between a radar receiving array element in the bistatic distance data and a corresponding pixel point, and the transmitting direction monostatic distance data is used for representing the distance between a radar transmitting array element in the bistatic distance data and a corresponding pixel point.
According to some embodiments of the invention, each of the back projection calculation basic units further comprises a fifth buffer for storing the echo data required for the back projection calculation.
According to some embodiments of the present invention, the back projection computation core further includes a cascade input unit and a cascade output unit, the cascade input unit is configured to receive and transmit the bistatic distance data, the echo data, and imaging intermediate data output by the back projection computation core of a previous stage to the back projection computation base unit of a first stage, respectively, and the cascade output unit is configured to receive and transmit the bistatic distance data, the echo data, and imaging intermediate data from the back projection computation base unit of a last stage to the back projection computation core of a next stage.
In a third aspect, a rear projection imaging architecture according to an embodiment of the invention comprises: the system comprises a first FPGA module, a second FPGA module and a third FPGA module, wherein the first FPGA module is used for acquiring echo sampling data input from the outside, performing range-wise pulse compression processing on the echo sampling data to acquire echo data and extracting imaging grid information from the echo data; and the second FPGA module is connected with the first FPGA module through an inter-chip interconnection bus, and is used for receiving the echo data and the imaging grid information, performing backward projection imaging processing according to the echo data and the imaging grid information to obtain imaging result data, and returning the imaging data to the first FPGA module for outputting the imaging result data to the outside.
According to some embodiments of the invention, the second FPGA module is configured with the FPGA architecture described above.
In a fourth aspect, an apparatus according to an embodiment of the present invention includes the above-described back projection imaging architecture.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
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The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a flow chart of a method for designing a back projection fast imaging architecture based on an FPGA according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a logic structure of a pixel grid and a transceiving distance in a method for designing a back projection fast imaging architecture based on an FPGA according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a logic structure of an on-chip cache in the design method of the FPGA-based rear projection fast imaging architecture according to the embodiment of the present invention;
fig. 4a and 4b are a data structure of echo data and a data structure of an imaging intermediate result of the FPGA-based back projection fast imaging architecture design method according to the embodiment of the present invention, respectively;
fig. 5 is a schematic diagram of a logical structure of a back projection computation kernel of the method for designing a back projection fast imaging architecture based on an FPGA according to the embodiment of the present invention;
FIG. 6 is a schematic diagram of a logical structure of a back-projection computation basic unit of the back-projection computation kernel in FIG. 5;
FIG. 7 is a logic relationship diagram of a dynamic clock gating in the design method of the FPGA-based back projection fast imaging architecture according to the embodiment of the present invention;
FIG. 8 is a schematic diagram of a logical structure of a rear projection imaging architecture according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a logic structure of an FPGA architecture according to an embodiment of the present invention;
FIG. 10 is a logic diagram of the accumulated output of imaging intermediate data according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, the meaning of a plurality of means is one or more, the meaning of a plurality of means is two or more, and larger, smaller, larger, etc. are understood as excluding the number, and larger, smaller, inner, etc. are understood as including the number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
Example 1
The embodiment discloses a method for designing a back projection fast imaging architecture based on an FPGA (field programmable gate array), which is mainly based on a pipeline processing technology of an FPGA module and the transceiving separation characteristic of bistatic distance data of a radar array element. In the present embodiment, a MIMO radar (multiple input multiple output radar) is taken as an example for description. The MIMO radar generally includes a plurality of transmitting array elements and a plurality of receiving array elements, and of course, the radar array elements may be shared for transmitting and receiving. The MIMO radar allows different waveforms to be transmitted on each radar array element simultaneously, each transmitting array element transmits different signal waveforms, and transmitting signals of each waveform are sampled and received by a plurality of receiving array elements after being reflected by a target object, so that echo sampling data are obtained. The basic principle of the backward projection algorithm is to reversely project the echo sampling data of the radar to each pixel point of the imaging area, and the value of the pixel point can be determined by calculating the delay accumulation of the distance between the radar array element and the pixel point of the radar echo. The main flow of the back projection algorithm comprises distance direction processing and azimuth direction processing, and the distance direction processing mainly comprises distance direction pulse compression processing based on Fourier transform and inverse Fourier transform on echo sampling data to obtain echo data. The processing method of this step is well known to those skilled in the art, and the description of this embodiment is not repeated. To improve data processing efficiency, this step may be preprocessed in a Pre Processing Unit (PPU). It should be noted that the subsequent azimuth processing requires imaging mesh information extracted from the echo data, where the imaging mesh information includes mesh size, mesh pitch, and mesh coordinates of the imaging region. In order to improve the data processing efficiency, the step of extracting the imaging mesh information from the echo data may be done in a pre-processing unit.
Referring to fig. 1, the present embodiment discloses a method for designing a back projection fast imaging architecture based on an FPGA, which performs the following steps S100, S200, S300, S400 and S500 in a pipeline manner. It should be noted that, in the description of the embodiment of the present invention, the consecutive reference numbers of the method steps are for convenience of examination and understanding, and the implementation order between the steps is adjusted without affecting the technical effect achieved by the technical solution of the present invention by combining the entire technical solution of the present invention and the logical relationship between the steps. The following describes steps S100, S200, S300, S400, and S500 in detail.
S100, acquiring imaging grid information and echo data subjected to distance direction pulse compression processing, and loading the echo data into an on-chip cache.
The design method of the Back projection fast imaging architecture based on the FPGA of the present embodiment is completed in a Back projection processing Unit (BPU), and functions of units can be more concentrated through division and cooperation of different units. In this embodiment, the preprocessing unit and the backward projection processing unit are both implemented by FPGA modules. The FPGA module is composed of hardware resources such as a logic unit, an RAM, a multiplier and the like, and on-chip cache for data storage can be realized by reasonably organizing the hardware resources. Compared with the data transmission efficiency among different FPGA modules, the data transmission efficiency among different units in the same FPGA module is higher, so that the echo data are loaded into the chip for caching, the corresponding echo data can be called conveniently in subsequent data processing, and the operation speed can be improved.
And S200, generating pixel point data of the imaging grid according to the imaging grid information.
Referring to fig. 2, during three-dimensional imaging, a spatial three-dimensional pixel grid is constructed by a radar front, wherein the pixel grid takes the radar front as a start of a Z dimension, a physical center of the radar front as a coordinate center of an X, Y dimension, and the pixel grid and the radar front are constructed in a global unified coordinate system and perform subsequent bistatic range calculation of radar echoes.
S300, performing bistatic distance operation of the radar array element according to the pixel point data to obtain bistatic distance data.
For a certain pixel point in the imaging space, the sum of the distances traveled by radar waves is the sum of the distances between the radar receiving and transmitting array elements and the pixel point, and the sum of the distances satisfies the formula:
RB＝Rt+Rr (1)
in the formula, RtFor the distance between the radar transmitting array element and the corresponding pixel point in the bistatic range data, RrThe distance between a radar receiving array element and a corresponding pixel point in bistatic distance data is shown, x, y and z are coordinate values of the pixel point in X, Y, Z dimensions respectively, and x is the coordinate value of the pixel point in the bistatic distance datat、ytCoordinate values of the radar transmitting array element in X, Y dimensions, x respectivelyr、yrRespectively, the coordinate values of the radar receiving array elements in the dimension X, Y.
And S400, calling the bistatic distance data and the echo data to perform parallel processing of back projection operation so as to obtain imaging intermediate data.
For three-dimensional imaging, three-dimensional pixel grids are divided at equal intervals in the (x, y, z) domain, and the polar coordinates of these pixel grids are respectively denoted as { x }p|p＝1，2，...，P}、{ y q1, 2,. Q, and { z |u1, 2. Recording the expression of echo signals in the azimuth time domain-distance frequency domain after the MIMO radar one-dimensional distance compression after compensating the position error of the array elements and the delay error between the channels as Sc＝(frM, n), the basic principle of the backprojection algorithm can be expressed in the frequency domain as:
in the formula (f)rAnd m is the number of radar transmitting array elements and n is the number of radar receiving array elements. Considering that the imaging scene and the distance are discretized towards the frequency axis in actual operation, the above formula can be degraded into a form of three-level summationThen, the three-dimensional complex image obtained by the back projection processing is:
further, remember
Indicating rounding up, will
Denoted as center frequency, Δ f denotes the frequency step interval, in which case the summation in the frequency dimension can be achieved by an Inverse Fast Fourier Transform (IFFT):
wherein,
equation (7) is a defining equation of a typical inverse fourier series, and considering that its frequency spectrum is just a finite baseband spectrum, and the calculation of this part can be calculated using an IFFT approximation, equation (6) can be written as follows:
where η represents the interpolation multiple, Sbase(h, m, n), h ═ 0, 1., η · K denotes Sc(fkM, n) sequences the IFFT results in the dimension k, which results are included in the echo data of step S100.
In formulas (5) to (8), the sum R of the distances traveled by the radar wavesB(m,n,xp,yq,zu) The calculation method (2) can be referred to the formulas (1) to (3). For a certain pixel point (x)p,yq,zu) In a word, I0(p, q, u) is simply understood as the sum of m, n as variables
The calculation form can be referred to table 1.
TABLE 1
In table 1, m is the number of radar transmitting array elements, and n is the number of radar receiving array elements. As can be seen from table 1, when n takes different values, it indicates that data corresponding to the nth radar receiving array element, such as bistatic range data and echo data, are accumulated. For a column with m equal to 1,
using data of radar receiving array elements as variable sum
Similarly, for each column of M, 2, the data of the radar receiving array element is used as a variable, and the data operations of each column are independent from each other, so that the operations can be performed in a parallel processing manner to obtain imaging intermediate data, which is beneficial to improving the operation efficiency. It should be understood that, in the operation process, the data of the radar transmitting array elements can be taken as variables to be summed to obtain imaging intermediate data.
And S500, performing coherent accumulation on the imaging intermediate data to obtain imaging result data.
As can be seen from table 1, the imaging intermediate data obtained by each column of calculation is the sum of the data of the radar receiving array elements as variables, and to obtain the imaging result data, coherent accumulation of the imaging intermediate data is also required.
The embodiment of the invention executes the steps S100 to S500 in a pipeline mode, can realize quasi-parallel operation in time and is beneficial to improving the efficiency of data processing. As can be seen from the principle of steps S300 and S400, the embodiment of the present invention performs parallel processing of the back projection operation based on the transmit-receive separation characteristic of the bistatic range data of the radar array element, which is beneficial to improving the back projection imaging speed. Compared with the existing serial and parallel processing mode of CPU and GPU, the embodiment of the invention adopts a pipeline parallel mode to better improve the imaging speed of back projection.
Referring to fig. 3, in order to improve the utilization efficiency of the on-chip cache, the on-chip cache is divided into a first cache region and a second cache region, the first cache region is used for accessing the echo data in a ping-pong access manner, and the second cache region is used for accessing the imaging intermediate data in a ping-pong access manner. Ping-pong access is the cooperative switching of storing and reading data according to the beat in the data access process, and the buffered data stream is continuously sent to the target processing module for processing. In the data access process, the data flow is continuous, so that the ping-pong data access mode can realize seamless buffer processing of data in the pipelined operation process. In addition, the embodiment separately divides the corresponding buffer areas for the echo data and the imaging intermediate data, can realize mutual independence of different data access in a physical space, and can realize parallel processing of different data access in a time dimension, thereby greatly improving the service efficiency of the on-chip buffer.
In the process of the back projection operation in step S400, the corresponding radar receiving array elements and the echo data of the radar transmitting array elements need to be called. As can be seen from the format of table 1, the data operation format is a two-dimensional matrix with m, n as variables. Therefore, referring to fig. 4a, in order to facilitate calling and managing the echo data, the first buffer area accesses the echo data in a manner that physical address coding is performed on two-dimensional quadrants of the radar receiving array element and the radar transmitting array element. When the echo data is called, memory address calculation and data calling can be carried out on the echo data of the corresponding radar array element according to the memory initial address, the number of the radar transmitting array element, the address offset and the number of the radar receiving array element.
Similarly, referring to FIG. 4b, the second buffer accesses the intermediate imaging data according to the interleaved address, which is shown at z in FIG. 4b0、z1、...、znIn the plane, imaging intermediate data corresponding to different pixel points are stored in an interleaving address mode, so that the imaging intermediate data can be conveniently stored, called and managed.
Referring to fig. 5, in step S400, in order to further improve the back-projection imaging efficiency, a plurality of cascaded back-projection computation kernels (Kernel) are used to perform back-projection computation, the back-projection computation kernels include a plurality of parallel cascaded back-projection computation basic units (BP core), and the bistatic distance data are cross-stored in a cache of the back-projection computation basic units. Referring to fig. 5, the back-projection operation basic unit is a basic operation unit of the back-projection computation kernel, referring to fig. 5 and table 1, a plurality of parallel cascaded back-projection operation basic units are used for performing parallel processing of cascade accumulation on data of the radar transmitting array element and the radar receiving array element of the same pixel point, redundant operation of data repeated accumulation is reduced, and a running-water parallel operation target of data cascade carry accumulation is achieved. The data of different pixel points are checked in the plurality of cascaded backward projection calculations to carry out the cascade carry flow processing, the carry accumulation redundant operation between the data is simplified, the data processing efficiency is favorably improved, and the backward projection imaging speed is improved. The number of the backward projection calculation kernels can be expanded or deleted according to actual requirements and corresponding hardware conditions, flexible clipping of the backward projection calculation kernels is achieved, and improvement of application flexibility is facilitated.
Referring to fig. 5 and 6, in a specific embodiment, each back-projection operation basic unit includes a third buffer area and a fourth buffer area, the third buffer areas of the back-projection operation basic units located in the same column are used for storing the same receiving direction monostatic distance data, the fourth buffer areas of the back-projection operation basic units located in the same row are used for storing the same transmitting direction monostatic distance data, wherein the receiving direction monostatic distance data is used for representing the distance between a radar receiving array element in the bistatic distance data and a corresponding pixel point, and the transmitting direction monostatic distance data is used for representing the distance between a radar transmitting array element in the bistatic distance data and a corresponding pixel point. By storing the bistatic distance data in the back-calculation basic unit in a crossed manner, the bistatic distance data can be crossed and multiplexed. In addition, in the bistatic distance operation of step S300, when bistatic distance data of a radar array element corresponding to a pixel point is calculated each time, only the receiver-direction monostatic distance data and the transmitting-direction monostatic distance data required by each back-projection operation basic unit need to be calculated, and repeated calculation is not needed, so that the bistatic distance operation of step S300 is simplified, the data processing efficiency is improved, and the back-projection imaging speed is increased.
With reference to fig. 6, each back-projection operation basic unit further includes a fifth buffer area, and the fifth buffer area is configured to store echo data required for back-projection operation, for example, in table 1, when the value of n is different, the echo data of the corresponding radar receiving array element is read from the on-chip buffer and stored in the fifth buffer area of the corresponding back-projection operation basic unit. When operation is carried out, the anti-operation unit in each anti-operation basic unit calls data from the fifth cache region to accumulate the data of the radar transmitting array element and the radar receiving array element of the pixel point without repeatedly reading the data from the on-chip cache, and the efficiency of data calling is improved.
Referring to fig. 5, the back projection computation kernel further includes a cascade input unit and a cascade output unit, the cascade input unit is configured to receive and transmit bistatic distance data, echo data, and imaging intermediate data output by the back projection computation kernel of a previous stage to the back projection computation basic unit of a first stage, the cascade output unit is configured to receive and transmit bistatic distance data, echo data, and imaging intermediate data from the back projection computation basic unit of a last stage to the back projection computation kernel of a next stage, and data between the back projection computation basic units is transmitted in a cascade manner in a broadcast form, for example, each data carries a broadcast destination ID, and the data is transmitted to the corresponding back projection computation basic unit according to the broadcast destination ID. It should be noted that the backward projection computation core of the first stage reads corresponding echo data from the on-chip cache, and the backward projection computation core of the last stage accumulates the imaging intermediate data obtained by operation and stores the accumulated imaging intermediate data into the on-chip cache.
Referring to fig. 7, fig. 7 shows the logical relationship between the clock source (CLK root), the clock gating unit (CLK gating), the backward projection computation core (Kernel), and the Standby control unit (Standby ctrl). When no echo sampling data is input to the preprocessing unit, the standby control unit provides a stop signal to the gating clock unit so as to cut off a clock signal between a clock source and the backward projection calculation kernel, and the backward projection calculation kernel stops working, so that the power consumption can be reduced; when the preprocessing unit receives echo sampling data or the backward projection processing unit receives echo data, the standby control unit provides an enabling signal for the gated clock unit to control the gated clock unit to act, so that the clock source provides a clock signal for the backward projection calculation kernel, and the backward projection calculation kernel works according to the clock signal. According to the embodiment, the power consumption of the backward projection computing kernel is controlled in a dynamic clock gating mode, and the power consumption is favorably reduced.
Example 2
Referring to fig. 8, a method for designing a fast imaging architecture based on FPGA of embodiment 1 is provided, where this embodiment provides a back projection imaging architecture, including a first FPGA module and a second FPGA module, the first FPGA module is configured to obtain echo sampling data input from outside, and perform range-wise pulse compression processing on the echo sampling data to obtain echo data, and is configured to extract imaging grid information from the echo data, the second FPGA module is connected to the first FPGA module through an inter-chip interconnect bus (SRIO), and is configured to receive the echo data and the imaging grid information, and perform back projection imaging processing according to the echo data and the imaging grid information to obtain imaging result data, and is configured to return the imaging data to the first FPGA module for external output of the imaging result data. Compared with the hardware architecture of a CPU + GPU, the pipeline design of the hardware architecture based on the FPGA module is more flexible, and the interior of the FPGA module can be configured with corresponding logic architectures according to different functional requirements, wherein the first FPGA module preprocesses externally input echo sampling data, the second FPGA module performs backward projection imaging processing on the echo data, corresponding functions are realized on different FPGA modules, the functions are absorbed, and the characteristics of flexibly reconstructing the FPGA module can be fully utilized to design, maintain and manage the functions and the architecture of the first FPGA module and the second FPGA module respectively, the two modules are matched with each other and can be designed independently, and the design difficulty is favorably reduced.
Referring to fig. 9, in order to improve the data processing efficiency of the second FPGA module, the second FPGA module may configure an FPGA architecture, where the FPGA architecture includes a bus controller (SRIOX4 controller), a Memory Management Unit (MMU), a high bandwidth storage unit (HBM), a pixel grid generation control unit (voxel _ grid _ gen), a bistatic distance calculation unit (range _ gen), and a back projection calculation Kernel (Kernel).
In this embodiment, the bus controller, the memory management unit, the high bandwidth storage unit, the pixel grid generation control unit, the bistatic distance calculation unit, and the back projection calculation kernel perform data calculation in a pipeline manner, and the data calculation process may refer to embodiment 1. The bus control unit is used for acquiring imaging grid information and echo data compressed to pulse through distance; the memory management unit is used for receiving the echo data and storing the echo data to the high-bandwidth storage unit; the pixel grid generation control unit is used for receiving imaging grid information and generating pixel point data according to the imaging grid information; the bistatic distance calculation unit is used for performing bistatic distance calculation of the radar array element according to the pixel point data to obtain bistatic distance data; the backward projection calculation kernel is used for calling the bistatic distance data and the echo data to perform parallel processing of backward projection operation so as to obtain imaging intermediate data; the memory management unit is also used for carrying out coherent accumulation on the imaging intermediate data to obtain imaging result data; the bus control unit is also used for sending the imaging result data to the first FPGA module.
Referring to fig. 2, the pixel grid generation control unit is provided with a memory area for caching imaging grid information. When the pixel grid generation control unit carries out three-dimensional imaging, a space three-dimensional pixel grid is constructed through a radar array surface, wherein the pixel grid takes the radar array surface as the start of a Z dimension, takes the physical center point of the array surface as the coordinate center point of X, Y dimensions, the pixel grid and the radar array surface are constructed under a global unified coordinate system and carry out subsequent bistatic distance operation of radar echo, and the pixel grid generation control unit generates corresponding pixel point data and transmits the pixel point data to the bistatic distance calculation unit. The bistatic distance calculation unit performs bistatic distance calculation of the radar array element according to the pixel point data, and the method for calculating the bistatic distance can refer to embodiment 1, which is not described in detail again.
Referring to fig. 3, the high bandwidth storage unit is provided with a first buffer area and a second buffer area, the first buffer area is used for accessing the echo data in a ping-pong access manner, and the second buffer area is used for accessing the imaging intermediate data in a ping-pong access manner. Ping-pong access is the cooperative switching of storing and reading data according to the beat in the data access process, and the buffered data stream is continuously sent to the target processing module for processing. In the data access process, the data flow is continuous, so that the ping-pong data access mode can realize seamless buffer processing of data in the pipelined operation process. And the high-bandwidth storage unit independently sets corresponding buffer areas for echo data and imaging intermediate data, so that mutual independence of different data access can be realized in a physical space, parallel processing of different data access can be realized in a time dimension, and the use efficiency of the high-bandwidth storage unit is greatly improved.
Referring to fig. 4a, the first buffer area accesses the echo data in a manner of performing physical address coding on two-dimensional quadrants of the radar receiving array element and the radar transmitting array element. When echo data is called, the memory management unit can calculate the memory address and call the data of the echo data of the corresponding radar array element according to the memory initial address, the number of the radar transmitting array element, the address offset and the number of the radar receiving array element.
Similarly, referring to FIG. 4b, the second buffer accesses the intermediate imaging data according to the interleaved address, which is shown in FIG. 4bz0、z1、...、znIn the plane, imaging intermediate data corresponding to different pixel points are stored in an interleaving address mode, so that the imaging intermediate data can be conveniently stored, called and managed. Based on the design of the first cache region and the second cache region, the memory management unit calls echo data and stores imaging intermediate data, so that parallelism in physical space and time dimensions can be realized.
Referring to fig. 5, in the present embodiment, the number of the back projection computation cores is multiple, the multiple back projection computation cores are connected in cascade, each back projection computation core includes multiple back throw computation basic units (BP core) cascaded in parallel, and the bistatic distance data from the bistatic distance computation unit is stored in a cache of the back throw computation basic units in a crossed manner. Referring to fig. 5, the back-projection operation basic unit is a basic operation unit of the back-projection computation kernel, referring to fig. 5 and table 1, a plurality of parallel cascaded back-projection operation basic units are used for performing parallel processing of cascade accumulation on data of the radar transmitting array element and the radar receiving array element of the same pixel point, redundant operation of data repeated accumulation is reduced, and a running-line parallel operation target of data cascade carry accumulation is achieved. The data of different pixel points are checked in the plurality of cascaded backward projection calculations to carry out cascade carry flow processing, the carry accumulation redundant operation among the data is simplified, the data processing efficiency is favorably improved, and the backward projection imaging speed is improved. The number of the backward projection calculation kernels can be expanded or deleted according to actual requirements and corresponding hardware conditions, flexible clipping of the backward projection calculation kernels is achieved, and improvement of application flexibility is facilitated.
Referring to fig. 5 and 6, in this embodiment, each back-projection operation basic unit includes a third buffer area and a fourth buffer area, the third buffer areas of the back-projection operation basic units located in the same column are used to store the same receiving-side monostatic distance data, and the fourth buffer areas of the back-projection operation basic units located in the same row are used to store the same transmitting-side monostatic distance data, where the receiving-side monostatic distance data is used to represent the distance between a radar receiving array element in the bistatic distance data and a corresponding pixel point, and the transmitting-side monostatic distance data is used to represent the distance between a radar transmitting array element in the bistatic distance data and a corresponding pixel point. By storing the bistatic distance data in the back-calculation basic unit in a crossed manner, the bistatic distance data can be crossed and multiplexed. In addition, in bistatic distance operation, when bistatic distance data of the radar array element corresponding to the pixel point are calculated once, only receiving direction monostatic distance data and transmitting direction monostatic distance data required by each back-projection operation basic unit need to be calculated, repeated calculation is not needed, bistatic distance operation is simplified, data processing efficiency is improved, and therefore backward projection imaging speed is improved.
With reference to fig. 6, each back-projection calculation basic unit further includes a fifth buffer area, and the fifth buffer area is used to store echo data required for back-projection calculation, for example, in table 1, when the value of n is different, the echo data of the corresponding radar receiving array element is read from the high-bandwidth storage unit and stored in the fifth buffer area of the corresponding back-projection calculation basic unit. When operation is carried out, the anti-operation unit in each anti-operation basic unit calls data from the fifth cache region to accumulate the data of the radar transmitting array element and the radar receiving array element of the pixel point without repeatedly reading the data from the high-bandwidth storage unit, and the efficiency of data calling is improved.
Referring to fig. 5, the back projection computation kernel further includes a cascade input unit and a cascade output unit, the cascade input unit is configured to receive and transmit bistatic distance data, echo data, and imaging intermediate data output by the back projection computation kernel of a previous stage to the back projection computation basic unit of a first stage, the cascade output unit is configured to receive and transmit bistatic distance data, echo data, and imaging intermediate data from the back projection computation basic unit of a last stage to the back projection computation kernel of a next stage, and data between the back projection computation basic units is transmitted in a cascade manner in a broadcast form, for example, each data carries a broadcast destination ID, and the data is transmitted to the corresponding back projection computation basic unit according to the broadcast destination ID. It should be noted that the backward projection computation kernel of the first stage reads corresponding echo data from the high bandwidth storage unit, and the backward projection computation kernel of the last stage outputs the imaging intermediate data obtained by the computation to the memory management unit, and stores the imaging intermediate data into the high bandwidth storage unit after the accumulation processing by the memory management unit.
Referring to fig. 7, the backward projection computation core is provided with a clock signal input end, the clock signal input end of the backward projection computation core is sequentially connected with a gated clock unit and a clock source, and an enable end of the gated clock unit is connected with a standby control unit. When no echo sampling data is input to the first FPGA module, the standby control unit provides a stop signal for the gating clock unit to cut off a clock signal between the clock source and the backward projection calculation kernel, and the backward projection calculation kernel stops working, so that the power consumption can be reduced; when the first FPGA module receives echo sampling data or the second FPGA module receives echo data, the standby control unit provides an enabling signal for the gated clock unit to control the gated clock unit to act, so that the clock source provides a clock signal to the projection computation kernel backwards, and the backward projection computation kernel works according to the clock signal. According to the embodiment, the power consumption of the backward projection computing kernel is controlled in a dynamic clock gating mode, and the power consumption is favorably reduced.
In this embodiment, the memory management unit is further configured to perform coherent accumulation on the imaging intermediate data. Referring to fig. 10, fig. 10 shows a logic relationship of functional modules for coherent accumulation, where a specific calculation method of an accumulator can refer to embodiment 1, and this embodiment is not described again, and as can be seen from fig. 10, in this embodiment, transmission and accumulation of imaging intermediate data are processed in parallel by a memory management unit, so that data processing efficiency can be improved, and therefore, a back-projection imaging speed is increased.
Example 3
In this embodiment, the backward projection imaging architecture of embodiment 2 is verified by taking an Ultrascale plus series FPGA product of XILINX (saint) as an example. The first FPGA module and the second FPGA module both adopt FPGA chips of the model VU 37P. 16 backward projection computation kernels (kernel) are integrated in the FPGA chip of the type, 1536 equivalent high concurrent back-projection computation basic units (BP core) are integrated, the working main frequency of the FPGA chip of the type is 420MHz, 2800 ten thousand logic units are possessed, and 8GB high-bandwidth storage units are configured.
In the present embodiment, the calculation time of the back projection imaging is obtained by equation (9), wherein the meaning of the variables in equation (9) refers to table 3.
TABLE 3
In this embodiment, the calculation power evaluation may be calculated according to equation (10), and the variable description in equation (10) is shown in table 4.
TOPS＝(kernel_num·kernel_PE·complex_mult_OPS+Accmulate_OPS)·fmax(10)
TABLE 4
In this embodiment, the power consumption of the second FPGA module in different operating modes is counted, which is detailed in table 5.
TABLE 5
Under the FPGA hardware architecture of the embodiment, the calculation time of the back projection imaging of the second FPGA module is 630ms, the calculation power reaches INT16 TOPS 10.3, the power consumption in the standby state is reduced to 30W, and the effects of quick imaging and low power consumption can be achieved.
Example 4
The present embodiment discloses an apparatus comprising the backprojection imaging architecture of embodiment 2. The pipeline design of the hardware framework based on the FPGA module is more flexible, the FPGA module can be internally configured with corresponding logic frameworks according to different functional requirements, corresponding functions are realized on different FPGA modules, the functions are absorbed, the flexible reconfiguration characteristics of the FPGA module can be fully utilized to maintain and manage the functions and the frameworks of the first FPGA module and the second FPGA module respectively, the FPGA module and the second FPGA module are matched with each other and can be independently designed, and the design difficulty is favorably reduced.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.
Claims (11)
1. A back projection fast imaging architecture design method based on FPGA is characterized in that the following steps are executed in a pipeline mode:
acquiring imaging grid information and echo data subjected to distance direction pulse compression processing, and loading the echo data into an on-chip cache;
generating pixel point data of the imaging grid according to the imaging grid information;
performing bistatic distance operation of the radar array element according to the pixel point data to obtain bistatic distance data;
calling the bistatic distance data and the echo data to perform parallel processing of back projection operation so as to obtain imaging intermediate data;
and carrying out coherent accumulation on the imaging intermediate data to obtain imaging result data.
2. The method as claimed in claim 1, wherein the on-chip buffer is divided into a first buffer and a second buffer, the first buffer is used for accessing the echo data in ping-pong access mode, and the second buffer is used for accessing the imaging intermediate data in ping-pong access mode.
3. The FPGA-based back projection fast imaging architecture design method as claimed in claim 2, wherein the first cache region accesses the echo data in a way of performing physical address coding on two-dimensional quadrants of a radar receiving array element and a radar transmitting array element, and the second cache region accesses the imaging intermediate data in a way of interleaving addresses.
4. The FPGA-based back projection fast imaging architecture design method as claimed in claim 1, wherein a plurality of cascaded back projection computation cores are adopted to perform the back projection computation, the back projection computation cores comprise a plurality of parallel cascaded back projection computation basic units, and the bistatic distance data is stored in a cache of the back projection computation basic units in a crossed manner.
5. The FPGA-based back projection fast imaging architecture design method as claimed in claim 4, wherein each of the back projection basic units comprises a third buffer area and a fourth buffer area, the third buffer areas of the back projection basic units in the same column are used for storing the same receiving direction monostatic distance data, the fourth buffer areas of the back projection basic units in the same row are used for storing the same transmitting direction monostatic distance data, the receiving direction monostatic distance data is used for representing the distance between a radar receiving array element in the bistatic distance data and a corresponding pixel point, and the transmitting direction monostatic distance data is used for representing the distance between a radar transmitting array element in the bistatic distance data and a corresponding pixel point.
6. The FPGA-based back projection fast imaging architecture design method as claimed in claim 5, wherein each back projection operation basic unit further comprises a fifth buffer area for storing the echo data required for the back projection operation.
7. The FPGA-based back projection fast imaging architecture design method as claimed in any one of claims 4 to 6, wherein a dynamic clock gating manner is adopted to perform power consumption control on the back projection computation kernel.
8. An FPGA architecture, comprising:
a high bandwidth storage unit;
the bus control unit is used for acquiring imaging grid information and echo data compressed to the pulse through the distance;
the memory management unit is used for receiving the echo data and storing the echo data to the high-bandwidth storage unit;
the pixel grid generation control unit is used for receiving the imaging grid information and generating pixel point data according to the imaging grid information;
the bistatic distance calculation unit is used for performing bistatic distance calculation of the radar array element according to the pixel point data to obtain bistatic distance data;
the backward projection calculation kernel is used for calling the bistatic distance data and the echo data to perform parallel processing of backward projection calculation so as to obtain imaging intermediate data;
the memory management unit is further configured to perform coherent accumulation on the imaging intermediate data to obtain imaging result data.
9. A backprojection imaging architecture, comprising:
the system comprises a first FPGA module, a second FPGA module and a third FPGA module, wherein the first FPGA module is used for acquiring echo sampling data input from the outside, performing range-wise pulse compression processing on the echo sampling data to acquire echo data and extracting imaging grid information from the echo data;
and the second FPGA module is connected with the first FPGA module through an inter-chip interconnection bus, and is used for receiving the echo data and the imaging grid information, performing backward projection imaging processing according to the echo data and the imaging grid information to obtain imaging result data, and returning the imaging data to the first FPGA module for outputting the imaging result data to the outside.
10. The architecture for backprojection imaging according to claim 9, wherein the second FPGA module is configured with the FPGA architecture of claim 8.
11. A device comprising the backprojection imaging architecture of claim 9 or 10.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106651740A (en) * | 2016-11-29 | 2017-05-10 | 中国科学院声学研究所 | FPGA-based ultrasonic total data focusing quick imaging method and system |
| US20190049575A1 (en) * | 2017-08-08 | 2019-02-14 | U.S. Army Research Laboratory Attn: Rdrl-Loc-I | Passive non-linear synthetic aperture radar and method thereof |
| US20200025855A1 (en) * | 2017-08-08 | 2020-01-23 | U.S. Army Research Laboratory Attn: Rdrl-Loc-I | Method and apparatus for providing a passive transmitter based synthetic aperture radar |
| CN111025293A (en) * | 2019-11-26 | 2020-04-17 | 北京遥测技术研究所 | Efficient FPGA real-time imaging system applied to small satellite SAR |
-
2021
- 2021-04-30 CN CN202110482828.5A patent/CN113156431B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106651740A (en) * | 2016-11-29 | 2017-05-10 | 中国科学院声学研究所 | FPGA-based ultrasonic total data focusing quick imaging method and system |
| US20190049575A1 (en) * | 2017-08-08 | 2019-02-14 | U.S. Army Research Laboratory Attn: Rdrl-Loc-I | Passive non-linear synthetic aperture radar and method thereof |
| US20200025855A1 (en) * | 2017-08-08 | 2020-01-23 | U.S. Army Research Laboratory Attn: Rdrl-Loc-I | Method and apparatus for providing a passive transmitter based synthetic aperture radar |
| CN111025293A (en) * | 2019-11-26 | 2020-04-17 | 北京遥测技术研究所 | Efficient FPGA real-time imaging system applied to small satellite SAR |
Non-Patent Citations (2)
| Title |
|---|
| 孙敏敏: "Backprojection成像多核并行计算系统设计", 《中国优秀博硕士学位论文全文数据库(硕士) 信息科技辑》 * |
| 张佳琪: "小卫星SAR实时成像技术研究", 《中国优秀博硕士学位论文全文数据库(硕士) 基础科学辑》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114397657A (en) * | 2021-12-20 | 2022-04-26 | 星测未来科技(北京)有限责任公司 | On-orbit real-time SAR imaging method |
| CN114397657B (en) * | 2021-12-20 | 2024-04-09 | 星测未来科技(北京)有限责任公司 | On-orbit real-time SAR imaging method |
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