CN1131557C - Process for mfg. micromechanical inductor with suspended structure on single surface of silicon substrate - Google Patents
Process for mfg. micromechanical inductor with suspended structure on single surface of silicon substrate Download PDFInfo
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- CN1131557C CN1131557C CN 01130793 CN01130793A CN1131557C CN 1131557 C CN1131557 C CN 1131557C CN 01130793 CN01130793 CN 01130793 CN 01130793 A CN01130793 A CN 01130793A CN 1131557 C CN1131557 C CN 1131557C
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Abstract
The present invention belongs to the technical field of making semiconductor devices and integrated circuits. The present invention comprises preparing a chip, and cleaning; oxidizing by heat; depositing a silicon nitride barrier layer; photoengraving for the first time, and etching the silicon nitride barrier layer; etching silicon dioxide; oxidizing an anode, and forming porous silicon; removing the silicon dioxide and silicon nitride; depositing a silicon dioxide support film; densifying; sputtering aluminium on the silicon chip; photoengraving for the second time, corroding the aluminium, and forming a lower layer aluminum wire; depositing a silicon nitride insulating layer; photoengraving for the third time, and etching the silicon nitride insulating layer; sputtering the aluminum as upper layer metal on an insulating film; photoengraving for the fourth time, corroding the aluminum, and forming an upper layer aluminum wire; alloying; photoengraving for the fifth time, and forming release holes; releasing the porous silicon; cleaning and baking. The method can make MEMS electrical inductors with suspension structures, and can also make filters, oscillators, etc. with the suspension structures. At the same time, an integrated CMOS compatible technique can greatly enhances the system integration level, lower the system cost, and can be widely used.
Description
Technical field
The invention belongs to semiconductor device and production of integrated circuits technical field, particularly the manufacture method of single surface of silicon substrate processing micromechanical inductor with suspended structure.
Background technology
Since the nineties, the integrated level of wireless telecommunication system improves constantly, and utilizes silicon technology to make monolithic radio frequency integrated circuit (RFIC), has become the research focus of present IC.Inductance is the critical elements in the wireless communication system, and its quality has directly determined the performance of entire circuit.Extensively adopt CMOS technology at present in the integrated circuit, various technological parameters, procedure of processing have formed industry standard.If adopt the CMOS standard technology that inductance is integrated in the silicon integrated circuit, can realize the compatibility of radio-frequency (RF) passive element and cmos circuit easily, but because the ghost effect of silicon substrate, the inductance value that obtains, Q value are all very limited, are unfavorable for the raising of entire system performance.The silicon RFIC that develops into of micromechanics (MEMS) technology provides new solution, has become a key areas in present radio circuit, the device research.Owing to adopt technologies such as sacrifice layer, deep erosion, the silicon micro mechanical planar spiral inductor is the various ghost effects in the control integrated circuit effectively, obviously improve the performance of inductance, people have developed the micromechanics planar spiral inductor of different structure, different manufacture methods.
At present, the micromechanical process technology of comparative maturity mainly contains: anisotropic body silicon corrosion technology, dry etching technology, wafer bonding (bonding) technology, thick positive photoresist lithographic technique, sacrificial layer technology or the like.These technologies of suitable employing can be produced well behaved micro mechanical device, but owing to exist and the incompatible step of CMOS technology in these silicon micro-machining technologies, are unfavorable for that the monolithic of system is integrated.
Had the snail structure micro-mechanical inductance that adopts anisotropic body silicon caustic solution to make at present, its structure as shown in Figures 1 and 2, its manufacture method is as follows.
(1) at the positive deposit one deck of silicon chip dielectric film, as suspension structure support membrane 1; (2) adopt bulk silicon etching technology to erode away cavity 6 from the silicon chip back side, only stay the insulation support membrane; (3) at insulating barrier 4, the contact hole 3 of levels line, the helical structure inductance upper coil 5 made successively on the support membrane between helical structure inductance lower metal wiring 2, the helical structure levels line; (4) make cmos circuit 7 (not doing expression in detail) in the position of not removing silicon substrate 8 with standard technology, realize the system integration.
The silicon substrate of this structure below the removal coil eliminated the loss of substrate, thereby reduces ghost effect, realizes that simultaneously the monolithic of passive component and active C MOS circuit is integrated.Its advantage is by thorough removal substrate, and that the performance of inductance can be done is very good, obtains high performance element.Its shortcoming is that technology is too complicated, needs two-sided processing, and technology difficulty is big.Because bulk silicon etching technology and CMOS compatibility are bad, must carry out excellent protection to silicon CMOS circuit in the manufacturing process, otherwise will cause the inefficacy of system simultaneously.These have all determined this design to be difficult to be widely used.
Summary of the invention
The objective of the invention is for overcoming the weak point of prior art, a kind of manufacture method of single surface of silicon substrate processing micromechanical inductor with suspended structure is proposed, adopt the porous silicon sacrificial layer technology, on silicon substrate, produce suspension structure, can produce and the compatible fully inductance element that guarantees circuit performance simultaneously of CMOS technology with single face technology.
The present invention includes following steps:
1) be equipped with sheet, cleaning: the silicon chip that with thickness is 400-600 μ m, single-sided polishing is as substrate, and the method that adopts sulfuric acid+hydrogen peroxide to boil is cleaned back rinsed with deionized water and oven dry;
2) oxidation: ready silicon chip is put into oxidation furnace, 1000-1100 ℃ down with the purity oxygen reaction, at the silicon dioxide of the burnishing surface generation 45-55nm of silicon chip as the destressing layer;
3) deposit silicon nitride barrier layer: adopting the method for chemical vapor deposition, is the silicon nitride of 180-220nm at the positive formation of silicon chip thickness, as the barrier layer of subsequent technique " anodic oxidation ";
4) photoetching for the first time, the etch silicon nitride barrier layer: to deposit the silicon chip of silicon nitride carry out photoetching, exposing needs the silicon nitride region removed, carries out etching then, removes and treats the silicon nitride in anodic oxidation zone, exposes following silicon dioxide layer;
5) etching silicon dioxide: the silicon dioxide that exposes is removed, exposed silicon substrate, then photoresist is removed;
6) anodic oxidation, form porous silicon: carry out anodic oxidation in 15～25% hydrofluoric acid solution, the current density of oxidation is 40 ± 5mA/cm
2, be the porous silicon of 15-30 μ m at the positive generation of the silicon chip that exposes thickness;
7) remove silicon dioxide, silicon nitride: the silicon chip that will generate porous silicon placed 8%～10% hydrofluoric acid solution soak at room temperature 2～3 hours, thoroughly remove the silicon dioxide and the silicon nitride of silicon chip surface, the purpose of this operation is to improve contacting of film and silicon substrate in the subsequent technique, improves the total quality of device;
8) deposit silicon dioxide: at silicon chip front deposition thickness is the silicon dioxide of 500 ± 50nm, as the support film of suspension structure;
9) densification: with deposit the silicon chip behind the silica membrane in oxygen, be heated to 900～1000 ℃, kept 20～30 minutes, carry out densification, improving the mechanical property of silica membrane, improve the quality of film;
10) sputtered aluminum on silicon chip: according to the requirement of electrical design parameter, sputter thickness is the aluminium of 400～600nm on silicon chip, as lower metal;
11) photoetching for the second time, corrosion aluminium forms lower floor's aluminum steel: at first form certain photoresist figure that shields on the aluminium surface, corrode then, form the lower floor's aluminum steel figure that meets design requirement, after corrosion finishes photoresist is removed;
12) deposit silicon nitride insulating barrier: the method for using plasma chemical vapor deposition, at the silicon nitride of the positive deposit 300nm ± 50nm of silicon chip, as the insulating barrier between the double layer of metal;
13) photoetching for the third time, etch silicon nitride insulating barrier: at the contact hole that etches on the silicon nitride dielectric layer between double layer of metal, so that carry out the interconnected of double layer of metal;
14) sputtered aluminum on insulating barrier, as the upper strata metal: according to the requirement of circuit design parameter, sputter thickness is the aluminium of 1～5 μ m;
15) the 4th photoetching, corrosion aluminium forms the upper strata aluminum steel: adopts photoetching, the burn into identical with the 11st step process technology of removing photoresist, aluminium is corroded the upper strata aluminum steel figure that formation meets design requirement;
16) alloy: the silicon chip that will form double-level-metal places 400～500 ℃ of environment, feeds protective gas simultaneously, heats 25 ± 5 minutes, carries out alloy, to improve the contact of double layer of metal aluminium, reduces contact resistance, improves inductance performance;
17) the 5th photoetching forms release aperture: adopt and identical photoetching and etching technics of the 4th, the 5th step, form some etch pits, expose porous silicon, so that carry out the release of porous silicon, at last photoresist is removed;
18) discharge porous silicon: silicon chip is placed the tetramethyl ammonium hydroxide solution that mixes silica flour and ammonium persulfate, in water-bath, heated 15～30 minutes, carry out the release of porous silicon, form suspension structure;
19) clean, dry: the silicon chip of making is soaked, cleans to be placed on not to be higher than in 100 ℃ of baking ovens and dry with a large amount of deionized waters.
Protective gas in above-mentioned the 16th step can adopt nitrogen or nitrogen hydrogen gas mixture or other protective gas.
A kind of example of the mass concentration of each composition is in the solution in above-mentioned the 18th step: Tetramethylammonium hydroxide 5%, silica flour 1.6%, ammonium persulfate 0.6%.
Advantage of the present invention:
1, adopt single-sided process technology fully, the variety of issue (as aligning, dual surface lithography etc.) of having avoided two-sided processing to bring.
2, the proposition of novelty adopt the suspension MEMS structure of porous silicon sacrifice layer, solved the contradiction of removing between substrate and the difficulty of processing.
3, the thickness of porous silicon, character can be controlled by the setting of anodic oxidation parameter, can be used for the element of different structure, different purposes.
4, adopt special wet etching liquid, can when discharging the porous silicon sacrifice layer, not corrode aluminium, this corrosive liquid alkali-free metal ion of while, complete and CMOS process compatible.
Adopt this technological process, not only can produce suspension structure MEMS inductance, and can make the filter that adopts similar suspension structure, oscillator etc., for the extensive use of Microwave MEMS device is laid a good foundation.Simultaneously, the CMOS compatible technology can improve the integrated level of system greatly completely, reduces system cost, is expected to be used widely.
Description of drawings:
The suspension structure spiral inductance structural profile schematic diagram of Fig. 1 for adopting existing technology to make.
Suspension structure spiral inductance and the circuit application schematic diagram thereof of Fig. 2 for adopting existing technology to make.
Fig. 3 makes the processing step embodiment flow chart of suspension structure inductance for adopting the inventive method, wherein:
Fig. 3 (1) is for being equipped with the substrate that obtains after sheet, the cleaning;
Fig. 3 (2) is the profile after the oxidation;
Fig. 3 (3) is the profile after the deposit silicon nitride;
Fig. 3 (4) crosses profile behind the silicon nitride for etching;
Fig. 3 (5) crosses profile behind the silicon dioxide for etching;
Fig. 3 (6) forms profile behind the porous silicon for anodic oxidation;
Fig. 3 (7) is the profile behind removal silicon dioxide, the silicon nitride;
Fig. 3 (8) is the profile behind the vapor deposition silica membrane;
Fig. 3 (9) is for carrying out the profile (identical with (8)) after the densification;
Fig. 3 (10) for sputter the profile behind the lower metal aluminium;
Fig. 3 (11) is for to have carried out the profile after the etching to aluminium;
Fig. 3 (12) is the profile behind the deposit silicon nitride insulating barrier;
Fig. 3 (13) crosses silicon nitride profile afterwards for etching;
Fig. 3 (14) is the profile behind sputter upper strata metallic aluminium on the dielectric film;
Fig. 3 (15) is for carrying out the profile after the etching to the upper strata metallic aluminium;
Fig. 3 (16) is the profile (identical with (15)) behind the alloy;
Fig. 3 (17) crosses silicon nitride, silicon dioxide for etching, the profile behind the formation porous silicon etch pit;
Fig. 3 (18) is the profile of porous silicon after discharging.
The suspension structure induction structure schematic diagram of Fig. 4 for adopting the present embodiment method to make.
Fig. 5 is a kind of anodic oxidation special equipment structural representation that is used for the present embodiment method.
Embodiment
The manufacture method embodiment of a kind of single surface of silicon substrate processing micromechanical inductor with suspended structure of the present invention, as shown in Figure 3.Among the figure, layers of material is respectively: a is a silicon substrate; B is the silicon dioxide layer that thermal oxidation obtains; C is the silicon nitride that low-pressure vapor phase deposit (LPCVD) obtains; D is the porous silicon that anodic oxidation generates; The silicon dioxide support membrane that e obtains for the low-pressure vapor phase deposit; F is a lower metal aluminium; The silicon nitride dielectric layer that g obtains for the plasma vapor deposition; H is the contact hole between the double layer of metal; I is the upper strata metallic aluminium; J is the porous silicon etch pit.
Present embodiment making flow process is as follows:
1) be that the N type height of 550 μ m single-sided polishings mixes up silicon chip a (resistivity is 0.01 Ω cm) as substrate with thickness, this silicon chip is put into the dioxysulfate water mixed solution (according to the concentrated sulfuric acid: the volume ratio configuration of hydrogen peroxide=4: 1) boiled rinsed with deionized water and oven dry then 15 minutes.Shown in Fig. 3 (1).
2) silicon chip is put into oxidation furnace, 1050 ℃ down with purity oxygen reaction 15 minutes, at the positive generation of silicon chip 49.3nm silicon dioxide b.Shown in Fig. 3 (2).
3) adopt low-pressure chemical vapor phase deposition (LPCVD) method, 700 ℃ of following deposits 50 minutes, positive to form thickness be the silicon nitride c of 200nm at silicon chip, as the barrier layer of subsequent technique " anodic oxidation ".Shown in Fig. 3 (3).
4) in deposit the silicon chip front of silicon nitride coat negative photoresist, rely on the reticle that designs to expose as mask.On reticle, the light transmitting property difference of zones of different because negative photoresist can form the material that is difficult for being dissolved in developer solution under illumination, therefore places developer solution with whole silicon wafer after exposure, and the photoresist of unexposed area is dissolved.Like this, a part of silicon nitride comes out, and all the other silicon nitrides are protected by photoresist.Be positioned in reactive ion etching (RIE) equipment after the silicon chip drying that photoetching finishes, the silicon nitride of exposure is etched, and exposes following silicon dioxide, by the silicon nitride of photoresist protection place not with these ionic reactions.Shown in Fig. 3 (4).
5) after silicon nitride etch finishes, silicon chip is placed hydrofluoric acid-ammonium fluoride cushioning liquid (abbreviating BHF solution as), the silicon dioxide of exposure and BHF solution reaction are removed, and expose silicon substrate.With fuming nitric aicd photoresist is removed then.Shown in Fig. 3 (5).
6) in 20% hydrofluoric acid solution, carry out anodic oxidation, at the positive porous silicon d that generates of the silicon chip that is exposing.The current density of oxidation is 40mA/cm
2, in 10 minutes reaction time, having formed thickness on the reacted silicon chip is the porous silicon of 15 μ m.Reaction finishes a large amount of washed with de-ionized water in back, and oven dry.Shown in Fig. 3 (6).
7) silicon chip was placed 10% hydrofluoric acid solution soak at room temperature 2 hours 15 minutes, thoroughly remove the silicon dioxide and the silicon nitride of silicon chip surface.In immersion process, determine whether that by range estimation and microscopic examination reaction thoroughly.Shown in Fig. 3 (7).
8) method (LPCVD) of employing low-pressure chemical vapor phase deposition is the silicon dioxide e of 530nm at the positive formation of silicon chip thickness, as the support film of suspension structure.Shown in Fig. 3 (8).
9) silicon chip is heated to 960 ℃ in purity oxygen, kept 30 minutes, carry out densification.The purpose of this technology is to improve the mechanical property of silica membrane, improves the quality of film, and the structure and the profile of device do not change.Shown in Fig. 3 (9).
10) sputter 500nm aluminium is as lower metal f.Shown in Fig. 3 (10).
11) in sputter the silicon chip front of aluminium coat negative photoresist, rely on the reticle that designs to expose as mask, form certain photoresist figure that shields at aluminium film surface.Place phosphoric acid to corrode silicon chip then.In the place that is not subjected to the photoresist protection, aluminium and phosphatase reaction are corroded, and all the other local aluminium are corroded, and form the lower floor's aluminum steel figure that meets design requirement.For accelerating corrosion rate, will corrode container and place Vltrasonic device, etching time is 5 minutes.After finishing, corrosion photoresist is removed with fuming nitric aicd.Shown in Fig. 3 (11).
12) method of using plasma chemical vapor deposition (PECVD) is at the silicon nitride g of the positive deposit 310nm of silicon chip, as the insulating barrier between the double layer of metal aluminium.Shown in Fig. 3 (12).
13) adopt the photoetching process identical, form certain photoresist figure that shields in silicon nitride surface with the 4th step process.The silicon chip that photoetching is finished places reactive ion etching equipment to react, etching 6 minutes, the silicon nitride of exposure is etched, and by the silicon nitride of photoresist protection place not with these ionic reactions.Like this, according to design configuration, obtain the contact hole h between the double layer of metal, so that carry out the interconnected of double layer of metal.After etching finishes, use fuming nitric aicd that photoresist is removed.Shown in Fig. 3 (13).
14) sputter 1000nm aluminium is as upper strata metal i.Shown in Fig. 3 (14).
15) adopt photoetching, the burn into identical technology of removing photoresist, the upper strata aluminum steel figure that formation meets design requirement with the 11st step process.During etching, will corrode container and place Vltrasonic device, etching time is 10 minutes.After finishing, corrosion photoresist is removed with fuming nitric aicd.Shown in Fig. 3 (15).
16) silicon chip that will form double-level-metal places 420 ℃ of environment, feeds hydrogen simultaneously, (its volume ratio is H to the nitrogen mixture body
2: N
2=1: 10) heating is 25 minutes, carries out alloy.The purpose of this technology is to improve the contact of double layer of metal aluminium, reduces contact resistance, improves electric property, and the structure and the profile of device do not change.Shown in Fig. 3 (16).
17) adopt photoetching and the etching technics identical with the 4th step process, at first form certain photoresist figure at silicon chip surface, with the silicon nitride of reactive ion etching equipment etching as dielectric film, expose silicon dioxide, use the identical caustic solution of the 5th step process then,, so just formed etch pit j with hydrofluoric acid-ammonium fluoride cushioning liquid corrode silicon dioxide support membrane, expose porous silicon, so that carry out the release of porous silicon.With fuming nitric aicd photoresist is removed at last.Shown in Fig. 3 (17).
18) silicon chip is placed mix silica flour and ammonium persulfate tetramethyl ammonium hydroxide solution (mass concentration of this each composition of solution: Tetramethylammonium hydroxide 5%, silica flour 1.6%, ammonium persulfate 0.6%), heating is 15 minutes in 85 ℃ of water-baths, discharge porous silicon, form suspension structure.Shown in Fig. 3 (18).
19) silicon chip of making is soaked, cleans with a large amount of deionized waters, place 80 ℃ of baking ovens to dry then.
The suspension structure induction structure that the employing present embodiment is made as shown in Figure 4.Wherein, 1 is the suspension structure support membrane; 2 is the wiring of helical structure inductance lower metal; 3 is the contact hole of levels line; 4 is the insulating barrier between the helical structure levels line; 5 is helical structure inductance upper coil; 8 be silicon substrate (1～5 and 8 all with Fig. 1,2 in corresponding structure identical); 9 is the cavity that obtains behind the porous silicon sacrifice layer corrosion, and 10 is the porous silicon etch pit.Compare with the method for above-mentioned prior art, the difference of two kinds of structures is the inductance that the inventive method is made owing to adopted single face technology, the silicon substrate corrosion is not worn.
In the present embodiment, adopted the anodic oxidation equipment of a special use, its structural representation as shown in Figure 5.This anodic oxidation container is made by polytetrafluoroethylene, and silicon chip 13 places in the hole of fixed head 12, and sealing ring 11 and fixed head 12 are divided into two parts with entire container, and a platinum electrode 14 is respectively placed in both sides.During anode reaction, two platinum electrodes connect the positive pole and the negative pole of D.C. regulated power supply respectively, because fixed head and sealing ring separate both sides anode reaction solution (hydrofluoric acid) 15 fully, the unique path of electric current is to pass silicon chip through solution.Like this, the silicon chip of facing negative electrode becomes the anode of electrochemical reaction, and anodic oxidation takes place, and generates porous silicon.Single-sided process has been accomplished in this design fully, has reduced technology difficulty, has improved compatibility.
Claims (1)
1, a kind of manufacture method of single surface of silicon substrate processing micromechanical inductor with suspended structure may further comprise the steps:
1) be equipped with sheet, cleaning: the silicon chip that with thickness is 400-600 μ m, single-sided polishing is as substrate, and the method that adopts sulfuric acid+hydrogen peroxide to boil is cleaned back rinsed with deionized water and oven dry;
2) thermal oxidation: ready silicon chip is put into oxidation furnace, 1000-1100 ℃ down with the purity oxygen reaction, at the silicon dioxide of the burnishing surface generation 45-55nm of silicon chip as the destressing layer;
3) deposit silicon nitride barrier layer: adopting the method for chemical vapor deposition, is the silicon nitride of 180-220nm at the positive formation of silicon chip thickness, as the barrier layer of subsequent technique " anodic oxidation ";
4) photoetching for the first time, the etch silicon nitride barrier layer: to deposit the silicon chip of silicon nitride carry out photoetching, exposing needs the silicon nitride region removed, carries out etching then, removes and treats the silicon nitride in anodic oxidation zone, exposes following silicon dioxide layer;
5) etching silicon dioxide: the silicon dioxide that exposes is removed, exposed silicon substrate, then photoresist is removed;
6) anodic oxidation, form porous silicon: carry out anodic oxidation in 15～25% hydrofluoric acid solution, the current density of oxidation is 40 ± 5mA/cm
2, be the porous silicon of 15-30 μ m at the positive generation of the silicon chip that exposes thickness;
7) remove silicon dioxide, silicon nitride: the silicon chip that will generate porous silicon placed 8%～10% hydrofluoric acid solution soak at room temperature 2～3 hours, thoroughly remove the silicon dioxide and the silicon nitride of silicon chip surface, contact the total quality of raising device with what improve film and silicon substrate in the subsequent technique;
8) deposit silicon dioxide: at silicon chip front deposition thickness is the silicon dioxide of 500 ± 50nm, as the support film of suspension structure;
9) densification: with deposit the silicon chip behind the silica membrane in oxygen, be heated to 900～1000 ℃, kept 20～30 minutes, carry out densification, improving the mechanical property of silica membrane, improve the quality of film;
10) sputtered aluminum on silicon chip: according to the requirement of electrical design parameter, sputter thickness is the aluminium of 400～600nm on silicon chip, as lower metal;
11) photoetching for the second time, corrosion aluminium forms lower floor's aluminum steel: at first form certain photoresist figure that shields on the aluminium surface, corrode then, form the lower floor's aluminum steel figure that meets design requirement, after corrosion finishes photoresist is removed;
12) deposit silicon nitride insulating barrier: the method for using plasma chemical vapor deposition, at the silicon nitride of the positive deposit 300nm ± 50nm of silicon chip, as the insulating barrier between the double layer of metal;
13) photoetching for the third time, etch silicon nitride insulating barrier: at the contact hole that etches on the silicon nitride dielectric layer between double layer of metal, so that carry out the interconnected of double layer of metal;
14) sputtered aluminum on insulating barrier, as the upper strata metal: according to the requirement of circuit design parameter, sputter thickness is the aluminium of 1～5 μ m;
15) the 4th photoetching, corrosion aluminium forms the upper strata aluminum steel: adopts photoetching, the burn into identical with the 11st step process technology of removing photoresist, aluminium is corroded the upper strata aluminum steel figure that formation meets design requirement;
16) alloy: the silicon chip that will form double-level-metal places 400～500 ℃ of environment, feeds protective gas simultaneously, heats 25 ± 5 minutes, carries out alloy, to improve the contact of double layer of metal aluminium, reduces contact resistance, improves inductance performance;
17) the 5th photoetching forms release aperture: adopt and identical photoetching and etching technics of the 4th, the 5th step, form some etch pits, expose porous silicon, so that carry out the release of porous silicon, at last photoresist is removed;
18) discharge porous silicon: silicon chip is placed the tetramethyl ammonium hydroxide solution that mixes silica flour and ammonium persulfate, in water-bath, heated 15～30 minutes, carry out the release of porous silicon, form suspension structure;
19) clean, dry: the silicon chip of making is soaked, cleans to be placed on not to be higher than in 100 ℃ of baking ovens and dry with a large amount of deionized waters.
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