CN113141176A - Automatic configuration output circuit - Google Patents

Automatic configuration output circuit Download PDF

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Publication number
CN113141176A
CN113141176A CN202010055349.0A CN202010055349A CN113141176A CN 113141176 A CN113141176 A CN 113141176A CN 202010055349 A CN202010055349 A CN 202010055349A CN 113141176 A CN113141176 A CN 113141176A
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China
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circuit
output
voltage
current
input
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CN202010055349.0A
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叶星炯
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Johnson Controls Air Conditioning and Refrigeration Wuxi Co Ltd
Johnson Controls Technology Co
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Johnson Controls Air Conditioning and Refrigeration Wuxi Co Ltd
Johnson Controls Technology Co
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Priority to CN202010055349.0A priority Critical patent/CN113141176A/en
Publication of CN113141176A publication Critical patent/CN113141176A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection

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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Amplifiers (AREA)

Abstract

The invention provides an output circuit capable of being automatically configured, which comprises a voltage driving circuit, a current driving circuit, an isolation circuit and an output stage circuit, wherein the output end of the voltage driving circuit is connected with the input end of the output stage circuit, the output end of the current driving circuit is connected with the input end of the output stage circuit through the isolation circuit, and the isolation circuit is provided with an input end and an output end. The output circuit of the present invention can automatically select one of the voltage drive circuit and the current drive circuit to operate to drive the device in voltage mode or in current mode according to the characteristics of the device connected to the output circuit. In addition, the output circuit has the advantages of simple structure, fewer components, smaller occupied substrate space, low price and no need of current compensation.

Description

Automatic configuration output circuit
Technical Field
The present invention relates to an output circuit, and more particularly, to an output circuit that can automatically switch between two different modes of output.
Background
The operation of various devices in industrial control is driven by an output circuit. Representative devices include valves, fans, actuators, and the like. Some devices in industrial control require voltage-based output for driving and some require current-based output for driving, due to the characteristics of the devices themselves. In order to facilitate manufacturing, an output circuit has been provided which includes both a voltage-based output and a current-based output. In actual operation, the output circuit may select either a voltage-based output or a current-based output depending on the characteristics of the device.
Disclosure of Invention
In order to solve the above problems, the present invention provides an output circuit capable of automatic configuration, which can select a voltage-based output or a current-based output according to the characteristics of a device. In addition, the output circuit has the advantages of simple structure, fewer components, smaller occupied substrate space, low price and no need of current compensation.
According to one aspect of the present invention, there is provided an automatically configurable output circuit, the output circuit comprising:
a voltage drive circuit configured to generate a voltage drive signal, the voltage drive circuit having an output;
a current drive circuit configured to generate a current drive signal, the current drive circuit having an output;
an isolation circuit;
the output stage circuit is provided with an input end, the output end of the voltage driving circuit is connected with the input end of the output stage circuit, and the output end of the current driving circuit is connected with the input end of the output stage circuit through the isolating circuit.
According to another aspect of the present invention, there is provided an automatically configurable output circuit, the output circuit comprising:
a voltage drive circuit configured to generate a voltage drive signal, the voltage drive circuit having an output;
a current drive circuit configured to generate a current drive signal, the current drive circuit having an output;
an isolation circuit;
the output stage circuit is provided with an input end, the output end of the voltage driving circuit is connected with the input end of the output stage circuit through the isolation circuit, and the output end of the current driving circuit is connected with the input end of the output stage circuit.
In one embodiment, the isolation circuit comprises a two-terminal isolation circuit. In another embodiment, the isolation circuit comprises a unidirectional isolation circuit. In a further embodiment, the isolation circuit is a diode.
Drawings
FIG. 1A illustrates a block diagram configuration of one embodiment of an output circuit in accordance with the present invention;
FIG. 1B illustrates a block diagram configuration of another embodiment of an output circuit according to the present invention;
FIG. 2A shows details of a circuit diagram of exemplary various modules according to one embodiment of the output circuit 100 shown in FIG. 1A;
FIG. 2B illustrates details of a circuit diagram of exemplary various modules in accordance with one embodiment of the output circuit 100 illustrated in FIG. 1B;
fig. 3A shows a specific circuit configuration of the voltage division shift circuit 201 when the input signal Sin is an analog signal;
fig. 3B shows a specific circuit configuration of the voltage-division shifting circuit 201 when the input signal Sin is a varying PWM signal;
fig. 4A shows a specific structure of the offset control circuit 202; and
fig. 4B shows another specific structure of the offset control circuit 202.
Detailed Description
Various embodiments of the present invention will now be described with reference to the accompanying drawings, which form a part hereof. It should be understood that wherever possible, the same or similar reference numbers used in the present application refer to the same or like parts.
Fig. 1A is a block diagram configuration 100 of one embodiment of an output circuit according to the present invention, and fig. 1B is a block diagram configuration 100 of another embodiment of an output circuit according to the present invention.
As shown in fig. 1A, the output circuit 100 of the auto configuration includes an offset configuration circuit 101, a voltage drive circuit 102, a current drive circuit 103, an isolation circuit 104, and an output stage circuit 105. The functions of the respective modules, and the connection and cooperation between the respective modules will be described below with reference to fig. 1A.
In fig. 1A, when the voltage driving circuit 102 operates together with the output stage circuit 105 to control the voltage output to the output device 106 to drive the output device 106, it is referred to as a voltage type driving the output device 106; when the current driving circuit 103 operates together with the output stage circuit 105 to control the current output to the output device 106 to drive the output device 106, it is referred to as a current mode driving the output device 106. In the present application, when the output device 106 is connected to the output stage circuit 105, one of the voltage drive circuit 102 and the current drive circuit 103 is automatically selected to operate with the output stage circuit 105 to drive the output device 106 based on the characteristics (e.g., resistance) of the output device 106 and the feedback received from the output stage circuit 105. The present application is therefore directed to automatically selecting either a voltage mode driven output device 106 or a current mode driven output device 106.
In order to realize automatic selection of the voltage-mode drive output device 106 or the current-mode drive output device 106, it is necessary to input an input signal to both the voltage drive circuit 102 and the current drive circuit 103, because this can enable the output circuit 100 to automatically select whether the output device 106 is driven by the voltage drive circuit 102 or the current drive circuit 103 based on the characteristics of the output device 106. As known to those skilled in the art, in some applications, it is common to provide power (e.g., voltage or current) to the output device 106 that varies within a certain range to meet the required drive of the output device 106, so the input signals to the voltage drive circuit 102 and the current drive circuit 103 need to vary within a certain range accordingly. Whereas, for the voltage-mode driven output device 106 and the current-mode driven output device 106, the power (e.g., voltage or current) required to be supplied to the output device 106 generally varies in different ranges, and therefore this may cause the variation range of the input signal required to be output to the voltage drive circuit 102 and the variation range of the input signal required to be output to the current drive circuit 103 to be different. For example, if it may be necessary to provide a voltage varying in the range of 0-10V to drive the output device 106 for the voltage-mode-driven output device 106, and a current varying in the range of 4-20mA to drive the output device 106 for the current-mode-driven output device 106, this may result in the need to provide an input voltage varying in the range of 0-5V to the voltage driving circuit 102 when the voltage-mode-driven output device 106, and an input voltage varying in the range of 1-5V to the current driving circuit 103 when the current-mode-driven output device 106, i.e., the variation range of the input voltage is different between the voltage-mode-driven output device 106 and the current-mode-driven output device 106. Therefore, in order to solve this problem, the present application appropriately offsets the same input signal so that the input signals simultaneously supplied to the voltage driving circuit 102 and the current driving circuit 103 vary within a first range when the output device 106 is driven by the voltage type, and the input signals simultaneously supplied to the voltage driving circuit 102 and the current driving circuit 103 vary within a second range (different from the first range) when the output device 106 is driven by the current type, thereby satisfying different requirements of the voltage type driving output device 106 and the current type driving output device 106.
In one embodiment, to solve the above problem, fig. 1A of the present application provides an offset configuration circuit 101, which functions as: when the voltage driving circuit 102 drives the output device 106, the offset configuration circuit 101 offsets the input signal Sin varying within a certain range to a signal varying within a first range; when the current driving circuit 103 drives the output device 106, the offset configuration circuit 101 offsets the input signal Sin varying within a certain range to a signal varying within a second range, the first range and the second range being different. It should be noted that if the power (e.g., voltage or current) required to be supplied to the output device 106 by the voltage-mode driving output device 106 and the current-mode driving output device 106 varies within the same range, the offset configuration circuit 101 is not required to be provided, and only the required input signal Sin varying within the same range is required to be supplied to the output device 106.
As shown in fig. 1A, the offset configuration circuit 101 has an input terminal, a control input terminal, and an output terminal. The input terminal of the offset configuration circuit 101 receives an external input signal Sin through a connection line 111, and the input signal Sin may be a variable analog voltage signal or a variable analog current signal. In some embodiments, the external input signal Sin may be generated by: in an air conditioning system, a temperature sensor detects an ambient temperature and converts the ambient temperature into a voltage signal, and an MCU receives the voltage signal from the temperature sensor and generates an input control signal based on the voltage signal, which is input to a driving circuit to drive an output device 106 (which may be the input signal Sin of the present application). The external input signal Sin of the present application may be generated by other methods.
The output terminal of the offset configuration circuit 101 is connected to the input terminal of the voltage drive circuit 102 via the connection lines 123, 112 and to the input terminal of the current drive circuit 103 (i.e., the input terminal of the current control circuit 107) via the connection lines 123, 113. When the output device 106 needs the voltage driving circuit 102 to drive, the offset configuration circuit 101 performs a first offset on the input signal Sin varying within a certain range to output an offset input signal Vin varying within a first range; when the output device 106 requires the current driving circuit 103 to drive, the offset configuration circuit 101 performs a second offset on the input signal Sin varying within a certain range to output an offset input signal Vin varying within a second range, the first range being different from the second range. The offset configuration circuit 101 outputs the offset input signal Vin to the input terminal of the voltage drive circuit 102 via the connection lines 123, 112 and to the input terminal of the current drive circuit 103 via the connection lines 123, 113.
In one embodiment, the control input of the offset configuration circuit 101 is connected to the control output of the voltage driving circuit 102 via the connection 126 for receiving the intermediate voltage driving signal Dr 1' output by the voltage driving circuit 102. Also, the offset configuration circuit 101 performs a first or second offset on the input signal Sin in accordance with the intermediate voltage drive signal Dr 1' (which is high or low) received at the control input. For example, when the intermediate voltage drive signal Dr 1' is high, the offset configuration circuit 101 performs a first offset on the input signal Sin; the offset configuration circuit 101 performs a second offset on the input signal Sin when the intermediate voltage drive signal Dr 1' is low. In another embodiment, the offset configuration circuit 101 performs a first offset on the input signal Sin when the intermediate voltage driving signal Dr 1' is low; the offset configuration circuit 101 performs a second offset on the input signal Sin when the intermediate voltage drive signal Dr 1' is high.
In another embodiment, the control input terminal of the offset configuration circuit 101 is connected to the output terminal of the current driving circuit 103 via the connection line 116 (shown by the dashed line in fig. 1A) for receiving the current driving signal Dr2 outputted by the current driving circuit 103. And the offset configuration circuit 101 performs a first or second offset on the input signal Sin in accordance with the current drive signal Dr2 (which is high or low) received at the control input. This shifting of the shift arrangement 101 operates in a similar manner as the previously described shift arrangement 101 for first or second shifting of the input signal Sin based on the intermediate voltage drive signal Dr 1'. Since the intermediate voltage drive signal Dr 1' output by the voltage drive circuit 102 and the current drive signal Dr2 output by the current drive circuit 103 can indicate whether the output device 106 is driven by the voltage drive circuit 102 or the current drive circuit 103, the offset configuration circuit 101 performs the first or second offset on the input signal Sin based on whether the output device 106 needs to be driven by the voltage drive circuit 102 or the current drive circuit 103.
In some embodiments, the input signal Sin may also be a voltage-varying PWM signal, and the offset configuration circuit 101 further includes a D/a conversion circuit for converting the PWM signal into an analog signal. Also, the offset configuration circuit 101 also performs the offset operation of the analog signal described above on the converted analog signal. In other embodiments, the input signal Sin may also be a current-varying PWM signal.
The voltage driver circuit 102 in fig. 1A has an input terminal, a feedback input terminal, a control output terminal, and an output terminal. The input end of the voltage driving circuit 102 is connected to the output end of the offset configuration circuit 101 through the connection lines 123 and 112 to receive the offset input signal Vin output by the offset configuration circuit 101; the output terminal of the voltage driving circuit 102 is connected to the input terminal of the output stage circuit 105 through a connection line 114. The voltage driving circuit 102 functions to: the offset configuration circuit 101 receives the offset input signal Vin, generates the voltage driving signal Dr1 based on the offset input signal Vin, and outputs the voltage driving signal Dr1 to the output stage circuit 105 through the connection line 114. The feedback input of the voltage driving circuit 102 receives a voltage-type output feedback signal from the output of the output stage circuit 105 through a connection line 120, and the voltage-type output feedback signal functions to operate or not operate the voltage driving circuit 102. The voltage driving circuit 102 operates to output a voltage driving signal Dr1 to the output stage circuit 105 by the voltage driving circuit 102 to control the output stage circuit 105 to provide a power output to the output device 106. In one embodiment, if the offset configuration circuit 101 performs the first or second offset on the input signal Sin based on the intermediate voltage driving signal Dr1 ', the control output of the voltage driving circuit 102 outputs the intermediate voltage driving signal Dr 1' to the control input of the offset configuration circuit 101 through the connection line 126 to control the offset configuration circuit 101 to perform the first or second offset on the input signal Sin.
The current drive circuit 103 in fig. 1A has one input, one feedback input, and one output. The input terminal of the current driving circuit 103 is connected to the output terminal of the offset configuration circuit 101 through the connection lines 113 and 123 to receive the offset input signal Vin output by the offset configuration circuit 101; the output terminal of the current drive circuit 103 is connected to the input terminal of the isolation circuit 104 through a connection line 115. The current drive circuit 103 functions to: the current drive signal Dr2 is generated in response to the shifted input signal Vin and is output to the output stage circuit 105 via the isolation circuit 104 as the current drive signal Dr 2. The feedback input of the current driving circuit 103 receives a current mode output feedback signal from the current mode feedback output of the output stage circuit 105 through the connection line 121, and the current mode output feedback signal functions to operate or not operate the current driving circuit 103. The current driving circuit 103 is operative to refer to the current driving circuit 103 outputting a current driving signal Dr2 to the output stage circuit 105 to control the output stage circuit 105 to provide a power output to the output device 106. In one embodiment, if the offset configuration circuit 101 performs the first or second offset on the input signal Sin based on the current driving signal Dr2, the output terminal of the current driving circuit 103 outputs the current driving signal Dr2 to the control input terminal of the offset configuration circuit 101 through the connection line 116 to control the offset configuration circuit 101 to perform the first or second offset on the input signal Sin.
Further, the current drive circuit 103 in fig. 1A includes a current control circuit 107 and a feedback differential amplification circuit 108. The current control circuit 107 includes an input terminal, a feedback amplification input terminal, and an output terminal. The input terminal of the current control circuit 107 is the input terminal of the current driving circuit 103, and the output terminal of the current control circuit 107 is the output terminal of the current driving circuit 103. The current control circuit 107 functions to: the current drive signal Dr2 is generated in response to the shifted input signal Vin and is output to the output stage circuit 105 via the isolation circuit 104 as the current drive signal Dr 2. The feedback amplification input of the current control circuit 107 receives an amplified feedback signal from the feedback differential amplification circuit 108 via connection 122, the amplified feedback signal having the effect of making the current control circuit 107 operative or inoperative.
The feedback differential amplifying circuit 108 includes a feedback input terminal and a feedback amplifying output terminal. A feedback input terminal of the feedback differential amplification circuit 108 (i.e., a feedback input terminal of the current drive circuit 103) receives a current mode output feedback signal from the output stage circuit 105 through a connection line 121; a feedback amplification output terminal of the feedback differential amplification circuit 108 is connected to a feedback amplification input terminal of the current control circuit 107. The feedback differential amplifying circuit 108 functions as: the received current mode output feedback signal is scaled up and the amplified feedback signal is output to the feedback amplification input terminal of the current control circuit 107 to control the operation or non-operation of the current control circuit 107.
The isolation circuit 104 in fig. 1A has an input terminal and an output terminal, wherein the input terminal of the isolation circuit 104 is connected to the output terminal of the current driving circuit 103 through the connection line 115 to receive the current driving signal Dr2, and the output terminal of the isolation circuit 104 is connected to the output terminal of the voltage driving circuit 102 through the connection line 114 and to the input terminal of the output stage circuit 105 through the connection line 117. The isolation circuit 104 functions to: when the current driving circuit 103 is in an operating state, the current driving circuit 103 drives the output stage circuit 105 through the isolation circuit 104, and at this time, the voltage driving circuit 102 is in an inoperative state; when the voltage driving circuit 102 is in the operating state, since the output of the current driving circuit 103 is also connected to the input terminal of the output stage circuit 105, the isolation circuit 104 disconnects the output of the current driving circuit 103 from the output stage circuit 105 to prevent the output of the current driving circuit 103 from controlling the driving of the output stage circuit 105. Note that the output of the current drive circuit 103 has a low impedance property, and the output of the voltage drive circuit 102 has a high impedance property. Therefore, when the voltage driving circuit 102 is operated and the current driving circuit 103 is not operated, if the current driving circuit 103 is not disconnected through the isolation circuit 104, the output of the current driving circuit 103 has a low impedance property such that the current driving circuit 103 cannot be disconnected from the output stage circuit 105. However, when the voltage driving circuit 102 does not operate and the current driving circuit 103 operates, the high impedance property of the output of the voltage driving circuit 102 can disconnect the voltage driving circuit 102 from the output stage circuit 105, so that the current driving circuit 103 does not influence the driving of the output stage circuit 105 by the voltage driving circuit 102, and therefore, the isolation circuit 104 is not needed to disconnect the voltage driving circuit 102.
It should be noted that when the current driving circuit 103 does not operate and the voltage driving circuit 102 operates, the voltage of the input terminal of the isolation circuit 104 (i.e., the output terminal of the current driving circuit 103) is smaller than the voltage of the output terminal of the isolation circuit 104 (i.e., the output terminal of the voltage driving circuit 102). Because the voltage-mode output feedback signal that voltage drive circuit 102 receives from output stage circuit 105 and the current-mode output feedback signal that current drive circuit 103 receives from output stage circuit 105 cause the voltage that current drive circuit 103 outputs to always be less than the voltage that voltage drive circuit 102 outputs, based on the characteristics (e.g., impedance) of output device 106 connected to output stage circuit 105, when output device 106 is driven by voltage drive circuit 102 and not by current drive circuit 103. Therefore, the inventors have used unidirectionally isolated devices, specifically diodes.
The output stage circuit 105 in fig. 1A has an input, a first output (device identification input), a second output (device identification input), and a current mode feedback output. The input terminal of the output stage circuit 105 is connected to the output terminal of the voltage driving circuit 102 through the connection line 114 and to the output terminal of the isolation circuit 104 through the connection line 117 to receive the voltage driving signal Dr1 output from the voltage driving circuit 102 or the current driving signal Dr2 output from the current driving circuit 103. A first output terminal of the output stage circuit 105 is connected to the output device 106 by a connection line 118 and a second output terminal of the output stage circuit 105 is connected to the output device 106 by a connection line 119 to output a driving output voltage Vout and a driving output current Iout to the output device 106. When the output device 106 is connected to the output stage circuit 105, the output device 106 can identify the characteristic (e.g., resistance) (device identification information) of the output device 106 through the connection lines 118, 119, and the output terminal of the output stage circuit 105 should be referred to as a device identification input terminal. A first output terminal of the output stage circuit 105 is connected to the feedback input terminal of the voltage driving circuit 102 through a connection line 120 to output a voltage-mode output feedback signal (Vout) to the voltage driving circuit 102, and a current-mode feedback output terminal of the output stage circuit 105 is connected to the feedback input terminal of the current driving circuit 103 through a connection line 121 to output a current-mode output feedback signal to the current driving circuit 103. The output stage circuit 105 functions to: driving the output device 106 based on the voltage drive signal Dr1 received from the voltage drive circuit 102 or the current drive signal Dr2 received from the current drive circuit 103; and outputs a voltage-mode output feedback signal to the voltage drive circuit 102 and outputs a current-mode output feedback signal to the current drive circuit 103 based on the device identification information received from the output device 106, thereby automatically selecting one of the voltage drive circuit 102 and the current drive circuit 103 to operate.
It is to be noted that when the voltage driving circuit 102 drives the output stage circuit 105, the output of the entire circuit is characterized by driving the output device 106 in a voltage mode. When the current drive circuit 103 drives the output stage circuit 105, the characteristics of the output of the entire circuit drive the output device 106 in a current mode. Specifically, when the voltage driving circuit 102 drives the output stage circuit 105, the voltage output from the output stage circuit 105 to the output device 106 is controlled by the input voltage Sin and the voltage driving circuit 102, which is referred to as driving the output device 106 in a voltage type; when the current driving circuit 103 drives the output stage circuit 105, the current output from the output stage circuit 105 to the output device 106 is controlled by the input voltage Sin and the current driving circuit 103, and in this case, the output device 106 is driven in a current mode.
The structure of the output circuit 100 in fig. 1B is substantially the same as the structure of the output circuit 100 in fig. 1A, except that: the isolation circuit 104 in fig. 1A is connected between the current drive circuit 103 and the output stage circuit 105, and the isolation circuit 104 in fig. 1B is connected between the voltage drive circuit 102 and the output stage circuit 105. Therefore, the functions of the respective blocks of the output circuit 100 in fig. 1B, and the connection relationship and the fitting relationship between the respective blocks are substantially the same as those in fig. 1A. The difference lies in that: in fig. 1B, in one embodiment, the output terminal of the voltage driving circuit 102 is connected to the control input terminal of the offset configuration circuit 101 through the connection line 126 to output the voltage driving signal Dr1 to the offset configuration circuit 101, so as to control the offset configuration circuit 101 to perform the first or second offset on the input signal Sin; in another embodiment, the current driving circuit 103 includes a control output (i.e., the control output of the current control circuit 107) coupled to the control input of the offset configuration circuit 101 via the connection 116 to output the intermediate current driving signal Dr 2' to the offset configuration circuit 101 to control the offset configuration circuit 101 to perform the first or second offset on the input signal Sin. The other differences are that: in fig. 1B, the output of the voltage drive circuit 102 has a low impedance property, and the output of the current drive circuit 103 has a high impedance property, so that: when the voltage driving circuit 102 operates and the current driving circuit 103 does not operate, the current driving circuit 103 can be disconnected from the output stage circuit 105 by the high impedance property of the output of the current driving circuit 103; when the current drive circuit 103 is operated and the voltage drive circuit 102 is not operated, the voltage drive circuit 102 is disconnected from the output stage circuit 105 by the isolation circuit 104.
FIG. 2A is a detail of a circuit diagram of exemplary various modules in accordance with one embodiment of the output circuit 100 of the present invention shown in FIG. 1A; fig. 2B is a detail of a circuit diagram of exemplary individual blocks of one embodiment of the output circuit 100 according to the present invention shown in fig. 1B.
Fig. 2A includes all circuit blocks of the output circuit 100 of fig. 1A configured automatically: an offset configuration circuit 101, a voltage drive circuit 102, a current drive circuit 103, an isolation circuit 104, and an output stage circuit 105. Each element and the connection between the respective elements are shown in each corresponding block diagram. For the purpose of convenience of explanation, each element of the offset configuration circuit 101 in fig. 2A and the connection relationship between the respective elements are shown in more detail in fig. 3A, 3B, 4A, 4B.
The offset configuration circuit 101 in fig. 2A includes a voltage division offset circuit 201 and an offset control circuit 202. The voltage division offset circuit 201 has one input terminal, two voltage division control input terminals, and one output terminal. The input terminal of the voltage division offset circuit 201 receives an external input signal Sin through a connection line 111, and the output terminal of the voltage division offset circuit 201 is connected to the input terminal of the voltage driving circuit 102 through connection lines 123, 112 and to the input terminal of the current driving circuit 103 through connection lines 123, 113. The voltage division offset circuit 201 functions as: the input signal Sin varying in a certain range is shifted to vary in another different range by voltage division of the resistor to output a shifted input signal Vin, and the shifted input signal Vin is output to the voltage drive circuit 102 and the current drive circuit 103. The two voltage division control input terminals of the voltage division offset circuit 201 are respectively connected to the two voltage division control output terminals of the offset control circuit 202 through connection lines 203 and 204, so as to receive voltage division control signals from the offset control circuit 202 to generate different voltage division characteristics. In operation, the voltage division and offset circuit 201 is capable of performing a first offset on the input signal Sin varying within the same range based on the received voltage division control signal to generate an offset input signal Vin varying within a first range, or performing a second offset to generate an offset input signal Vin varying within a second range, the first range being different from the second range, and the first range and the second range being different from the same range. As described for fig. 1A, the effect of the offset (i.e., offset of the voltage division offset circuit 201) operation of the offset configuration circuit 101 is: the input signal Sin varying in the same range is shifted to vary in different ranges, so that the electric power output to the output device 106 when the output device 106 is driven by the voltage drive circuit 102 or the current drive circuit 103 varies in different ranges to satisfy different demands for electric power for voltage-type driving of the output device 106 and current-type driving of the output device 106.
The offset control circuit 202 in fig. 2A has one control input and two voltage division control outputs. The control input of the offset control circuit 202 is connected to the control output of the voltage drive circuit 102 via connection 126 to receive the intermediate voltage drive signal Dr 1' from the voltage drive circuit 102; or the control input of the offset control circuit 202 is connected to the output of the current drive circuit 103 via connection 116 to receive the voltage drive signal Dr2 from the current drive circuit 103. Two voltage division control output ends of the offset control circuit 202 are respectively connected with two voltage division control input ends of the voltage division offset circuit 201 through connecting lines 203 and 204. The offset control circuit 202 functions to: the voltage division control signal is generated based on the received intermediate voltage driving signal Dr 1' or the voltage driving signal Dr2 and is output to the voltage division shifting circuit 201 to control the voltage division shifting circuit 201 to shift the input signal Sin by the first or second shift.
The voltage division offset circuit 201 of the offset configuration circuit 101 in fig. 2A includes a specific circuit configuration shown in fig. 3A and 3B, and the offset control circuit 202 of the offset configuration circuit 101 in fig. 2A includes a specific circuit configuration shown in fig. 4A and 4B. Fig. 3A shows a specific circuit configuration of the voltage division shift circuit 201 when the input signal Sin is an analog signal, and fig. 3B shows a specific circuit configuration of the voltage division shift circuit 201 when the input signal Sin is a varied PWM signal. Fig. 4A shows a specific structure of the offset control circuit 202, and fig. 4B shows another specific structure of the offset control circuit 202.
The offset configuration circuit 101 in fig. 2A includes the following embodiments: in the first embodiment, the offset configuration circuit 101 includes a voltage division offset circuit 201 as shown in fig. 3A and an offset control circuit 202 as shown in fig. 4A; in the second embodiment, the offset configuration circuit 101 includes a voltage division offset circuit 201 as shown in fig. 3A and an offset control circuit 202 as shown in fig. 4B; in the third embodiment, the offset configuration circuit 101 includes a voltage division offset circuit 201 as shown in fig. 3B and an offset control circuit 202 as shown in fig. 4A; in the fourth embodiment, the offset configuration circuit 101 includes a voltage division offset circuit 201 as shown in fig. 3B and an offset control circuit 202 as shown in fig. 4B.
As described previously, in the first embodiment, the offset configuration circuit 101 includes the voltage division offset circuit 201 shown in fig. 3A and the offset control circuit 202 shown in fig. 4A. Specifically, the input signal Sin in fig. 3A is a varying analog signal, and the voltage division offset circuit 201 in fig. 3A includes a resistor R1, a resistor R2, and a resistor R3. The resistor R2, the resistor R3, and the resistor R1 are sequentially connected in series between the power supply and the input signal Sin, wherein a first end of the resistor R2 is connected to the power supply, a second end of the resistor R2 is connected to a first end of the resistor R3, a second end of the resistor R3 is connected to a first end of the resistor R1, and a second end of the resistor R1 (i.e., an input end of the voltage division offset circuit 201) is connected to the input signal Sin through a connection line 111. First and second terminals of the resistor R2 (i.e., two voltage division control input terminals of the voltage division offset circuit 201) are connected to the source and drain of the switching element Q2 in fig. 4A (i.e., two voltage division control output terminals of the offset control circuit 202) through connection lines 203, 204, respectively (see fig. 2A), and a connection between the resistor R3 and the resistor R1 (i.e., an output terminal of the voltage division offset circuit 201) outputs the input signal Vin subjected to the offset to the voltage drive circuit 102 and the current drive circuit 103 through the connection line 123.
Also, in the first embodiment, the offset control circuit 202 in fig. 4A includes the switching element Q2, and the switching element Q2 is a P-channel field effect transistor. The source and drain of the P-channel fet Q2 are connected to the first and second terminals (see fig. 3A) of the resistor R2 in the voltage-dividing offset circuit 201 via connection lines 203, 204, respectively. The gate of the P-channel fet Q2 is coupled to the control output of the voltage driver circuit 102 via the connection 126 to receive the intermediate voltage driving signal Dr 1' output by the voltage driver circuit 102.
In the first embodiment, when the voltage driving circuit 102 is in an operating state (when the current driving circuit 103 is in an inactive state), the intermediate voltage driving signal Dr 1' output by the voltage driving circuit 102 is at a high level, the P-channel fet Q2 is turned off, and the resistor R2, the resistor R3, and the resistor R1 in the voltage division and offset circuit 201 are connected in series between the power supply and the input signal Sin (see fig. 3A), and when the offset configuration circuit 101 performs a first offset on the input signal Sin to output the offset input signal Vin varying within a first range. When the voltage driving circuit 102 is in the inactive state (when the current driving circuit 103 is in the active state), the intermediate voltage driving signal Dr 1' outputted by the voltage driving circuit 102 is at the low level, the P-channel fet Q2 is turned on, the resistor R2 (see fig. 3A) in the voltage division and offset circuit 201 is short-circuited, and only the resistor R3 and the resistor R1 in the voltage division and offset circuit 201 are connected in series between the power supply and the input signal Sin (see fig. 3A), and at this time, the offset configuration circuit 101 performs the second offset on the input signal Sin to output the offset input signal Vin varying within the second range. That is, when the voltage driving circuit 102 is in an operating or non-operating state, the resistor R2 is connected or not connected into the voltage division shift circuit 201, thereby causing the voltage division shift circuit 201 to generate different voltage division characteristics to perform different shifts (i.e., first or second shifts) on the input signal Sin.
In some embodiments, the input signal Sin is an analog voltage signal varying in the range of 0-5V, the power supply provides 5V, the resistor R2 has a resistance of 475K Ω, the resistor R3 has a resistance of 20K Ω, and the resistor R1 has a resistance of 4.99K Ω. Therefore, according to the principle of voltage division by resistors, when the voltage driving circuit 102 is in an operating state such that the resistor R2, the resistor R3, and the resistor R1 are connected in series between the power supply and the input signal Sin, the offset (first offset) input voltage Vin output at the connection between the resistor R3 and the resistor R1 is: vin is 0.99Sin + 0.05. At this time, the offset configuration circuit 101 performs a first offset on the input signal Sin to output an offset input voltage Vin varying in a range of 0.05-5V. It should be noted that the ideal state may require the offset configuration circuit 101 to perform the first offset on the input signal Sin to output the offset input voltage Vin varying in the range of 0-5V, but actually output the offset input voltage Vin varying in the range of 0.05-5V. However, the error generated by the actual value (0.05-5V) is small, and the influence on the output of the output stage circuit is small and can be ignored. When the voltage driving circuit 102 is in the inactive state such that the resistors R3 and R1 are connected in series between the power supply and the input signal Sin, the offset (second offset) input voltage Vin output at the connection between the resistor R3 and the resistor R1 is: vin is 0.8Sin + 1. At this time, the offset configuration circuit 101 performs a second offset on the input signal Sin to output an offset input voltage Vin varying in a range of 1-5V.
As described previously, in the second embodiment, the offset configuration circuit 101 includes the voltage division offset circuit 201 shown in fig. 3A and the offset control circuit 202 shown in fig. 4B. The structure and function of each element and the connection and cooperation relationship thereof in the second embodiment are the same as those in the first embodiment. The difference lies in that: the offset control circuit 202 employed in the first embodiment is a P-channel fet, and the gate of the P-channel fet is connected to the control output terminal of the voltage driving circuit 102 through the connection line 126 to receive the intermediate voltage driving signal Dr 1' output by the voltage driving circuit 102, so that the first embodiment performs the first or second offset on the input signal Sin according to the output of the voltage driving circuit 102. The offset control circuit 202 of the second embodiment is an N-channel fet, whose gate is connected to the output terminal of the current driving circuit 103 through the connection line 116 to receive the voltage driving signal Dr2 output by the current driving circuit 103, so that the second embodiment performs the first or second offset on the input signal Sin according to the output of the current driving circuit 103.
More specifically, in the second embodiment, the offset control circuit 202 in fig. 4B includes the switching element Q2, and the switching element Q2 is an N-channel field effect transistor. The drain and source of the N-channel fet Q2 are connected to the first and second terminals (see fig. 3A) of the resistor R2 in the voltage-dividing offset circuit 201 via connection lines 203, 204, respectively. The gate of the N-channel fet Q2 is connected to the output of the current driving circuit 103 via the connection 116 to receive the voltage driving signal Dr2 output by the current driving circuit 103. When the current driving circuit 103 is in an operating state (at this time, the voltage driving circuit 102 is in an inactive state), the current driving signal Dr2 output by the current driving circuit 103 is at a high level, the N-channel fet Q2 (see fig. 4B) is turned on, the resistor R2 (see fig. 3A) in the voltage division and shift circuit 201 is short-circuited, only the resistor R3 and the resistor R1 in the voltage division and shift circuit 201 are connected in series between the power supply and the input signal Sin (see fig. 3A), and at this time, the shift configuration circuit 101 performs a second shift on the input signal Sin to output a shifted input signal Vin varying within a second range. When the current driving circuit 103 is in the inactive state (when the voltage driving circuit 102 is in the active state), the current driving signal Dr2 output by the current driving circuit 103 is at the low level, the N-channel fet Q2 (see fig. 4B) is turned off, and the resistor R2, the resistor R3 and the resistor R1 in the voltage division and offset circuit 201 are connected in series between the power supply and the input signal Sin (see fig. 3A), and when the offset configuration circuit 101 performs the first offset on the input signal Sin to output the offset input signal Vin varying in the first range.
In the third and fourth embodiments, the input signal Sin in fig. 3B is a varying PWM signal, and the structures and functions of the elements in fig. 4A and 4B and their connections and mating relationships are the same as those in the first and second embodiments. The structure and function of the elements in the voltage division offset circuit 201 in fig. 3B and their connection and matching relationship are substantially the same as those in fig. 3A, except that: the voltage division offset circuit 201 in fig. 3B further includes a D/a conversion circuit for converting the input PWM signal into an analog signal. As in fig. 3A, the voltage division offset circuit 201 in fig. 3B also performs a first or second offset on the input signal to output an offset (analog) input signal Vin varying within a first or second range.
Compared to the voltage division offset circuit 201 in fig. 3A, the voltage division offset circuit 201 in fig. 3B further includes a resistor R4 and a capacitor C1, wherein a connection between the resistor R3 and the resistor R1 is connected to a first end of the capacitor C1 and a first end of the resistor R4, a second end of the capacitor C1 is grounded, and a second end of the resistor R4 outputs the shifted input signal Vin to the voltage driving circuit 102 and the current driving circuit 103 through the connection line 123. The resistor R1 and the capacitor C1 constitute a D/a conversion circuit for filtering the input varying PWM signal Sin to generate an analog signal. Also, since the capacitor C1 is connected to the inverting input terminals of the voltage output operational amplifier OA1 of the voltage drive circuit 102 and the current output operational amplifier OA2 of the current drive circuit 103 (see fig. 2A), it is easy to oscillate the outputs of the voltage output operational amplifier OA1 and the current output operational amplifier OA 2. In one embodiment, the present invention connects a resistor R4 between the capacitor C1 and the voltage output operational amplifier OA1 and the current output operational amplifier OA2 to prevent the output of the voltage output operational amplifier OA1 and the current output operational amplifier OA2 from oscillating. In another embodiment, resistor R4 may not be connected to reduce the number of components in the output circuit.
In one embodiment, the input PWM signal Sin of fig. 3B has a high level of 5V, a low level of 0V, and a duty ratio of D. If there is no capacitor C1 in fig. 3B, the connection between the resistor R3 and the resistor R1 outputs an offset (amplitude offset) PWM signal based on the voltage division principle of the resistors. Assuming that the input signal Sin is an analog voltage signal varying in the range of 0-5V, the power supply provides a voltage of 5V, the resistance of resistor R2 is 475K Ω, the resistance of resistor R3 is 20K Ω, and the resistance of resistor R1 is 4.99K Ω, as mentioned in the description of fig. 3A. When the PWM signal Sin outputs a low level (0V) when the voltage driving circuit 102 is in an operating state such that the resistor R2, the resistor R3, and the resistor R1 are connected in series between the power supply and the input signal Sin, a voltage generated at the connection between the resistor R3 and the resistor R1 based on the voltage division principle is 0.05V; when the PWM signal Sin outputs a high level (5V), a voltage generated at the connection between the resistor R3 and the resistor R1 based on the voltage division principle is 5V. That is, the high level of the shifted PWM signal outputted through the first shift at the connection between the resistor R3 and the resistor R1 is 5V, the low level is 0.05V, and the duty ratio is D. While there is a capacitor C1 in fig. 3B, the resistor R1 and the capacitor C1 form a filter circuit to convert the shifted PWM signal output at the connection between the resistor R3 and the resistor R1 into an analog voltage signal: 0.05 × (1-D) +5 × D, when the analog voltage signal is limited to vary within the range of 0.05-5V (first range). The analog voltage signal output at the connection between the resistor R3 and the resistor R1 outputs the shifted input signal Vin via the resistor R4, the shifted input signal Vin output from the second end of the resistor R4 being the same as the analog voltage signal input to the first end of the resistor R4. Since the resistor R4 is connected to the input terminals of the voltage output operational amplifier OA1 in the voltage drive circuit 102 and the current output operational amplifier OA2 in the current drive circuit 103 via the connection line 123, and the input resistances of the voltage output operational amplifier OA1 and the current output operational amplifier OA2 are infinite as seen from the virtual short virtual cutoff characteristic of the operational amplifiers, it can be considered that no current flows through the resistor R4, and thus the voltages of the first terminal and the second terminal of the resistor R4 are the same. The value of the output shifted (analog) input signal Vin can be changed by adjusting the duty cycle D of the PWM signal to output the desired analog voltage signal.
Described above is that the voltage division shift circuit 201 in fig. 3B performs the first shift on the input signal to output the shifted (analog) input signal Vin varying within the first range when the voltage drive circuit 102 is in the operating state. It is understood that, similar to the operation principle, when the voltage driving circuit 102 is in the non-operating state, the voltage division offset circuit 201 in fig. 3B may perform the second offset on the input signal to output the offset (analog) input signal Vin varying within the second range.
The voltage driving circuit 102 in fig. 2A includes a voltage output operational amplifier OA1, a resistor R5, a resistor R6, and a resistor R7. As mentioned in the description of fig. 1A, the voltage driving circuit 102 functions to: receiving the shifted input signal Vin from the shift configuration circuit 101, generating a voltage driving signal Dr1 based on the shifted input signal Vin, and outputting the voltage driving signal Dr1 to the output stage circuit 105 through the connection line 114; and receives a voltage-type output feedback signal from the output stage circuit 105 to operate or not operate the voltage drive circuit 102.
In the particular configuration shown in fig. 2A, the Vcc + pole of the voltage output operational amplifier OA1 is connected to the power supply Vcc and the Vcc-pole of the voltage output operational amplifier OA1 is connected to the ground GND, and the voltage output operational amplifier OA1 has a non-inverting input, an inverting input, and an output. The resistor R5 and the resistor R6 are connected in series, wherein a first end of the resistor R5 is connected to a first end of the output device 106 through the connection line 120, a second end of the resistor R5 is connected to a first end of the resistor R6, and a second end of the resistor R6 is connected to the GND. Since the output stage circuit 105 outputs the driving output voltage Vout to the first terminal of the output device 106 through the connection line 118, and the first terminal of the resistor R5 is connected to the first terminal of the output device 106 through the connection line 120, the first terminal of the resistor R5 receives the driving output voltage Vout (voltage-type output feedback signal) from the output stage circuit 105 through the connection line 120. Also, the junction between the resistor R5 and the resistor R6 is connected to the non-inverting input terminal of the voltage output operational amplifier OA1, so the voltage VOA1 at the non-inverting input terminal is a voltage value provided to both ends of the resistor R6 after the driving output voltage Vout is divided by the resistor R5 and the resistor R6, that is, VOA1 ═ Vout × R6/(R5+ R6), where R5 and R6 represent resistance values of the resistor R5 and the resistor R6, respectively. Assuming that R6/(R5+ R6) is L, VOA1 is Vout L. The inverting input of the voltage output operational amplifier OA1 is connected to the output of the offset configuration circuit 101 via connection 112 to receive the offset input voltage Vin. An output terminal of the voltage output operational amplifier OA1 is connected to a first terminal of the resistor R7 to output the intermediate voltage drive signal Dr 1' to a first terminal of the resistor R7, a second terminal of the resistor R7 is connected to an input terminal of the output stage circuit 105 through a connection line 114 to output the voltage drive signal Dr1 to the input terminal of the output stage circuit 105, and a second terminal of the resistor R7 is connected to an output terminal of the isolation circuit 104 through connection lines 114 and 117.
The voltage output operational amplifier OA1 functions as: the intermediate voltage drive signal Dr 1' is output to the resistor R7 in response to the divided voltage signal VOA1 of the voltage type output feedback signal Vout received at the non-inverting input terminal from the output stage circuit 105 and the shifted input voltage Vin received at the inverting input terminal from the offset configuration circuit 101, and the voltage drive signal Dr1 is output to the output stage circuit 105 via the resistor R7. The voltage mode output feedback signal is used to enable or disable the voltage driving circuit 102, wherein the voltage driving circuit 102 is enabled to output the voltage driving signal Dr1 to the output stage circuit 105 to control the output stage circuit 105 to provide power to the output device 106 (i.e., to drive the output device in a voltage mode) (see below).
In one embodiment, if the offset configuration circuit 101 performs the first or second offset on the input signal Sin based on the intermediate voltage driving signal Dr1 ', the control output terminal (the second terminal of the resistor R7) of the voltage driving circuit 102 in fig. 2A outputs the intermediate voltage driving signal Dr 1' to the control input terminal of the offset control circuit 202 of the offset configuration circuit 101 through the connection line 126 to control the offset configuration circuit 101 to perform the first or second offset on the input signal Sin.
The current drive circuit 103 in fig. 2A includes a current control circuit 107 and a feedback differential amplification circuit 108. The feedback differential amplifying circuit 108 functions as: the current mode output feedback signal received from the output stage circuit 105 is scaled up and the amplified feedback signal V1 is output to the feedback amplification input of the current control circuit 107. The current control circuit 107 functions to: receives the offset input voltage Vin from the output terminal of the offset configuration circuit 101 and the amplified feedback signal V1 from the feedback differential amplification circuit 108, and generates the current drive signal Dr2 in response to the offset input voltage Vin and the amplified feedback signal V1, and outputs the current drive signal Dr2 to the output stage circuit 105 through the isolation circuit 104. The current mode output feedback signal functions to enable or disable the current drive circuit 103.
The current control circuit 107 in fig. 2A includes a current output operational amplifier OA2, a resistor R8, and a resistor R9. The current output operational amplifier OA2 is connected between the operating power supply VCC and ground GND, and the current output operational amplifier OA2 has a non-inverting input terminal, an inverting input terminal, and an output terminal. The inverting input of the current output operational amplifier OA2 is connected to the output of the offset configuration circuit 101 to receive the offset input voltage Vin. The resistor R8 and the resistor R9 are connected in series to the output terminal of the feedback differential amplification circuit 108 to receive the amplified feedback signal V1, wherein the feedback differential amplification circuit 108 proportionally amplifies the voltage difference (i.e., current-mode output feedback signal) received from both ends of the current detection resistor R15 of the output stage circuit 105 to output the amplified feedback signal V1. A first terminal of the resistor R9 is connected to the output terminal of the feedback differential amplifying circuit 108 to receive the amplified feedback signal V1, a second terminal of the resistor R9 is connected to a first terminal of the resistor R8, and a second terminal of the resistor R8 is connected to the ground GND. The junction between the resistor R8 and the resistor R9 is connected to the positive input terminal of the current output operational amplifier OA2, so the voltage (VOA2) at the positive input terminal is the voltage value provided to both ends of the resistor R8 after the feedback signal V1 is divided by the resistor R8 and the resistor R9, i.e., VOA2 ═ V1 ═ R8/(R8+ R9), where R8 and R9 represent the resistance values of the resistor R8 and the resistor R9, respectively. The output terminal of the current output operational amplifier OA2 is connected to the output terminal of the voltage driving circuit 102 and the input terminal of the output stage circuit 105 via the isolation circuit 104.
The current output operational amplifier OA2 functions as: the current drive signal Dr2 is output in response to the offset input voltage Vin received at the inverting input terminal from the output terminal of the offset configuration circuit 101 and the feedback signal V1 amplified in current mode output feedback signal received at the non-inverting input terminal from the output terminal of the feedback differential amplification circuit 108, and the current drive signal Dr2 is output to the output stage circuit 105 through the isolation circuit 104. The current mode output feedback signal functions to enable or disable the current driver circuit 103, wherein the current driver circuit 103 is enabled to indicate that the current driver circuit 103 outputs the current driver signal Dr2 to the output stage circuit 105 to control the output stage circuit 105 to provide power to the output device 106 (i.e., to drive the output device in a current mode) (see details below).
The feedback differential amplifying circuit 108 in fig. 2A includes a feedback operational amplifier OA3, a resistor R10, a resistor R11, a resistor R12, and a resistor R13. The feedback operational amplifier OA3 is connected between the operating power supply VCC and ground GND, and the feedback operational amplifier OA3 has a non-inverting input terminal, an inverting input terminal, and an output terminal. A first terminal of the resistor R13 is connected to a first terminal (the terminal voltage is V2) of the current detecting resistor R15 in the output stage circuit 105, a second terminal of the resistor R13 is connected to the first terminal of the resistor R12 and the non-inverting input terminal of the feedback operational amplifier OA3, and a second terminal of the resistor R12 is connected to the ground GND. A first terminal of the resistor R11 is connected to a second terminal (the terminal voltage is V3) of the current detecting resistor R15 in the output stage circuit 105, a second terminal of the resistor R11 is connected to a first terminal of the resistor R10 and an inverting input terminal of the feedback operational amplifier OA3, and a second terminal of the resistor R10 is connected to an output terminal of the feedback operational amplifier OA 3. In the feedback differential amplifier circuit 108, the following characteristics are obtained from the virtual short-circuit characteristics of the feedback operational amplifier OA 3: v1 ═ R12 ═ R11+ R10 ═ V2/[ R11 × (R13+ R12) ] -R10 × V3/R11, where R10, R11, R12, R13 are the resistance values of resistors R10, R11, R12, R13, respectively. If R10 ═ R12 and R11 ═ R13, then V1 ═ R10 ═ (V2-V3)/R11.
The feedback differential amplifying circuit 108 functions as: the voltage difference V2-V3 (current mode output feedback signal) across the current detection resistor R15 is received from the output stage circuit 105, and is proportionally amplified to output an amplified feedback signal V1. If the current through the output device 106 is assumed to be equal to the current through the current sensing resistor R15, V2-V3 is Iout R15, where R15 represents the resistance value of the current sensing resistor R15. By substituting V2-V3-Iout R15 into the above formula V1-R10 (V2-V3)/R11: v1 ═ Iout × R10 × R15/R11. By substituting V1 into VOA2 ═ V1 ═ R8/(R8+ R9), VOA2 ═ Iout × R10 × R15 × R8/[ (R8+ R9) × R11] can be obtained, where VOA2 is the voltage at the positive input terminal of the current output operational amplifier OA2 of the current control circuit 107 (of the current drive circuit 103). And Iout Vout/R device, where R device represents the resistance value of the output device 106, then VOA2 Vout R10R 15R 8/[ (R8+ R9) R11R device ]. Assuming R10 × R15 × R8/[ (R8+ R9) × R11 × R device ] ═ M, then VOA2 is Vout × M, where the value of M is related to the resistance value rsevic of the output device 106. As mentioned in the description of the voltage output operational amplifier OA1 of the voltage driving circuit 102, the voltage VOA1 at the non-inverting input of the voltage output operational amplifier OA1 is Vout L, where L is R6/(R5+ R6).
It is to be noted that when the output device 106 is connected to the output stage circuit 105, the voltage-mode output feedback signal output by the output stage circuit 105 to the voltage driving circuit 102 and the current-mode output feedback signal output to the current driving circuit 103 cause one of the voltage driving circuit 102 and the current driving circuit 103 to operate. Therefore, in the present application, by designing the specific circuit structures of the voltage driving circuit 102, the current driving circuit 103 and the output stage circuit 105, it is possible to: when the output device 106 connected to the output stage circuit 105 has a certain resistance R, L is M, the voltage VOA1 at the non-inverting input of the voltage output operational amplifier OA1 of the voltage driving circuit 102 is equal to the voltage VOA2 at the non-inverting input of the current output operational amplifier OA2 of the current driving circuit 103 (VOA1 is VOA 2); when the output device 106 is less than the resistance R, L < M, VOA1< VOA 2; when the output device 106 is greater than the resistance R, L > M, VOA1> VOA 2.
Since the voltage received by the inverting input terminal of the voltage output operational amplifier OA1 of the voltage drive circuit 102 and the voltage received by the inverting input terminal of the current output operational amplifier OA2 of the current drive circuit 103 are both the biased input voltage Vin, when the voltage VOA1 at the non-inverting input terminal of the voltage output operational amplifier OA1 is less than the voltage VOA2 at the non-inverting input terminal of the current output operational amplifier OA2 (i.e., VOA1< VOA2), the voltage Dr 1' output by the output terminal of the voltage output operational amplifier OA1 of the voltage drive circuit 102 is always less than the voltage Dr2 (current drive signal) output by the output terminal of the current output operational amplifier OA2 of the current drive circuit 103. Therefore, the voltage driving signal Dr1 output from the voltage driving circuit 102 after the voltage drop across the resistor R7 is always smaller than the current driving signal Dr2 output from the current driving circuit 103. The potential difference formed by the voltages Dr1 (lower) and Dr2 (higher) is applied to the isolation circuit 104, so that the isolation circuit 104 is turned on to provide the current driving signal Dr2 output by the current driving circuit 103 to the input terminal of the output stage circuit 105, while the resistor R7 prevents the voltage Dr1 'output by the voltage driving circuit 102 from being provided to the input terminal of the output stage circuit 105, so that the voltage Dr 1' output by the voltage driving circuit 102 does not affect the voltage control function of the current driving signal Dr2 output by the current driving circuit 103 on the output stage circuit 105. Only the current driving signal Dr2 output by the current driving circuit 103 is provided to the input of the output stage circuit 105 to control the output stage circuit 105 to provide power to the output device 106, which is referred to as driving the output device in current mode. That is, when the output device 106 is smaller than the above resistance value R, the output circuit 100 has a characteristic of driving the output device in a current mode.
When the voltage VOA1 at the non-inverting input of the voltage output operational amplifier OA1 is greater than the voltage VOA2 at the non-inverting input of the current output operational amplifier OA2 (i.e., VOA1> VOA2), the voltage Dr 1' output at the output of the voltage output operational amplifier OA1 of the voltage drive circuit 102 is always greater than the voltage Dr2 (current drive signal) output at the output of the current output operational amplifier OA2 of the current drive circuit 103. Since the voltage drop across the resistor R7 is small, the voltage driving signal Dr1 output by the voltage driving circuit 102 is also always smaller than the current driving signal Dr2 output by the current driving circuit 103. The potential difference formed by the voltages Dr1 (higher) and Dr2 (lower) is applied to the isolation circuit 104, so the isolation circuit 104 is turned off to isolate the current drive signal Dr2 output by the current drive circuit 103 from the input terminal of the output stage circuit 105, while the voltage Dr 1' output by the voltage drive circuit 102 outputs the voltage drive signal Dr1 to the input terminal of the output stage circuit 105 via the resistor R7. Only the voltage driving signal Dr1 output by the voltage driving circuit 102 is provided to the input of the output stage circuit 105 to control the output stage circuit 105 to provide power to the output device 106, which is referred to as driving the output device in a voltage mode. That is, when the output device 106 is larger than the resistance R, the output circuit 100 is characterized in that the output device is driven in a voltage type. It is noted that other circuit designs will be appreciated by those skilled in the art such that: when the output device 106 is greater than the resistance R, the output circuit 100 is characterized as driving the output device in a current mode, and when the output device 106 is less than the resistance R, the output circuit 100 is characterized as driving the output device in a voltage mode.
The isolation circuit 104 in fig. 2A is a diode D1, and the diode D1 has a positive terminal and a negative terminal, wherein the positive terminal of the diode D1 is connected to the output terminal of the current driving circuit 103, and the negative terminal of the diode D1 is connected to the output terminal of the voltage driving circuit 102 and the input terminal of the output stage circuit 105. Diode D1 is preferably a schottky diode. The isolation circuit 104 functions to: when the current driving circuit 103 is in an operating state, the current driving signal Dr2 output by the current driving circuit 103 drives the output stage circuit 105 via the isolation circuit 104, and at this time, the voltage driving circuit 102 is in an inactive state; however, when the voltage driving circuit 102 is in the operating state, the isolation circuit 104 disconnects the output of the current driving circuit 103 from the output stage circuit 105 because the output of the current driving circuit 103 is also connected to the input terminal of the output stage circuit 105.
In operation, when the current driving circuit 103 is in an active state, the voltage Dr1 'output by the output terminal of the voltage output operational amplifier OA1 of the voltage driving circuit 102 is less than the voltage Dr2 (current driving signal) output by the output terminal of the current output operational amplifier OA2 of the current driving circuit 103, the isolation circuit 104 is turned on to provide the voltage current driving signal Dr2 output by the current driving circuit 103 to the input terminal of the output stage circuit 105, and the resistor R7 prevents the voltage Dr 1' output by the voltage driving circuit 102 from being provided to the input terminal of the output stage circuit 105, so that the voltage driving circuit 102 is in an inactive state.
When the voltage driving circuit 102 is in an operating state, the voltage Dr1 'output from the output terminal of the voltage output operational amplifier OA1 of the voltage driving circuit 102 is greater than the voltage Dr2 (current driving signal) output from the output terminal of the current output operational amplifier OA2 of the current driving circuit 103, the isolation circuit 104 is turned off to isolate the current driving signal Dr2 output from the current driving circuit 103 from the input terminal of the output stage circuit 105, so that the current driving circuit 103 is in an inactive state, and the voltage Dr 1' output from the voltage driving circuit 102 outputs the voltage driving signal Dr1 to the input terminal of the output stage circuit 105 via the resistor R7.
In one embodiment, a capacitor may be connected between the output and inverting input of each of the voltage output operational amplifier OA1, the current output operational amplifier OA2, and the feedback operational amplifier OA3 to prevent the phase of the output of these feedback operational amplifiers from lagging behind the phase of their inverting input. The capacitor has a small capacitance, for example 330 pF. In another embodiment, the capacitor may not be connected to reduce the number of components in the output circuit. The output stage circuit 105 in fig. 2A includes a diode D2, a diode D3, a resistor R14, a switching element (e.g., PNP triode) Q1, a current sensing resistor R15, a diode D4, and a capacitor C2, which are in turn connected in series between a power supply VCC and a ground GND. The positive end of the diode D2 is connected to the power supply VCC, the negative end of the diode D2 is connected to the positive end of the diode D3, the negative end of the diode D3 is connected to the first end of the resistor R14, and the second end of the resistor R14 is connected to the emitter of the transistor Q1. The base of the transistor Q1 is connected to the second terminal of the resistor R7 of the voltage driving circuit 102 (the output terminal of the voltage driving circuit 102) through the connection line 114 and to the negative terminal of the diode D1 of the isolation circuit 104 (the output terminal of the isolation circuit 104) through the connection line 117 to receive the voltage driving signal Dr1 output by the voltage driving circuit 102 or the current driving signal Dr2 output by the current driving circuit 103. The collector of transistor Q1 is connected to a first terminal of current sensing resistor R15, and the second terminal of current sensing resistor R15 is connected to the positive terminal of diode D4. The negative terminal of the diode D4 is connected to the first terminal of the capacitor C2, and the second terminal of the capacitor C2 is connected to GND. A first terminal of the output device 106 is connected to a first terminal of the capacitor C2 by a connection 118 and a second terminal of the output device 106 is connected to a second terminal of the capacitor C2 by a connection 119 (both connected to ground). The output stage circuit 105 outputs a driving output voltage Vout and a driving output current Iout to the output device 106 through connection lines 118, 119. In fig. 2A, the negative terminal of the diode D4 of the output stage circuit 105 is connected to the first terminal of the capacitor C2, the second terminal of the capacitor C2 is connected to ground GND, and the output device 106 is connected in parallel with the capacitor C2. The capacitor C2 functions to filter the output voltage Vout and the output current Iout output to the output device 106 so that the output voltage Vout and the output current Iout change slowly when the resistance value of the output device 106 changes greatly.
In fig. 2A, a first terminal of the output device 106 is connected to a first terminal of a resistor R5 of the voltage driving circuit 102 (a feedback input terminal of the voltage driving circuit 102) through a connection line 120 to output a voltage type output feedback signal (Vout) to the voltage driving circuit 102. Also, a first end of the current detection resistor R15 of the output stage circuit 105 is connected to a first end of the resistor R13 of the feedback differential amplification circuit 108 of the current drive circuit 103 through the connection line 121, and a second end of the current detection resistor R15 is connected to a first end of the resistor R11 of the feedback differential amplification circuit 108 of the current drive circuit 103 through the connection line 121, so that a voltage difference (Iout × R15, i.e., a current type output feedback signal) across the current detection resistor R15 is output to the current drive circuit 103. The output stage circuit 105 outputting the voltage-type output feedback signal to the voltage driving circuit and outputting the current-type output feedback signal to the current driving circuit 103 causes one of the voltage driving circuit 102 and the current driving circuit 103 to operate, i.e., drive the output device 106 in a voltage-type manner or drive the output device 106 in a current-type manner (see above for details), at which time the driving signal Dr1 from the voltage driving circuit 102 or the current driving signal Dr2 from the current driving circuit 103 is output to the base of the transistor Q1 of the output stage circuit 105 to turn on the transistor Q1, so that the circuit of the output stage circuit 105 is turned on to drive the output device 106.
When the output device 106 is driven in a voltage mode, as shown in fig. 2A, the voltage output operational amplifier OA1 in the voltage driving circuit 102 has two operation states, the first operation state is an operation state in which the input signal is kept unchanged when the output circuit 100 is initially started, and the second operation state is an operation state in which the input signal is changed during the operation of the output circuit 100.
In the first operating state embodiment, if the input signal Sin is 5V at the initial start-up of the output circuit 100, so that the offset input voltage Vin is also 5V, the voltage at the inverting input of the voltage output operational amplifier OA1 of the voltage driving circuit 102 increases to 5V because the offset input voltage Vin is provided to the inverting input. While the non-inverting input terminal of the voltage output operational amplifier OA1 of the voltage driving circuit 102 is still 0V due to the initial start-up of the circuit, the voltage output from the output terminal of the voltage output operational amplifier OA1 increases from 0V to slightly more than 0V, which is a lower voltage (low level). This lower voltage is output to the base of transistor Q1 of output stage circuit 105, causing transistor Q1 to turn on (in an amplified or saturated state), output stage circuit 105 to be turned on, output current Iout provided by output stage circuit 105 to output device 106 to increase from 0A to greater than 0A, and output voltage Vout provided by output stage circuit 105 to output device 106 to increase from 0V to greater than 0V. The increase of the output voltage Vout in turn causes the voltage at the non-inverting input terminal of the voltage output operational amplifier OA1 to also increase from 0V to greater than 0V, so that the voltage output from the output terminal of the voltage output operational amplifier OA1 further increases, resulting in an increase in the base current of the transistor Q1 of the output stage circuit 105, a decrease in the voltage between the collector and the emitter of the transistor Q1, a further increase in the output voltage Vout, and a further increase in the output current Iout. As the above cycle, the output voltage Vout increases all the time. When the output voltage Vout rises to a certain value such that the voltage Vin at the inverting input terminal of the voltage output operational amplifier OA1 is equal to the voltage VOA1 at the non-inverting input terminal (i.e., Vin is equal to VOA1), the voltage output operational amplifier OA1 reaches a steady state due to the virtual short virtual break characteristic of the voltage output operational amplifier OA1, and therefore the voltage VOA1 at the non-inverting input terminal and the voltage at the output terminal of the voltage output operational amplifier OA1 are stable and do not change any more. Therefore, the voltage outputted from the voltage output operational amplifier OA1 to the base of the transistor Q1 of the output stage circuit 105 is stable and no longer varies, so that the voltage Vout and the current Iout outputted from the output stage circuit 105 to the output device 106 are also stable. As mentioned above, the voltage Vout output from the output stage circuit 105 to the output device 106 is fed back to the non-inverting input of the voltage output operational amplifier OA1 of the voltage driving circuit 102, where the voltage VOA1 is: VOA1 ═ Vout × R6/(R5+ R6). When the voltage output operational amplifier OA1 reaches a steady state, Vin is VOA1, so the input signal can control the voltage Vout output from the output stage 105 to the output device 106, which is Vin (R5+ R6)/R6.
In the second operating state embodiment, if the input voltage Vin increases to a certain voltage value, the voltage Vin at the inverting input of the voltage output operational amplifier OA1 also increases to the certain voltage value when the voltage output operational amplifier OA1 reaches a steady state through the first operating state. At this time, the voltage output from the output terminal of the voltage output operational amplifier OA1 decreases, which causes the base current of the transistor Q1 of the output stage circuit 105 to increase, the voltage between the collector and emitter of the transistor Q1 to decrease, and the output voltage Vout to increase, so that the voltage at the non-inverting input terminal of the voltage output operational amplifier OA1 increases. As the above cycle, the output voltage Vout increases, so that the voltage at the non-inverting input terminal of the voltage output operational amplifier OA1 increases until the voltage VOA1 at the non-inverting input terminal of the voltage output operational amplifier OA1 is equal to the voltage Vin at the inverting input terminal of the voltage output operational amplifier OA1, the voltage output operational amplifier OA1 reaches a steady state, and the voltage Vout and the current Iout output by the output stage circuit 105 to the output device 106 also reach a steady state accordingly. At this time, the input signal still controls the voltage Vout output from the output stage 105 to the output device 106, which is Vin (R5+ R6)/R6.
When the voltage output operational amplifier OA1 reaches a steady state through the first operating state, if the input voltage Vin decreases to a certain voltage value, the voltage Vin at the inverting input terminal of the voltage output operational amplifier OA1 decreases to the certain voltage value. At this time, the voltage output from the output terminal of the voltage output operational amplifier OA1 increases, which causes the base current of the transistor Q1 of the output stage circuit 105 to decrease, the voltage between the collector and emitter of the transistor Q1 to increase, and the output voltage Vout to decrease, so that the voltage at the non-inverting input terminal of the voltage output operational amplifier OA1 decreases. As the above cycle, the output voltage Vout is decreased, so that the voltage at the non-inverting input terminal of the voltage output operational amplifier OA1 is decreased until the voltage at the non-inverting input terminal of the voltage output operational amplifier OA1 is equal to the voltage Vin at the inverting input terminal of the voltage output operational amplifier OA1, the voltage output operational amplifier OA1 reaches a steady state, and the voltage Vout and the current Iout output from the output stage circuit 105 to the output device 106 are correspondingly stabilized. At this time, the input signal still controls the voltage Vout output from the output stage 105 to the output device 106, which is Vin (R5+ R6)/R6.
When the output device 106 is driven in current mode, as shown in fig. 2A, the current output operational amplifier OA2 in the current drive circuit 103 operates in the manner described above similarly to the voltage output operational amplifier OA1 in the voltage drive circuit 102. The difference is that the voltage difference (Iout × R15) output by the output stage circuit 105 to both ends of the current detection resistor R15 is fed back to the input terminal of the feedback differential amplifying circuit 108 of the current driving circuit 103, and the feedback differential amplifying circuit 108 performs proportional amplification to output the voltage V1 to the non-inverting input terminal of the current output operational amplifier OA2 in the current control circuit 107, so that the voltage VOA2 at the non-inverting input terminal is: VOA2 ═ Iout × R10 × R15 × R8/[ (R8+ R9) × R11 ]. When the current output operational amplifier OA2 reaches a steady state, Vin is VOA2, so the input signal can control the current Iout output from the output stage circuit 105 to the output device 106, which is Vin (R8+ R9) × R11/(R10R 15 × R8).
It is noted that in fig. 2A, the voltage output operational amplifier OA1 in the voltage drive circuit 102 and the current output operational amplifier OA2 in the current drive circuit 103 are both non-rail-to-rail operational amplifiers. According to the formula Dr1 ═ a1 × (VOA1-Vin) + VCC and the formula Dr2 ═ a2 × (VOA2-Vin) + VCC (where a1 and a2 are amplification factors of the voltage output operational amplifier OA1 and the current output operational amplifier OA2, respectively, and a1 and a2 are both large values), the actual values of the voltage drive signal Dr 1' output from the voltage output operational amplifier OA1 and the current drive signal Dr2 output from the current output operational amplifier OA2 are both smaller than the ideal values. Therefore, the diode D2 and the diode D3 are added to the output stage 105 of the present application, so that the voltage of the emitter of the transistor Q1 is reduced, and the transistor Q1 can still operate normally when its base is connected to the voltage driving signal Dr 1' and the current driving signal Dr2, which are smaller than the ideal value. Those skilled in the art will appreciate that in other embodiments, the voltage output operational amplifier OA1 and the current output operational amplifier OA2 may employ rail-to-rail operational amplifiers without the use of diode D2 and diode D3. Also, since rail-to-rail operational amplifiers are much more expensive than non-rail-to-rail operational amplifiers, the combined scheme of using non-rail-to-rail operational amplifiers and diodes shown in fig. 2A is less expensive than the scheme using rail-to-rail operational amplifiers.
In other embodiments, transistor Q1 may be a P-channel fet Q1 or a PMOS transistor Q1, as will be appreciated by those skilled in the art. Wherein the source of the P-channel fet Q1 is connected to the second terminal of the resistor R14, the gate of the P-channel fet Q1 is connected to the second terminal of the resistor R7 of the voltage driving circuit and to the negative terminal of the diode D1 of the isolation circuit 104 to receive the voltage driving signal Dr1 or the current driving signal Dr2, and the drain of the P-channel fet Q1 is connected to the first terminal of the current sensing resistor R15 and to the second terminal of the resistor R13 of the feedback differential amplifying circuit 108 of the current driving circuit 103.
Furthermore, the output circuit of the present invention does not require a current compensation circuit. Specifically, as described above, the present invention recognizes the output current Iout output to the output device 106 as being equal to the current flowing through the current detection resistor R15 in the calculation. However, in practice, when the output stage circuit 105 is driven by the current drive signal Dr2, as shown in fig. 2A, since the current flowing through the current detection resistor R15 in the output stage circuit 105 is not only output to the output device 106 but also shunted by the resistors R5 and R6 in the voltage drive circuit 102 in parallel with the output device 106, the output current Iout is made not to reach the current flowing through the current detection resistor R15. However, since the resistance values of the resistors R5 and R6 are much larger than the resistance value of the output device 106, the current shunted by the resistors R5 and R6 from the current detecting resistor R15 is small, and thus the error caused by considering the output current Iout output to the output device 106 to be equal to the current flowing through the current detecting resistor R15 is small. For example, in one embodiment, the resistors R5 and R6 are both 20k Ω, the output device 106 has a resistance of 500 Ω, and if the output current to the output device 106 is in the range of 4-20mA, then when the current value flowing through the current sensing resistor R15 is 20mA, for example, the current value shunted by the resistors R5 and R6 is about 0.25mA, and the final output current to the output device 106 is about 19.75mA with an error of only 1.25%. Because the error of the output current Iout caused by the resistors R5 and R6 is small and negligible, the invention does not need to adopt an additional current compensation circuit.
Fig. 2B is a detail of a circuit diagram of exemplary individual blocks of one embodiment of the output circuit 100 according to the present invention shown in fig. 1B. The structure of the output circuit 100 in fig. 2B is substantially the same as the structure of the output circuit 100 in fig. 2A, except for the following aspects: in fig. 2B, the output terminal of the voltage driving circuit 102 (i.e., the output terminal of the voltage output operational amplifier OA1) is connected to the input terminal of the isolation circuit 104 (i.e., the positive terminal of the diode D1) by the connection line 124 to output the voltage driving signal Dr1 to the isolation circuit 104, and the output terminal of the isolation circuit 104 (i.e., the negative terminal of the diode D1) is connected to the input terminal of the output stage circuit 105 (i.e., the base of the transistor Q1) by the connection line 127 to output the voltage driving signal Dr1 output by the voltage driving circuit 102 to the output stage circuit 105. The output terminal of the voltage driving circuit 102 (i.e., the output terminal of the voltage output operational amplifier OA1) is further connected to the control input terminal of the offset configuration circuit 101 via the connection line 126 to output the voltage driving signal Dr1 to the offset configuration circuit 101, thereby controlling the offset configuration circuit 101 to perform the first or second offset on the input signal Sin. In one embodiment, the control output of the current driving circuit 103 (i.e., the output of the current output operational amplifier OA2) is connected to the control input of the offset configuration circuit 101 via connection 116 to output the intermediate current driving signal Dr 2' to the offset configuration circuit 101 to control the offset configuration circuit 101 to perform the first or second offset on the input signal Sin. An output terminal of the current output operational amplifier OA2 of the current driving circuit 103 is connected to a first terminal of the resistor R7, and a second terminal of the resistor R7 (i.e., an output terminal of the current driving circuit 103) is connected to an output terminal of the isolation circuit 104 and an input terminal of the output stage circuit 105 through a connection line 125 to output a current driving signal Dr2 to the output stage circuit 105.
In operation, the operation of the voltage output operational amplifier OA1 and the current output operational amplifier OA2 in fig. 2B are the same as fig. 2A, except that: in FIG. 2B, the output of the voltage output operational amplifier OA1 outputs the voltage drive signal Dr1, and the output of the current output operational amplifier OA2 outputs the intermediate current drive signal Dr 2'. When the voltage VOA1 at the non-inverting input of the voltage output operational amplifier OA1 is less than the voltage VOA2 at the non-inverting input of the current output operational amplifier OA2 (i.e., VOA1< VOA2), the voltage Dr1 (voltage drive signal) output by the output of the voltage output operational amplifier OA1 of the voltage drive circuit 102 is always less than the voltage Dr 2' output by the output of the current output operational amplifier OA2 of the current drive circuit 103. Since the voltage drop across the resistor R7 is small, the voltage driving signal Dr1 output by the voltage driving circuit 102 is also always smaller than the current driving signal Dr2 output by the current driving circuit 103. The potential difference formed by the voltages Dr1 (lower) and Dr2 (higher) is applied to the isolation circuit 104, so that the isolation circuit 104 is turned off to isolate the voltage drive signal Dr1 output by the voltage drive circuit 102 from the input terminal of the output stage circuit 105, while the current drive circuit 103 outputs the current drive signal Dr2 to the input terminal of the output stage circuit 105. Only the current driving signal Dr2 output by the current driving circuit 103 is provided to the input of the output stage circuit 105 to control the output stage circuit 105 to provide power to the output device 106, which is referred to as driving the output device in current mode.
Also, when the voltage VOA1 at the non-inverting input terminal of the voltage output operational amplifier OA1 is greater than the voltage VOA2 at the non-inverting input terminal of the current output operational amplifier OA2 (i.e., VOA1> VOA2), the voltage Dr1 (voltage drive signal) output by the output terminal of the voltage output operational amplifier OA1 of the voltage drive circuit 102 is always greater than the voltage Dr 2' output by the output terminal of the current output operational amplifier OA2 of the current drive circuit 103. Therefore, the voltage driving signal Dr1 output by the voltage driving circuit 102 is always larger than the current driving signal Dr2 output by the current driving circuit 103 after the voltage drop through the resistor R7. The potential difference formed by the voltages Dr1 (higher) and Dr2 (lower) is applied to the isolation circuit 104, so that the isolation circuit 104 is turned on to provide the voltage driving signal Dr1 output by the voltage driving circuit 102 to the input terminal of the output stage circuit 105, while the resistor R7 prevents the voltage Dr2 'output by the current driving circuit 103 from being provided to the input terminal of the output stage circuit 105, so that the voltage Dr 2' output by the current driving circuit 103 does not affect the voltage control function of the voltage driving signal Dr1 output by the voltage driving circuit 102 on the output stage circuit 105. Only the voltage driving signal Dr1 output by the voltage driving circuit 102 is provided to the input of the output stage circuit 105 to control the output stage circuit 105 to provide power to the output device 106, which is referred to as driving the output device in a voltage mode.
In one embodiment of the present application, the parameters of the various components in the output circuit 100 may be set as in table 1 below:
TABLE 1
Figure BDA0002372604420000241
Those skilled in the art will appreciate that other parameters may be set for these elements in the output circuit 100.
In the present application, when the output device 106 is connected to the output stage circuit 105, the voltage-type output feedback signal output by the output stage circuit 105 to the voltage driving circuit 102 and the current-type output feedback signal output by the current driving circuit 103 automatically select one of the voltage driving circuit 102 and the current driving circuit 103 to operate, so as to automatically select whether to drive the output device 106 in the voltage type or to drive the output device 106 in the current type. As will be appreciated by those skilled in the art, the self-configuring output circuit of the present application may employ other circuit configurations and arrangements to carry out the functions of the various circuits and arrangements of FIGS. 1A and 1B.
For the existing output circuits, some conventional methods use a large number of electronic components and complex circuits, are high in cost, and require current compensation, while other conventional methods cannot realize automatic selection of voltage output and current output. Compared with the prior art, the output circuit in the application has the following beneficial technical effects: the isolation circuit is used for isolating the voltage driving circuit or the current driving circuit from the output stage circuit so as to realize automatic selection of voltage-type ground driving output equipment and current-type ground driving output equipment; the isolation circuit, especially the diode, is simple, fast and economical, so that the circuit is simple, the elements are few, the price is low and the occupied substrate space is small; the voltage driving circuit and the current driving circuit have simple circuit structures, few elements, low price and small occupied substrate space; the circuit is reasonably designed and the resistance values of the resistors are selected, so that a current compensation circuit is not needed when the current mode drives the output equipment, the circuit structure is simple, and the number of elements is small.
Although the present invention has been described with reference to the particular embodiments shown in the drawings, it should be understood that many variations of the output circuit of the present invention are possible without departing from the spirit and scope and background of the teachings of the present invention. Those of ordinary skill in the art will also recognize different ways to alter the parameters of the disclosed embodiments of the invention, such as resistance, capacitance, or type of elements, within the spirit and scope of the invention and claims.

Claims (21)

1. An automatically configurable output circuit (100), comprising:
a voltage drive circuit (102), the voltage drive circuit (102) configured to generate a voltage drive signal (Dr1), the voltage drive circuit (102) having an output;
a current drive circuit (103), the current drive circuit (103) configured to generate a current drive signal (Dr2), the current drive circuit (103) having an output;
an isolation circuit (104);
an output stage circuit (105), said output stage circuit (105) having an input, said output of said voltage driver circuit (102) being coupled to said input of said output stage circuit (105), said output of said current driver circuit (103) being coupled to said input of said output stage circuit (105) through said isolation circuit (104).
2. An automatically configurable output circuit (100), comprising:
a voltage drive circuit (102), the voltage drive circuit (102) configured to generate a voltage drive signal (Dr1), the voltage drive circuit (102) having an output;
a current drive circuit (103), the current drive circuit (103) configured to generate a current drive signal (Dr2), the current drive circuit (103) having an output;
an isolation circuit (104);
an output stage circuit (105), said output stage circuit (105) having an input, said output of said voltage driver circuit (102) being coupled to said input of said output stage circuit (105) through said isolation circuit (104), said output of said current driver circuit (103) being coupled to said input of said output stage circuit (105).
3. The output circuit (100) of claim 1 or 2, wherein:
the voltage drive circuit (102) receives a voltage mode output feedback signal from the output stage circuit (105), and the current drive circuit (103) receives a current mode output feedback signal from the output stage circuit (105).
4. The output circuit (100) of claim 1 or 2, wherein:
the output stage circuit (105) comprises two outputs, the two outputs of the output stage circuit (105) are connected to an output device (106),
the output stage circuit (105) is configured to be able to detect a characteristic of the output device (106), the characteristic of the output device (106) being an impedance of the output device (106).
5. The output circuit (100) of claim 4, wherein:
the voltage drive signal (Dr1) is always higher than the current drive signal (Dr 2); or the voltage drive signal (Dr1) is always lower than the current drive signal (Dr 2).
6. The output circuit (100) of claim 1, wherein:
the isolation circuit (104) isolates the output of the current drive circuit (103) from the input of the output stage circuit (105) when the current drive signal (Dr2) is always lower than the voltage drive signal (Dr 1).
7. The output circuit (100) of claim 2, wherein:
the isolation circuit (104) isolates the output of the voltage drive circuit (102) from the input of the output stage circuit (105) when the voltage drive signal (Dr1) is always lower than the current drive signal (Dr 2).
8. The output circuit (100) of claim 6 or 7, wherein:
the isolation circuit (104) is a two-terminal isolation circuit.
9. The output circuit (100) of claim 6 or 7, wherein:
the isolation circuit (104) is a unidirectional isolation circuit.
10. The output circuit (100) of claim 8, wherein:
the isolation circuit (104) is a diode.
11. The output circuit (100) of claim 1 or 2, wherein:
the current drive circuit (103) does not include a current compensation circuit.
12. The output circuit (100) of claim 1 or 2, further comprising:
an offset configuration circuit (101), the offset configuration circuit (101) being configured to receive a varying input signal (Sin) and to selectively offset a variation range of the input signal (Sin) to a first variation range or a second variation range based on a signal received from the current driving circuit (103) or a signal received from the voltage driving circuit (102) to generate an offset input signal (Vin), the first variation range and the second variation range being different,
the offset configuration circuit (101) comprises an output terminal, the voltage driving circuit (102) comprises an input terminal, the current driving circuit (103) comprises an input terminal,
the output terminal of the offset configuration circuit (101) is connected to the input terminal of the voltage driving circuit (102) and the input terminal of the current driving circuit (103) to output the offset input signal (Vin) to the voltage driving circuit (102) and the current driving circuit (103).
13. The output circuit (100) of claim 1 or 2, wherein:
the current drive circuit (103) comprises a current control circuit (107) and a feedback differential amplification circuit (108), the current control circuit (107) and the feedback differential amplification circuit (108) being connected, the feedback differential amplification circuit (108) being configured to receive a current mode output feedback signal from the output stage circuit (105) for amplifying the current mode output feedback signal, the current control circuit (107) being configured to generate the current drive signal (Dr2) based on the amplified signal received from the feedback differential amplification circuit (108).
14. The output circuit (100) of claim 12, wherein:
the offset configuration circuit (101) further comprises a voltage division offset circuit (201) and an offset control circuit (202), the offset control circuit (202) being configured to control the voltage division offset circuit (201) to selectively offset a variation range of the input signal (Sin) to the first variation range or the second variation range based on the signal received from the current drive circuit (103) or the signal received from the voltage drive circuit (102).
15. The output circuit (100) of claim 14, wherein: the offset control circuit (202) includes a switching element (Q2).
16. The output circuit (100) of claim 14, wherein:
the voltage drive circuit (102) comprises a voltage output operational amplifier (OA1), the voltage output operational amplifier (OA1) having a non-inverting input, an inverting input, and an output;
wherein the inverting input of the voltage output operational amplifier (OA1) is connected to the output of the offset configuration circuit (101), and the non-inverting input of the voltage output operational amplifier (OA1) receives an output voltage signal (Vout) output by the output stage circuit (105) to an output device (106);
the output of the voltage output operational amplifier (OA1) is coupled to the output of the isolation circuit (104) and the input of the output stage circuit (105) when the output of the current drive circuit (103) is connected to the input of the output stage circuit (105) through the isolation circuit (104);
the output of the voltage output operational amplifier (OA1) is connected to the input of the isolation circuit (104) when the output of the voltage drive circuit (102) is connected to the input of the output stage circuit (105) through the isolation circuit (104).
17. The output circuit (100) of claim 13, wherein:
the feedback differential amplification circuit (108) comprises a feedback operational amplifier (OA3), the feedback operational amplifier (OA3) having a non-inverting input, an inverting input and one output, the non-inverting input and the inverting input of the feedback operational amplifier (OA3) being coupled to the output stage circuit (105), and the output of the feedback operational amplifier (OA3) being connected to the current control circuit (107), wherein the feedback operational amplifier (OA3) is configured to proportionally amplify an output current signal (Iout) output by the output stage circuit (105) to an output device (106) to output a feedback amplified voltage signal (V1).
18. The output circuit (100) of claim 17, wherein:
the current control circuit (107) comprises a current output operational amplifier (OA2),
wherein the current output operational amplifier (OA2) has a non-inverting input, an inverting input, and an output, the inverting input of the current output operational amplifier (OA2) is connected to the output of the offset configuration circuit (101), the output of the feedback operational amplifier (OA3) of the feedback differential amplification circuit (108) is coupled to the non-inverting input of the current output operational amplifier (OA2), and the output of the current output operational amplifier (OA2) is connected to the input of the isolation circuit (104) when the output of the current drive circuit (103) is connected to the input of the output stage circuit (105) through the isolation circuit (104);
the output of the current output operational amplifier (OA2) is coupled to the output of the isolation circuit (104) and the input of the output stage circuit (105) when the output of the voltage drive circuit (102) is connected to the input of the output stage circuit (105) through the isolation circuit (104).
19. The output circuit (100) of claim 10, wherein:
the diode (D1) has a positive terminal and a negative terminal, wherein the positive terminal of the diode (D1) is the input terminal of the isolation circuit (104) and the negative terminal of the diode (D1) is the output terminal of the isolation circuit (104).
20. The output circuit (100) of claim 17, wherein:
the output stage circuit (105) comprises:
a current sensing resistor (R15), both ends of the current sensing resistor (R15) being coupled to the non-inverting input and the inverting input of the feedback operational amplifier (OA3), respectively.
21. The output circuit (100) of claim 1 or 2, wherein:
the output stage circuit (105) further comprises:
a switching element (Q1), the switching element (Q1) configured to receive the voltage drive signal (Dr1) or the current drive signal (Dr2) to conduct to thereby cause the circuitry of the output stage circuit to communicate to drive an output device (106).
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