CN113140538A - Adapter plate, packaging structure and manufacturing method of adapter plate - Google Patents
Adapter plate, packaging structure and manufacturing method of adapter plate Download PDFInfo
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- CN113140538A CN113140538A CN202110431865.3A CN202110431865A CN113140538A CN 113140538 A CN113140538 A CN 113140538A CN 202110431865 A CN202110431865 A CN 202110431865A CN 113140538 A CN113140538 A CN 113140538A
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- adapter plate
- interposer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
Abstract
The invention provides an adapter plate, a packaging structure and a manufacturing method of the adapter plate, and relates to the technical field of packaging. The adapter plate comprises an adapter plate body, wherein a first electrical element is arranged in the adapter plate body and is electrically connected with the inside of the adapter plate body. The packaging structure comprises a mainboard and a patch panel, wherein the patch panel is attached to the mainboard, and related electronic elements can be attached between the patch panel and the mainboard according to actual design requirements. The method for manufacturing the adapter plate comprises the steps of manufacturing a resin layer on a substrate, embedding an electronic element into the resin layer, and manufacturing a through hole in the resin layer, wherein the electronic element is electrically connected with a circuit layer through the through hole, and the circuit layer is electrically connected through the through hole. This application keysets is through burying electronic component in self inner space to improve self inner space's utilization ratio, and then saved packaging structure's shared space from to a great extent, improve packaging structure's compact structure nature.
Description
Technical Field
The invention relates to the technical field of packaging, in particular to an adapter plate, a packaging structure and a manufacturing method of the adapter plate.
Background
At present, the adapter plate is mostly of a simple laminated structure, the thickness of a plastic package body is mostly about 1 mm, a welding point of the adapter plate needs to be exposed out of the plastic package body, the height of a used solder ball is generally about 100 microns, the thickness of a PCB plate is about 900 microns approximately, and if the size of the adapter plate is 3 x 3 square millimeters, the volume of 8.1 cubic millimeters is wasted.
That is, the internal space of the current adapter plate is wasted to some extent.
Disclosure of Invention
The present invention provides an interposer, a package structure and a method for manufacturing the interposer, which can effectively improve space utilization.
Embodiments of the invention may be embodied as follows:
in a first aspect, an embodiment of the present invention provides an interposer body, which includes a first electronic component disposed inside the interposer body and electrically connected to the interposer body.
In an alternative embodiment, the resin layer is provided with a first via hole, and the first electronic component is provided on the resin layer and electrically connected to the second circuit layer through the first via hole.
In an alternative embodiment, the resin layer is provided with a second via hole, and the first line layer and the second line layer are electrically connected through the second via hole.
In an alternative embodiment, the first electronic component is at least one of a chip, a resistor and a capacitor.
In a second aspect, an embodiment of the present invention provides a package structure, where the package structure is based on the interposer described in any one of the foregoing embodiments, and the interposer is attached to a motherboard.
In an optional embodiment, the package structure includes a second electronic component located between the interposer body and the motherboard, and the second electronic component is attached to a side of the surface of the interposer close to the motherboard and electrically connected to the interposer.
In an optional embodiment, the package structure includes a second electronic component located between the interposer body and the motherboard, and the second electronic component is attached to a side of the surface of the motherboard close to the interposer and electrically connected to the motherboard.
In an optional embodiment, the package structure includes a plurality of stacked interposer boards, the interposer boards are sequentially and mechanically connected and electrically connected, and one of the interposer boards located at an outermost layer is attached to the motherboard and electrically connected to the motherboard.
In an optional implementation manner, the package structure further includes a plastic package layer and a shielding layer, the plastic package layer is disposed on the motherboard and covers one side of the interposer close to the motherboard, the shielding layer covers a surface of the plastic package layer, and one side of the interposer far from the motherboard is exposed outside the plastic package layer and the shielding layer.
In a third aspect, an embodiment of the present invention provides a method for manufacturing an interposer, where the method for manufacturing an interposer includes:
manufacturing a resin layer on a first substrate and embedding the electronic element in the resin layer;
manufacturing the first via hole and the second via hole in the resin layer, wherein one end of the first via hole is electrically connected with the electronic element, and one end of the second via hole is electrically connected with the first substrate;
and a second substrate is attached to one side, far away from the first substrate, of the resin layer, the second substrate is electrically connected with one end, far away from the electronic element, of the first via hole, and the second substrate is electrically connected with the other end of the second via hole.
The embodiment of the invention has the beneficial effects that:
the chip-embedded adapter plate has the advantages that the electronic elements (such as chips, resistors and the like) are embedded into the internal space of the chip-embedded adapter plate, so that the utilization rate of the internal space of the chip-embedded adapter plate is improved, the occupied space of the packaging structure is saved to a great extent, the structural compactness of the packaging structure is improved, and a new idea can be provided for further miniaturization of system-level packaging.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a schematic diagram of a package structure according to an embodiment of the invention;
FIG. 2 is a schematic diagram of an interposer in an embodiment of the invention;
fig. 3 is a schematic view of a first structure of the interposer connected to the motherboard according to the embodiment of the present invention;
fig. 4 is a second schematic structural diagram of the interposer connected to the motherboard according to the embodiment of the present invention;
fig. 5a to 5h are flow charts of interposer manufacturing in the embodiment of the present invention.
Icon: 1000-package structure; 100-common type shielding; 300-partition shielding; 500-a main board; 510-a third electronic component; 700-an adapter plate; 710-a first electronic component; 720-a second electronic component; 730-first line layer; 740-a resin layer; 741 — a first via; 743 — a second via; 750-a second line layer; 760-solder mask layer; 770-solder ball; 771-first solder ball; 772 "second solder ball; 773-third tin ball; 774 fourth solder ball; 780-a first substrate; 790-a second substrate; 900-plastic packaging layer.
Detailed Description
At present, the adapter plate is mostly of a simple laminated structure, so that the available three-dimensional space in the adapter plate is almost wasted, and the space utilization rate of electronic elements in the packaging structure is low due to the spatial layout of the electronic elements.
The embodiment of the invention provides an adapter plate, a packaging structure and a manufacturing method of the adapter plate. According to the practical design, the related electronic elements meeting the design function of the adapter plate are embedded in the adapter plate, so that a certain space in the packaging structure is saved, further miniaturization of system-level packaging can be met, the packaging volume can be reduced, the space can be saved, and the connecting line between the elements can be shortened, so that the resistance is reduced.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. indicate an orientation or a positional relationship based on that shown in the drawings or that the product of the present invention is used as it is, this is only for convenience of description and simplification of the description, and it does not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
Referring to fig. 1, the present embodiment provides a package structure 1000, where the package structure 1000 includes a motherboard 500, an interposer 700, a molding compound 900, and a shielding layer (including a partition shield 300 and a common shield 100).
The main Board 500 is a Printed Circuit Board (PCB), and the main Board 500 has a first side and a second side opposite to each other. In this embodiment, the first side and the second side are both provided with a wiring layer and a third electronic component 510 (such as a chip, a resistor or a capacitor) in communication with the wiring layer to support the required functions of the package structure 1000.
It should be noted that in other embodiments, the main board 500 may be provided with a circuit layer and a third electronic element 510 communicating with the circuit layer only on the first side.
The interposer 700 may be disposed on the first side of the motherboard 500 via solder balls 770, and electronic components meeting design requirements are embedded in the interposer 700 according to actual design requirements. In order to fully utilize the three-dimensional space of the interposer 700, electronic components meeting design functions can be soldered between the interposer 700 and the motherboard 500 according to actual design requirements, so as to achieve the purpose of further miniaturization.
The plastic package layer 900 is disposed on the motherboard 500 and covers one side of the interposer 700 close to the motherboard 500, in detail, the plastic package layer 900 is disposed on the first side surface and the second side surface of the motherboard 500 at the same time, the plastic package layer 900 disposed on the first side surface is a first plastic package layer, the plastic package layer 900 disposed on the second side surface is a second plastic package layer, the first plastic package layer covers one side of the interposer 700 close to the motherboard 500, one side of the interposer 700 far away from the motherboard 500 exposes the first plastic package layer and is flush with one side of the first plastic package layer far away from the motherboard 500 (i.e. both are located on the same surface), so as to improve the smoothness of the package structure 1000.
Further, the molding compound layer 900 may be made of epoxy resin material, and is disposed on the main board 500 by an injection molding process to encapsulate the interposer 700, so as to protect the related components and provide a carrier for the shielding layer (including the partition shield 300 and the common type shield 100).
The shielding layer comprises a subarea shielding 300 and a common type shielding 100, wherein the subarea shielding 300 can be formed by filling conductive silver colloid, and the conductive silver colloid is filled on the plastic package body. The common-mode shield 100 can be formed by a coating process or a coating process, so that the shielding layer and the package are completely fused together, and the module has a shielding function and does not need an additional shielding cover.
The shielding layer covers the surface of the plastic package layer 900, one side of the adapter plate 700, which is far away from the motherboard 500, is exposed outside the shielding layer, in detail, a notch is arranged at a position of the shielding layer, which corresponds to one side of the adapter plate 700, which is far away from the motherboard 500, and one side of the adapter plate 700, which is far away from the motherboard 500, is exposed through the notch. The partition shield 300 is disposed on the molding layer 900 and the partition shield 300 may be formed by filling silver paste. The conformal shield 100 is disposed on the partition shield 300 and covers the molding layer 900 with the partition shield 300.
In the packaging structure in the scheme, relevant electronic elements meeting the design function of the adapter plate are embedded in the adapter plate according to the actual design, so that certain space in the packaging structure is saved, further miniaturization of system-level packaging can be met, the packaging volume can be reduced, the space is saved, and connecting circuits among elements can be shortened so as to reduce the resistance.
Referring to fig. 2, the interposer 700 includes an interposer body, and the first electronic component 710 is disposed inside the interposer body and electrically connected to the interposer body. The interposer body includes a first wiring layer 730, a resin layer 740, a second wiring layer 750, and a solder resist layer 760.
Relevant electronic elements required by design are embedded in the adapter plate 700, so that the three-dimensional space inside the adapter plate 700 is better utilized, the number of layers of the adapter plate 700 is overlapped according to the actual design condition, the adapter plates 700 are sequentially and mechanically and electrically connected, and one adapter plate 700 positioned at the outermost layer is arranged on the mainboard 500 and electrically connected with the mainboard 500.
The solder mask 760 of the interposer 700 is coated on the circuit layer at locations where soldering is not desired, to prevent soldering at those locations.
The circuit layers in the interposer 700 are formed by etching the substrate to form the desired circuit board and thus the desired circuit layers.
Optionally, the substrate of this embodiment may be a copper foil substrate.
In this embodiment, the resin layer 740 is coated between the circuit layers, and the resin layer 740 is provided with the first via 741 and the second via 743, and the first electronic component 710 (such as a chip, a resistor, a capacitor, or the like) is disposed in the resin layer 740 according to actual requirements.
Further, in this embodiment, the circuit layer and the electronic component are electrically connected through the first via 741, and the first circuit layer 730 and the second circuit layer 750 of the interposer 700 are electrically connected through the second via 743.
Optionally, solder balls 770 are implanted on the circuit board to connect the interposer 700 with the motherboard 500 or a plurality of interposers 700.
Optionally, the number of the solder balls 770 may be designed according to actual design requirements, and is not limited to the number of the solder balls 770 in the embodiment of the present application.
Referring to fig. 3 to 4, in other embodiments of the invention, the second electronic component 720 may be disposed between the interposer 700 and the motherboard 500 by fully utilizing a three-dimensional space in the interposer according to actual design conditions. The second electronic component 720 may be disposed on the surface of the interposer 700 and near one side of the motherboard 500 to make full use of the three-dimensional space. The interposer 700 and the motherboard 500 are connected by solder balls 770.
Optionally, the second electronic component 720 may also be disposed on the surface of the motherboard 500 and near the interposer 700 to make full use of the three-dimensional space.
Further, referring to fig. 5a to 5f, the method for manufacturing the interposer 700 includes the following steps:
firstly, preparing a chip, and grinding and cutting the wafer to obtain the chip or other prepared corresponding electronic elements.
Next, a substrate is prepared, and a first substrate 780 is prepared, wherein the substrate may be a copper foil substrate, and a resin layer is coated on the prepared substrate.
The prepared chips are then disposed on the coated resin layer 740, followed by coating a thickness of resin and allowing the chips to be disposed in the resin layer 740.
Next, drilling holes in the resin layer 740 and performing copper deposition to metallize the holes to form vias, so that the electronic components in the resin layer 740 are electrically connected with the circuit layer or the circuit layers.
Next, the second substrate 790 is laminated with the resin layer 740, and the substrates on both sides of the resin layer 740 are etched to obtain the wiring required for the actual design.
It should be noted that the interposer 700 of the present embodiment may be manufactured by repeating the steps of preparing a substrate, coating a resin, mounting related electronic components, laminating the substrate, and etching the substrate according to the layer number required by the specific interposer 700.
Next, a solder resist ink is applied to the portion of the outermost wiring board obtained from the etched substrate, which is not to be soldered, to form a solder resist layer 760.
The obtained interposer 700 is then baked to remove moisture and humidity, and to remove moisture contained in the PCB or absorbed from the outside.
Alternatively, solder paste printing or solder ball 770 implantation may be performed to connect the interposer 700 and the main board 500 or the interposer 700, followed by cleaning.
In this embodiment, the solder balls 770 include a first solder ball 771, a second solder ball 772, a third solder ball 773 and a fourth solder ball 774, but in actual design, different numbers of solder balls 770 can be designed according to actual requirements.
The resulting interposer 700 is then baked again to remove moisture from the board.
The resulting interposer 700 is finally packaged for use.
By embedding electronic components required by actual design in the resin layer 740 of the interposer 700, the space in the interposer 700 can be effectively used, and the package structure 1000 can be further miniaturized.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. An interposer, comprising:
an adapter plate body;
the first electronic element is arranged inside the adapter plate body and electrically connected with the adapter plate body.
2. The interposer as recited in claim 1, wherein:
the adapter plate body comprises a first circuit layer, a resin layer, a second circuit layer and a solder mask layer;
the resin layer is provided with first via hole, first electronic component set up in the resin layer just passes through first via hole is connected with second circuit layer electricity.
3. The interposer as recited in claim 2, wherein:
the resin layer is provided with a second via hole, and the first circuit layer and the second circuit layer are electrically connected through the second via hole.
4. The interposer as recited in claim 1, wherein:
the first electronic component is at least one of a chip, a resistor and a capacitor.
5. A package comprising a motherboard and the interposer of any of claims 1-4, wherein the interposer is attached to the motherboard.
6. The package structure of claim 5, wherein: the electronic device comprises a second electronic element positioned between an adapter plate body and a mainboard, wherein the second electronic element is attached to one side, close to the mainboard, of the surface of the adapter plate and is electrically connected with the adapter plate.
7. The package structure of claim 5, wherein: the electronic device comprises a second electronic element positioned between the adapter plate body and the mainboard, wherein the second electronic element is attached to one side, close to the adapter plate, of the surface of the mainboard and is electrically connected with the mainboard.
8. The package structure according to claim 5, comprising a plurality of stacked interposer boards, wherein the interposer boards are sequentially mechanically and electrically connected, and one of the interposer boards at an outermost layer is attached to and electrically connected with the motherboard.
9. The package structure according to claim 5, further comprising a molding compound layer and a shielding layer, wherein the molding compound layer is disposed on the motherboard and covers a side of the interposer close to the motherboard, the shielding layer covers a surface of the molding compound layer, and a side of the interposer far from the motherboard is exposed outside the molding compound layer and the shielding layer.
10. A manufacturing method of an adapter plate is characterized by comprising the following steps:
manufacturing a resin layer on a first substrate and embedding a first electronic element in the resin layer;
manufacturing a first through hole and a second through hole in the resin layer, wherein one end of the first through hole is electrically connected with the electronic element, and one end of the second through hole is electrically connected with the first substrate;
and a second substrate is attached to one side, far away from the first substrate, of the resin layer, the second substrate is electrically connected with one end, far away from the electronic element, of the first via hole, and the second substrate is electrically connected with the other end of the second via hole.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110431865.3A CN113140538A (en) | 2021-04-21 | 2021-04-21 | Adapter plate, packaging structure and manufacturing method of adapter plate |
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| CN202110431865.3A CN113140538A (en) | 2021-04-21 | 2021-04-21 | Adapter plate, packaging structure and manufacturing method of adapter plate |
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| CN113140538A true CN113140538A (en) | 2021-07-20 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115939108A (en) * | 2021-08-23 | 2023-04-07 | 荣耀终端有限公司 | Electronic equipment and chip packaging method |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050247665A1 (en) * | 2004-05-10 | 2005-11-10 | Shinko Electric Industries Co., Ltd. | Method of manufacturing an electronic parts packaging structure |
| CN102648667A (en) * | 2009-09-15 | 2012-08-22 | R&D电路股份有限公司 | Embedded components in interposer board for improving power gain (distribution) and power loss (dissipation) in interconnect configuration |
| CN103296008A (en) * | 2012-02-22 | 2013-09-11 | 中国科学院微电子研究所 | TSV or TGV pinboard, 3D packaging and manufacture method thereof |
| CN103929896A (en) * | 2014-05-07 | 2014-07-16 | 上海美维科技有限公司 | Method for manufacturing printed circuit board with internally-buried chip |
| CN107768349A (en) * | 2017-09-25 | 2018-03-06 | 江苏长电科技股份有限公司 | Two-sided SiP three-dimension packagings structure |
| CN111010815A (en) * | 2019-12-27 | 2020-04-14 | 安捷利（番禺）电子实业有限公司 | Semiconductor chip embedded circuit board and processing method and processing device thereof |
| CN111010801A (en) * | 2019-12-30 | 2020-04-14 | 安捷利（番禺）电子实业有限公司 | Double-side heat dissipation chip packaging structure, method and device |
| CN210926014U (en) * | 2019-12-27 | 2020-07-03 | 安捷利（番禺）电子实业有限公司 | Sip packaging structure of semiconductor chip |
-
2021
- 2021-04-21 CN CN202110431865.3A patent/CN113140538A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050247665A1 (en) * | 2004-05-10 | 2005-11-10 | Shinko Electric Industries Co., Ltd. | Method of manufacturing an electronic parts packaging structure |
| CN102648667A (en) * | 2009-09-15 | 2012-08-22 | R&D电路股份有限公司 | Embedded components in interposer board for improving power gain (distribution) and power loss (dissipation) in interconnect configuration |
| CN103296008A (en) * | 2012-02-22 | 2013-09-11 | 中国科学院微电子研究所 | TSV or TGV pinboard, 3D packaging and manufacture method thereof |
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| CN116031247A (en) * | 2021-08-23 | 2023-04-28 | 荣耀终端有限公司 | Electronic equipment and chip packaging method |
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